JP2762183B2 - Method for manufacturing silicon substrate - Google Patents
Method for manufacturing silicon substrateInfo
- Publication number
- JP2762183B2 JP2762183B2 JP3265366A JP26536691A JP2762183B2 JP 2762183 B2 JP2762183 B2 JP 2762183B2 JP 3265366 A JP3265366 A JP 3265366A JP 26536691 A JP26536691 A JP 26536691A JP 2762183 B2 JP2762183 B2 JP 2762183B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- oxygen
- manufacturing
- precipitates
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 37
- 229910052710 silicon Inorganic materials 0.000 title claims description 37
- 239000010703 silicon Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 34
- 239000001301 oxygen Substances 0.000 claims description 34
- 229910052760 oxygen Inorganic materials 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 13
- 239000002244 precipitate Substances 0.000 description 15
- 230000000694 effects Effects 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 10
- 238000005247 gettering Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 229910001385 heavy metal Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005923 long-lasting effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、シリコン基板の製造方
法に関し、詳しくはデバイス工程中に誘起される欠陥、
不純物等を、デバイスが構成される活性領域から除去す
ることができるようにしたシリコン基板の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon substrate, and more particularly, to a method for manufacturing a silicon substrate.
The present invention relates to a method for manufacturing a silicon substrate capable of removing impurities and the like from an active region where a device is formed.
【０００２】[0002]
【従来の技術】近年、メガビットメモリの量産化に基づ
いてＤＲＡＭ等の半導体素子の高集積化が要求され、シ
リコン基板についてもより一層の高品質化が要望されて
いる。2. Description of the Related Art In recent years, high integration of semiconductor devices such as DRAMs has been demanded based on mass production of megabit memories, and further higher quality silicon substrates have been demanded.
【０００３】従来、ＣＺ単結晶から切り出された単結晶
シリコン基板では、特定の加熱処理が施されている。こ
の加熱処理により、基板表面に無欠陥層（ＤＺ）を、基
板内部に内部領域微小欠陥（Bulk Micro Defect:BMD）
を、それぞれ形成している。この内部領域微小欠陥によ
り、半導体集積回路の製造過程中に侵入する微量の重金
属、例えば鉄、ニッケル、銅等を析出させている。イン
トリンシック・ゲッタリング（ＩＧ）効果を積極的に利
用しているものである。そして、その結果として、半導
体装置の歩留まりの向上、例えばｐｎ接合のリーク電流
の減少、キャリアのライフタイムの向上等を図ってい
る。Conventionally, a single crystal silicon substrate cut from a CZ single crystal has been subjected to a specific heat treatment. By this heat treatment, a defect-free layer (DZ) is formed on the substrate surface, and an internal area minute defect (Bulk Micro Defect: BMD) is formed inside the substrate.
Are formed respectively. Due to the minute defects in the internal region, a minute amount of heavy metal, for example, iron, nickel, copper, or the like that invades during the manufacturing process of the semiconductor integrated circuit is deposited. It uses the intrinsic gettering (IG) effect positively. As a result, the yield of the semiconductor device is improved, for example, the leakage current of the pn junction is reduced, and the lifetime of the carrier is improved.
【０００４】この場合、ＩＧ効果には、単結晶シリコン
基板中に含有されている酸素（［Ｏi］：格子間に存在
する酸素）濃度が関連する。すなわち、結晶成長時、坩
堝や雰囲気から混入し、単結晶シリコン中に溶解してい
る過剰の酸素（高酸素）は、高温処理、例えば１１００
〜１１５０℃程度の熱処理を行い、基板中の酸素を外方
拡散させている。このことにより、酸素濃度が低下した
領域内の一部を最終的にＤＺに形成するものである。次
に、低温処理、例えば９００℃以下の熱処理を行い、基
板内部に酸素が析出し、その析出箇所の周囲に結晶欠陥
を形成する。この形成により、結晶格子に歪が生じ、ゲ
ッタリング源として作用し、重金属等が析出するもので
ある。In this case, the IG effect is related to the concentration of oxygen ([Oi]: oxygen existing between lattices) contained in the single crystal silicon substrate. That is, during crystal growth, excess oxygen (high oxygen) mixed from the crucible or atmosphere and dissolved in the single crystal silicon is treated at a high temperature, for example, 1100.
A heat treatment of about 1150 ° C. is performed to diffuse oxygen in the substrate outward. As a result, a part of the region where the oxygen concentration is reduced is finally formed in the DZ. Next, a low-temperature treatment, for example, a heat treatment at 900 ° C. or lower is performed to deposit oxygen inside the substrate and form crystal defects around the deposition location. This formation causes distortion in the crystal lattice, acts as a gettering source, and precipitates heavy metals and the like.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のＩＧ処理では、シリコン結晶中に固溶する酸
素の濃度が低いシリコン基板では、酸素析出物が発生し
難いものであった。また、ＤＺ（デバイス形成領域）を
形成するための上記高温処理により、酸素析出物の核も
縮小してしまう。このため、低酸素濃度のシリコン基板
については十分な量のゲッタリング源の確保が難しかっ
た。すなわち、従来のＩＧ処理は、主に高酸素濃度のシ
リコン基板にのみ用いられ、低酸素濃度のシリコン基板
には用いられていなかった。換言すると、低酸素濃度の
シリコン基板については十分なＩＧ効果を備えることは
できなかった。However, in such a conventional IG process, oxygen precipitates are hardly generated on a silicon substrate having a low concentration of oxygen dissolved in a silicon crystal. In addition, the high-temperature treatment for forming the DZ (device formation region) also reduces the nuclei of oxygen precipitates. For this reason, it has been difficult to secure a sufficient amount of a gettering source for a silicon substrate having a low oxygen concentration. That is, the conventional IG process is mainly used only for a silicon substrate having a high oxygen concentration, and is not used for a silicon substrate having a low oxygen concentration. In other words, a silicon substrate having a low oxygen concentration could not have a sufficient IG effect.
【０００６】[0006]
【発明の目的】本発明の目的は、低酸素濃度のシリコン
基板においても十分なＩＧ効果を得ることのできるシリ
コン基板の製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a silicon substrate which can obtain a sufficient IG effect even on a silicon substrate having a low oxygen concentration.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
になされた本発明のシリコン基板の製造方法において
は、７.５×１０17ａｔｏｍｓ／ｃｍ3以下の格子間酸素
を含有している単結晶シリコン基板を準備する工程と、
この単結晶シリコン基板の裏面に多結晶シリコン膜を形
成する工程と、このシリコン基板を１２００℃以上で３
０分間以上熱処理する工程と、このシリコン基板を１０
００℃以下で２時間以上熱処理する工程と、を有してい
る。In order to achieve the above object, a method of manufacturing a silicon substrate according to the present invention is directed to a method for producing a silicon substrate containing at least 7.5 × 10 17 atoms / cm 3 of interstitial oxygen. Preparing a crystalline silicon substrate;
Forming a polycrystalline silicon film on the back surface of the single crystal silicon substrate;
Heat-treating the silicon substrate for 10 minutes or more,
Heat treating at a temperature of not more than 00 ° C. for 2 hours or more.
【０００８】[0008]
【作用】上記のように構成されたシリコン基板の製造方
法では、７.５×１０17ａｔｏｍｓ／ｃｍ3以下の格子間
酸素を含有している低酸素濃度の単結晶シリコン基板の
裏面に、例えばＣＶＤ法（化学気相成長法）により、多
結晶シリコン膜を形成する。そして、このシリコン基板
に上記２段階の熱処理を施す。この１２００℃以上の熱
処理と１０００℃以下の熱処理とにより、低酸素濃度の
シリコン基板にあってもそのシリコン基板の内部に形成
される酸素析出物の核の成長が助長される。すなわち、
十分な量のゲッタリング源をシリコン基板の内部に確保
することができるものである。In the method of manufacturing a silicon substrate configured as described above, for example, the back surface of a low-oxygen-concentration single-crystal silicon substrate containing 7.5 × 10 17 atoms / cm 3 or less of interstitial oxygen is formed on the back surface. A polycrystalline silicon film is formed by a CVD method (chemical vapor deposition). Then, the silicon substrate is subjected to the two-stage heat treatment. The heat treatment at 1200 ° C. or higher and the heat treatment at 1000 ° C. or lower promotes the growth of nuclei of oxygen precipitates formed inside the silicon substrate even in the case of a low oxygen concentration silicon substrate. That is,
It is possible to secure a sufficient amount of gettering source inside the silicon substrate.
【０００９】[0009]
【実施例】以下、本発明に係るシリコン基板の製造方法
の実施例について、図面を参照して説明する。図１は本
発明の一実施例に係るシリコン基板の製造方法の工程を
示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a silicon substrate according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing steps of a method for manufacturing a silicon substrate according to one embodiment of the present invention.
【００１０】図１（ａ）、（ｂ）に示すように、まず、
７.５×１０17ａｔｏｍｓ／ｃｍ3（ＪＥＩＤＡ）の格子
間酸素を含んだ単結晶シリコン基板１を準備し、この単
結晶シリコン基板１の裏面（図中の上面）に、例えばＳ
ｉＨ4ガスを用い６２０℃の温度にて通常のＣＶＤ法に
よって、多結晶シリコン膜２を１.５μｍの厚さに被着
し、シリコン基板３を得る。As shown in FIGS. 1A and 1B, first,
A single-crystal silicon substrate 1 containing interstitial oxygen of 7.5 × 10 17 atoms / cm 3 (JEIDA) is prepared, and for example, S
A polycrystalline silicon film 2 is deposited to a thickness of 1.5 μm by a normal CVD method at a temperature of 620 ° C. using iH 4 gas to obtain a silicon substrate 3.
【００１１】このようにして準備したシリコン基板３
に、例えば１２００℃、１時間の高温熱処理を施す（図
１（ｃ））。次に、このシリコン基板３に例えば５５０
℃、４８時間の低温熱処理を加える（図１（ｄ））。こ
の結果、単結晶シリコン基板１内部に、酸素析出物の核
４（図１（ｄ）中×印）が成長する。そして、多結晶シ
リコン膜２と単結晶シリコン基板１との界面近傍におい
ては、酸素析出物の発生量が多くなる。次に、析出物を
顕在化させるために、１０００℃、２４時間の熱処理を
施す。そして、表１は、光顕微鏡の観察により求めた酸
素析出物の密度を示している。酸素濃度の同じ単結晶シ
リコン基板に、多結晶シリコン膜２を被着した場合と、
被着しない場合とを比較して示している。The silicon substrate 3 thus prepared
Is subjected to a high-temperature heat treatment at, for example, 1200 ° C. for one hour (FIG. 1C). Next, 550, for example, is
A low-temperature heat treatment at 48 ° C. for 48 hours is applied (FIG. 1D). As a result, nuclei 4 of oxygen precipitates (indicated by x in FIG. 1D) grow inside the single crystal silicon substrate 1. In the vicinity of the interface between the polycrystalline silicon film 2 and the single-crystal silicon substrate 1, the amount of generated oxygen precipitates increases. Next, heat treatment is performed at 1000 ° C. for 24 hours to make the precipitates visible. Table 1 shows the density of oxygen precipitates obtained by observation with a light microscope. A case where the polycrystalline silicon film 2 is deposited on a single crystal silicon substrate having the same oxygen concentration;
This is shown in comparison with the case where no attachment is made.
【００１２】[0012]
【表１】 [Table 1]
【００１３】この表より、低酸素濃度のシリコン基板に
あっても、多結晶シリコン膜をその裏面に形成すること
により、そのシリコン基板の内部に形成される酸素析出
物の核の成長が助長されることがわかる。すなわち、十
分な量のゲッタリング源をシリコン基板の内部に確保す
ることができる。この場合、この酸素析出物の周囲に形
成される歪はゲッタリング源として機能することとな
る。すなわち、このシリコン基板３は十分なＩＧ効果を
有することとなる。例えば、その後のデバイス形成工程
において、これらの歪に重金属等が析出される結果とな
る。According to this table, even when the silicon substrate has a low oxygen concentration, the growth of nuclei of oxygen precipitates formed inside the silicon substrate is promoted by forming the polycrystalline silicon film on the back surface. You can see that That is, it is possible to secure a sufficient amount of the gettering source inside the silicon substrate. In this case, the strain formed around the oxygen precipitate functions as a gettering source. That is, the silicon substrate 3 has a sufficient IG effect. For example, in a subsequent device forming process, heavy metals and the like are precipitated due to these strains.
【００１４】また、このシリコン基板３にあっては、多
結晶シリコン膜２の結晶粒界はＥＧ（エクストリンシッ
ク・ゲッタリング）源として作用する。なお、この多結
晶シリコン膜２は、デバイス形成工程にあって酸化工程
等を繰り返すと、それの一部が酸化により消費された
り、多結晶シリコンの再結晶化が起こる。しかし、多結
晶シリコン膜２のこの様な変化が起きても、上記酸素析
出物の成長に起因して、積層欠陥などの二次欠陥がこの
酸素析出物の近傍に高密度に発生し、これが強力なゲッ
ター源として作用し、不純物等を析出させる。つまり、
ゲッター効果が強力で長持ちし、クリーンである。In the silicon substrate 3, the crystal grain boundaries of the polycrystalline silicon film 2 act as an EG (extrinsic gettering) source. When the oxidation process or the like is repeated in the device forming process, a part of the polycrystalline silicon film 2 is consumed by oxidation or the polycrystalline silicon is recrystallized. However, even if such a change of the polycrystalline silicon film 2 occurs, secondary defects such as stacking faults are generated at high density near the oxygen precipitates due to the growth of the oxygen precipitates. It acts as a powerful getter source and precipitates impurities and the like. That is,
Getter effect is strong, long lasting and clean.
【００１５】さらに、出発原料の単結晶シリコン基板１
の酸素濃度が、従来のＩＧ効果を有する高酸素シリコン
基板より低いので、より完全なＤＺ（無欠陥層）５をシ
リコン基板３の表面（デバイス活性領域）に実現でき
る。また、不純物等のゲッタリング源も、酸素析出物の
周囲の歪、多結晶シリコン膜の結晶粒界、積層欠陥等
で、ＩＧ効果に加え、強力で長持ちするＥＧ効果を得る
ことができる。以上の結果、デバイス特性の劣化、製品
の歩留りの低下をなくすことができる。Further, a single-crystal silicon substrate 1 as a starting material
Has a lower oxygen concentration than that of a conventional high oxygen silicon substrate having an IG effect, so that a more complete DZ (defect-free layer) 5 can be realized on the surface (device active region) of the silicon substrate 3. In addition, a gettering source such as an impurity can obtain a strong and long-lasting EG effect in addition to the IG effect due to distortion around the oxygen precipitate, crystal grain boundaries of the polycrystalline silicon film, stacking faults, and the like. As a result, deterioration of device characteristics and reduction of product yield can be prevented.
【００１６】[0016]
【発明の効果】本発明は、以上説明してきたように構成
されているので、格子間酸素濃度の低いシリコン基板に
おいて、十分なＩＧ効果を持つことができる。また、多
結晶シリコン膜によるＥＧ効果を合わせて持つことがで
きる。また、完全なＤＺを得ることができる。そして、
これらの結果として、不純物、重金属等の汚染物質を、
ゲッタリング源に取り込み、基板表面でのデバイス特性
の劣化や、製品歩留りの低下をなくすことができる。Since the present invention is configured as described above, a sufficient IG effect can be obtained on a silicon substrate having a low interstitial oxygen concentration. In addition, the EG effect of the polycrystalline silicon film can be obtained. Further, complete DZ can be obtained. And
As a result of these, impurities, pollutants such as heavy metals,
Incorporation into a gettering source can prevent degradation of device characteristics on the substrate surface and reduction in product yield.
【図１】 本発明の一実施例に係るシリコン基板の製造
方法の工程を示す断面図である。FIG. 1 is a cross-sectional view showing steps of a method for manufacturing a silicon substrate according to one embodiment of the present invention.
１ 単結晶シリコン基板 ２ 多結晶シリコン膜 ３ シリコン基板 ４ 酸素析出物の核 ５ ＤＺ Reference Signs List 1 single-crystal silicon substrate 2 polycrystalline silicon film 3 silicon substrate 4 nucleus of oxygen precipitate 5 DZ
フロントページの続き (72)発明者 堀口 清一 埼玉県大宮市北袋町一丁目297番地 三 菱マテリアル株式会社 中央研究所内 (72)発明者 降屋 久 埼玉県大宮市北袋町一丁目297番地 三 菱マテリアル株式会社 中央研究所内 (72)発明者 島貫 康 埼玉県大宮市北袋町一丁目297番地 三 菱マテリアル株式会社 中央研究所内 審査官 宮崎 園子 (56)参考文献 特開 昭61−24240（ＪＰ，Ａ) 特開 昭63−7636（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/322Continuing from the front page (72) Inventor Seiichi Horiguchi 1-297 Kitabukurocho, Omiya-shi, Saitama Prefecture, Central Research Laboratory (72) Inventor Hisashi Furiya 1-297 Kitabukurocho, Omiya-shi, Saitama, Japan Materials Co., Ltd. Central Research Laboratory (72) Inventor Yasushi Shimanuki Yasushi 1-297 Kitabukurocho, Omiya City, Saitama Prefecture Mitsubishi Materials Co., Ltd. Central Research Laboratory Inspector Sonoko Miyazaki (56) References JP-A-61-24240 (JP, A ) JP-A-63-7636 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/322
Claims (1)
格子間酸素を含有している単結晶シリコン基板を準備す
る工程と、 この単結晶シリコン基板の裏面に多結晶シリコン膜を形
成する工程と、 このシリコン基板を１２００℃以上で３０分間以上熱処
理する工程と、 このシリコン基板を１０００℃以下で２時間以上熱処理
する工程と、を有したことを特徴とするシリコン基板の
製造方法。1. A step of preparing a single crystal silicon substrate containing interstitial oxygen of 7.5 × 10 17 atoms / cm 3 or less, and forming a polycrystalline silicon film on the back surface of the single crystal silicon substrate A method of manufacturing a silicon substrate, comprising: a step of heat-treating the silicon substrate at 1200 ° C. or higher for 30 minutes or more; and a step of heat-treating the silicon substrate at 1000 ° C. or lower for 2 hours or longer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3265366A JP2762183B2 (en) | 1991-09-17 | 1991-09-17 | Method for manufacturing silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3265366A JP2762183B2 (en) | 1991-09-17 | 1991-09-17 | Method for manufacturing silicon substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0574784A JPH0574784A (en) | 1993-03-26 |
| JP2762183B2 true JP2762183B2 (en) | 1998-06-04 |
Family
ID=17416183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3265366A Expired - Fee Related JP2762183B2 (en) | 1991-09-17 | 1991-09-17 | Method for manufacturing silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762183B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275436A (en) * | 1992-03-24 | 1993-10-22 | Shin Etsu Handotai Co Ltd | Heat treatment of silicon wafer |
| JPH0786289A (en) * | 1993-07-22 | 1995-03-31 | Toshiba Corp | Semiconductor silicon wafer and its manufacture |
| JP5188673B2 (en) | 2005-06-09 | 2013-04-24 | 株式会社Ｓｕｍｃｏ | Silicon wafer for IGBT and method for manufacturing the same |
| JP4760729B2 (en) | 2006-02-21 | 2011-08-31 | 株式会社Ｓｕｍｃｏ | Silicon single crystal wafer for IGBT and manufacturing method of silicon single crystal wafer for IGBT |
| US20120049330A1 (en) * | 2009-05-15 | 2012-03-01 | Sumco Corporation | Silicon wafer and method for producing the same |
-
1991
- 1991-09-17 JP JP3265366A patent/JP2762183B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0574784A (en) | 1993-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0635879A2 (en) | Semiconductor silicon wafer and process for producing it | |
| JPS6255697B2 (en) | ||
| JP2004304095A (en) | Silicon wafer, and manufacturing method thereof | |
| TW201003746A (en) | Silicon substrate for solid-state imaging device and method for manufacturing the same | |
| JP3381816B2 (en) | Semiconductor substrate manufacturing method | |
| JP4013276B2 (en) | Manufacturing method of silicon epitaxial wafer | |
| US20090226736A1 (en) | Method of manufacturing silicon substrate | |
| JP2762183B2 (en) | Method for manufacturing silicon substrate | |
| WO2003021660A1 (en) | Production method for anneal wafer and anneal wafer | |
| KR100625822B1 (en) | Silicon wafer and process for producing it | |
| WO2002049091A1 (en) | Anneal wafer manufacturing method and anneal wafer | |
| JPS63227026A (en) | Gettering method for silicon crystal substrate | |
| JPS60247935A (en) | Manufacture of semiconductor wafer | |
| JPH08139295A (en) | Soi substrate | |
| US20020157597A1 (en) | Method for producing silicon epitaxial wafer | |
| JPH11204534A (en) | Manufacture of silicon epitaxial wafer | |
| US5574307A (en) | Semiconductor device and method of producing the same | |
| JP2003188176A (en) | Silicon wafer and its producing method | |
| JP2003100760A (en) | Epitaxial silicon wafer and method for manufacturing the same | |
| JP3294722B2 (en) | Method for manufacturing silicon wafer and silicon wafer | |
| JP2774855B2 (en) | Gettering effect enhanced silicon substrate and method of manufacturing the same | |
| JP2002076005A (en) | Single crystal silicon wafer | |
| JP2762190B2 (en) | Silicon wafer manufacturing method | |
| JP2005050942A (en) | Silicon wafer and manufacturing method therefor | |
| JPS60148127A (en) | Manufacture of semiconductor substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980224 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080327 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090327 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100327 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100327 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110327 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |