JP3381816B2 - A method of manufacturing a semiconductor substrate - Google Patents

A method of manufacturing a semiconductor substrate

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JP3381816B2
JP3381816B2 JP2479696A JP2479696A JP3381816B2 JP 3381816 B2 JP3381816 B2 JP 3381816B2 JP 2479696 A JP2479696 A JP 2479696A JP 2479696 A JP2479696 A JP 2479696A JP 3381816 B2 JP3381816 B2 JP 3381816B2
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epitaxial
temperature
heat treatment
process
substrate
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JPH09199416A (en )
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正隆 宝来
英一 浅山
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三菱住友シリコン株式会社
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【発明の詳細な説明】 【0001】 【発明の属する技術分野】この発明は、半導体基板として利用されるエピタキシャル層を基板上に成長させたエピタキシャルウェーハに係り、エピタキシャル成長を行うプロセス時に特定の熱処理を行い内部欠陥核を導入し、基板内にイントリンシックゲッタリング能を付与した半導体基板製造方法に関する。 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention relates to an epitaxial layer is used as the semiconductor substrate in the epitaxial wafer grown on a substrate, certain heat treatment during the process of performing epitaxial growth introducing performs internal defects nucleus, a method of manufacturing a semiconductor substrate imparted with intrinsic gettering capability in the substrate. 【0002】 【従来の技術】現在シリコン半導体デバイスの高集積化は急速に進行しており、シリコンウェーハに要求される特性はますます厳しくなっている。 [0002] integration of current silicon semiconductor devices has progressed rapidly, characteristics required for the silicon wafer have become more stringent. 高集積化デバイスにおいては、デバイスが形成されるいわゆるデバイス活性領域に結晶欠陥、あるいはドーパント以外の金属不純物が含まれていると、リーク電流の増大などの電気的特性の劣化を招く。 In highly integrated device, the device is a so-called device active region in the crystal defects formed or contains other metal impurities dopant, leading to deterioration of electric characteristics such as increase in leakage current. 【0003】従来、高集積化シリコン半導体デバイスは、CZ法で育成されたCZ−Si基板が用いられてきたが、これらのCZ−Si基板には過飽和の格子間酸素が約10 18 atoms/cm 3のオーダーで含まれており、デバイスプロセスにおいて酸素析出物や転位、積層欠陥などの結晶欠陥が誘起されることはよく知られている。 Conventionally, highly integrated silicon semiconductor devices, although CZ-Si substrate that is grown have been used in the CZ method, the interstitial oxygen supersaturated These CZ-Si substrate is about 10 18 atoms / cm included in the third order, the oxygen precipitates and dislocation, crystal defects such as stacking faults is well known to be induced in the device process. 【0004】しかし、従来、LOCOS形成やWELL [0004] However, conventional, LOCOS formation and WELL
拡散層形成のために1100〜1200℃の高温で数時間の熱処理が行われていたため、基板表面近傍では格子間酸素の外方拡散によって、表面近傍の数10μmには結晶欠陥のない所謂DZ(Denuded Zone) Since the heat treatment for several hours at a high temperature of 1100 to 1200 ° C. for diffusion layer formation it has been performed, by outward diffusion of interstitial oxygen in the vicinity of the surface of the substrate, not on the number 10μm near surface crystal defects called DZ ( Denuded Zone)
層が自然に形成され、ウェーハ表面のデバイス活性領域での結晶欠陥の発生が自然に抑制されていた。 Layer is naturally formed, occurrence of crystal defects in the device active region of the wafer surface have been naturally suppressed. 【0005】しかしながら半導体デバイスの微細化に伴い、WELL形成に高エネルギーイオン注入が用いられ、デバイスプロセスが1000℃以下の低温で行われるようになると、上記の酸素外方拡散が充分に起こらず、表面近傍でのDZ層の形成が困難となってきた。 However with miniaturization of semiconductor devices, high-energy ion implantation is used to WELL formation, the device process is to be performed at a low temperature of 1000 ° C. or less, oxygen outdiffusion above does not occur sufficiently, formation of DZ layer near the surface has become difficult. このために基板の低酸素化が行われてきたが、結晶欠陥の発生を完全に抑制することは困難であった。 While a low-oxygen of the substrate have been made for this, it is difficult to completely suppress the occurrence of crystal defects. 【0006】 【発明が解決しようとする課題】このようなことから、 [Problems that the Invention is to Solve] [0006] For this reason,
結晶欠陥をほぼ完全に含まないエピタキシャル層を基板上に成長させたエピタキシャルウェーハは、今日の高集積化デバイスに多く用いられている。 Epitaxial wafer grown an epitaxial layer containing no crystalline defects almost entirely on the substrate are often used in today's highly integrated devices. しかしながら、結晶の完全性が高いエピタキシャルウェーハを用いても、 However, even with a high epitaxial wafer completion of crystallinity,
その後のデバイス工程におけるエピタキシャル膜の金属不純物汚染はデバイスの特性を悪化させる。 Metal impurity contamination of the epitaxial film in the subsequent device process exacerbates the characteristics of the device. 【0007】従って、金属不純物をデバイス活性領域から離れた場所(シンク)に捕獲させるゲッタリング技術が必要となる。 Accordingly, gettering technique to capture the location (sink) leaving the metal impurities from the device active region is required. 従来は、デバイスプロセスの熱処理中に自然に誘起される酸素起因の結晶欠陥をシンクとするイントリンシックゲッタリング(IG)やサンドブラスト、Si 34膜あるいはPoly−Si膜の成長などによる裏面歪付けに代表されるイクストリンシックゲッタリング(EG)が用いられてきた。 Conventionally, intrinsic gettering (IG) or sandblasting to sink crystal defects of the oxygen due to naturally induced during the thermal treatment of the device process, Si 3 N 4 film or growth backside strain with due the Poly-Si film Ickx intrinsic gettering to be representative (EG) have been used to. 【0008】しかし、エピタキシャル工程では1050 [0008] However, 1050 is an epitaxial process
〜1200℃の高温熱処理が施されるためにCZ−Si CZ-Si for high temperature heat treatment of to 1200 ° C. is performed
基板に内在する酸素析出核が縮小、消滅し、その後のデバイスプロセスにおいて基板内に充分に結晶欠陥を誘起することが困難である。 Oxygen precipitation nuclei reduction inherent in the substrate, disappear, it is difficult to induce sufficient crystal defects in the substrate in the subsequent device process. 従って、デバイスプロセスの初期においてはもちろんのこと、プロセス全体にわたって金属不純物に対するIG効果が低減するという新たな問題が生じた。 Therefore, of course in the initial device process, a new problem IG effect is reduced to metal impurities throughout the process has occurred. 【0009】このためゲッタリング方法としてはEGの他に、エピ工程の前後にウェーハに熱処理を施すことにより故意に生成させた結晶欠陥をシンクとするIGが用いられることになる。 [0009] Thus in addition to the EG as the gettering process, so that the IG is used to sink crystal defects were generated deliberately by heat treatment to the wafer before or after the epitaxial process. この熱処理は基本的に、酸素の外方拡散によりウェーハ表面の酸素濃度を減少させ、デバイス活性領域での酸素析出物の生成を抑制する高温熱処理(1000〜1200℃)、欠陥核生成のための低温熱処理(600〜800℃)および成長のための中温熱処理(800〜1000℃)から構成されており、コストの増大の問題があった。 The heat treatment is basically to reduce the oxygen concentration of the wafer surface by outward diffusion of oxygen to suppress the generation of oxygen precipitates in the device active region a high-temperature heat treatment (1000 to 1200 ° C.), for defect nucleation low-temperature heat treatment is composed of a medium temperature heat treatment for (600 to 800 ° C.) and growth (800 to 1000 ° C.), there was an increase in cost problems. 【0010】また、EG処理においてはコストの問題の他に歪み層からのシリコン片の剥がれによるパーティクルの発生といった問題があった。 Further, there is a problem occurrence of particles due to peel off of the silicon pieces from the strain layer to another cost issue is the EG process. 【0011】この発明は、上述した問題に鑑み、コストを増大させるEGやIG処理を必要とせず、安定した内部IG領域と高い結晶性を有するデバイス活性領域とを合わせ持つ半導体基板製造方法を提供することを目的としている。 [0011] The present invention, in view of the problems mentioned above, without the need for EG and IG treatment increase the cost, stable method for manufacturing a semiconductor substrate having both a device active region having an interior IG area and high crystallinity It is an object of the present invention to provide. 【0012】 【課題を解決するための手段】発明者らは、安定した内部IG領域と高い結晶性を有するデバイス活性領域とを合わせ持つ半導体基板を目的に、内部IG領域の生成について種々検討した結果、エピタキシャル工程において、シリコンウェーハに1150℃以上でエピタキシャル成長をさせた後に、一旦基板を10K/s以上の速度で冷却することにより、基板内に内部IG領域の欠陥核を生成、付与できることを知見し、この発明を完成した。 [0012] Means for Solving the Problems The inventors have found that stable internal IG region and aims semiconductor substrate having both a device active region having a high crystallinity, and various investigations on production of internal IG region result, the epitaxial process, after the epitaxial growth at 1150 ° C. or higher in the silicon wafer, once by cooling the substrate at 10K / s or faster, generating a defect nuclei inside IG region in the substrate, knowledge that can be imparted and, to complete the present invention. 【0013】この発明はシリコン半導体基板に115 [0013] The present invention, in the silicon semiconductor substrate 115
0℃以上でエピタキシャル成長をさせた後、該基板を1 After the epitaxial growth at 0 ℃ above, the substrate 1
0K/s以上の速度で冷却することにより 、基板内にイントリンシックゲッタリング能を付与し、さらに、例えばエピタキシャル成長後に700〜1000℃の温度範囲の前記熱処理を施すことによって、 イントリンシック By cooling at 0K / s or faster, the intrinsic gettering ability was imparted to the substrate, further, by performing the heat treatment in the temperature range of 700 to 1000 ° C. For example, after the epitaxial growth, intrinsic
ゲッタリング能を発揮できる半導体基板を得る製造方法 Manufacturing method for obtaining a semiconductor substrate which can exhibit gettering capability
である It is. 【0014】 【発明の実施の形態】この発明による製造方法は、シリコンウェーハをエピタキシャル成長時に1150℃以上の高温に所定時間保持し、その後、特定の冷却速度で冷却することにより、続く熱処理の際に酸素析出を促進してIG能を付与することを特徴としている。 [0014] manufacturing method according to an embodiment of the Invention The present invention maintains a predetermined time at a high temperature of over 1150 ° C. during the silicon wafer epitaxial growth, followed by cooling at a specific cooling rate, during subsequent heat treatment to promote oxygen precipitation is characterized by imparting IG capability. この現象は、酸素が過飽和に存在する基板内部でのみ起こり、デバイス活性領域となるエピタキシャル層では酸素が存在しないことから起こらないため、極めて高い結晶性を有するエピタキシャル層の品質を劣化させることなく、安定したIG領域と良好な結晶性を有するデバイス活性領域を確保することができる。 This phenomenon, oxygen takes place only inside the substrate present in the supersaturated, because does not occur by the absence of oxygen in the epitaxial layer to be a device active region, without degrading the quality of the epitaxial layer having extremely high crystallinity, it is possible to secure the device active region with stable IG area and good crystallinity. 【0015】この発明において、エピタキシャル成長の処理温度としては、1150℃〜1250℃が望ましく、また、冷却速度は10K/s〜100K/sの範囲が好ましい。 [0015] In the present invention, the treatment temperature of the epitaxial growth, desirably 1150 ° C. to 1250 ° C., also the cooling rate in the range of 10K / s~100K / s is preferred. エピタキシャル成長後の熱処理の際に10 At the time of the heat treatment after the epitaxial growth 10
6 〜10 7 cm -2の高い密度の欠陥を生成させるのに、この温度範囲並びに冷却速度の各下限値が必要であるが、 To thereby generate a defect high 6 to 10 7 cm -2 density, it is necessary that each lower limit of this temperature range and the cooling rate,
各上限値を越えるとシリコンウェーハにスリップや反りが発生するため、上記の範囲が好ましい。 Since the slips and warpage generated in a silicon wafer exceeds the respective upper limit, the above range is preferred. 【0016】この発明によるシリコンウェーハは、エピタキシャル成長後の700〜1000℃の温度範囲での熱処理においては、熱処理温度に依存せず10 6 〜10 7 The silicon wafer according to the present invention, in the heat treatment at a temperature range of 700 to 1000 ° C. after the epitaxial growth, without depending on the heat treatment temperature 10 6 to 10 7
cm -2の高い密度の欠陥が生成することを特徴としている。 It is characterized in that a defect of the high density of cm -2 to produce. このことは、デバイスプロセスの初期に行われる7 This is done early in the device process 7
00〜1000℃での酸化や窒化処理により欠陥を充分に生成させることが可能であり、IG効果がデバイスプロセス全体にわたって維持されることを示している。 00-1000 it is possible to sufficiently generate defects by oxidation or nitriding treatment at ° C., IG effect indicates that it is maintained throughout the device process. 従ってEG処理や、エピ工程の前後に特別に結晶欠陥を生成させるためのIG処理が必要ではなくなるため、この発明は、シリコンウェーハの製造コストの面で極めて有効である。 Thus EG process and, since the IG process for producing specially crystal defects before and after the epitaxial process is not required, the invention is extremely effective in terms of manufacturing cost of the silicon wafer. 【0017】 【実施例】試料としてボロン添加量により抵抗率を変化させた5種類(抵抗率;4mΩcm、7mΩcm、11 [0017] EXAMPLES 5 kinds of changing the resistivity of the boron addition amount as a sample (resistivity; 4mΩcm, 7mΩcm, 11
mΩcm、50mΩcm、500mΩcm)のP型(1 mΩcm, 50mΩcm, 500mΩcm) P-type (1
00)8インチCZ−Siウェーハ(酸素濃度;11× 00) 8 inches CZ-Si wafer (oxygen concentration; 11 ×
10 17 atoms/cm 3 )を用いた。 10 17 atoms / cm 3) was used. 【0018】これらの試料をランプ加熱方式の横型CV [0018] The horizontal CV of these samples lamp heating system
Dエピタキシャル装置により、水素雰囲気中で1150 The D epitaxial device, 1150 in a hydrogen atmosphere
℃で60秒間ベーキングを行った後、堆積処理を行った。 After the 60 seconds baking was carried out at ° C., subjected to deposition process. 堆積処理はトリクロロシランを原料ガスとして用い、1100℃、1150℃、1200℃の3種類の温度で180秒間堆積処理を行い、約3μmのエピタキシャル層を堆積させた。 Deposition process using trichlorosilane as a raw material gas, 1100 ℃, 1150 ℃, performed for 180 seconds deposition process in three temperature 1200 ° C., it was deposited epitaxial layer of about 3 [mu] m. 【0019】堆積後、各温度から5K/s、10K/ [0019] After the deposition, 5K / s from each temperature, 10K /
s、15K/sの3種類の速度で冷却した。 s, and cooled in three types of speed of 15K / s. その後、乾燥酸素雰囲気中で1000℃で16時間の熱処理並びに次に示す2段階熱処理を行った。 Thereafter, heat treatment was carried out as well as two-stage heat treatment in the following 16 hours at 1000 ° C. in a dry oxygen atmosphere. すなわち、700℃、 In other words, 700 ℃,
800℃、900℃の各温度でそれぞれ4時間ずつ熱処理をした後、1000℃で16時間熱処理を施した。 800 ° C., after the heat treatment by each 4 hours at each temperature of 900 ° C., was subjected to 16 hours heat treatment at 1000 ° C.. 【0020】これらの熱処理試料について、ライトエッチングを行い、光学顕微鏡により観察を行った。 [0020] These heat treated samples, perform light etching, it was observed by optical microscopy. 観察結果を図1〜図3に示し、堆積処理温度がそれぞれ110 The observation results shown in FIGS. 1 to 3, the deposition process temperature is respectively 110
0℃、1150℃、1200℃の場合を示している。 0 ℃, 1150 ℃, shows a case of 1200 ℃. 各図において、各A図は堆積処理後の冷却速度が5K/ In each figure, each A diagram cooling rate after the deposition process is 5K /
s、各B図は10K/s、各C図は15K/sの場合であり、グラフの縦軸は欠陥密度、横軸はエピタキシャル工程後の2段階熱処理における、1段目の熱処理温度を示しており、1000℃での1段階熱処理の結果は図中黒印で示している。 s, each B diagram 10K / s, each C Figure is a case of 15K / s, the vertical axis represents the defect density of the graph, the horizontal axis in the two-stage heat treatment after epitaxial step, it shows the heat treatment temperature in the first stage and, one step the result of heat treatment at 1000 ° C. is shown in black marks in FIG. 【0021】図1〜図3から明らかなように、エピタキシャル堆積処理温度が1100℃のとき、並びに115 As it is apparent from FIGS. 1 to 3, when an epitaxial deposition process temperature is 1100 ° C., and 115
0℃と1200℃で処理した後5K/sで冷却したときでは、エピタキシャル後の1段目の熱処理温度が増大するに伴い欠陥密度は減少する。 0 ℃ and when cooled with 5K / s after treatment with 1200 ° C., the defect density with the heat treatment temperature of the first stage after the epitaxial increases is reduced. これは、エピタキシャル堆積処理およびエピタキシャル後の1段目の熱処理を施すことにより、それぞれの温度で存在可能な臨界サイズ以下の微小欠陥が縮小、消滅し、次の1000℃での熱処理において臨界サイズ以上の核のみが成長したものである。 This is by applying a first-stage heat treatment after epitaxial deposition process and an epitaxial, critical size following micro defects that can exist at each temperature is reduced, eliminated, or critical size in the heat treatment in the next 1000 ° C. one in which only the nucleus has grown. これらの試料では欠陥密度は低くIG効果は期待されない。 Defect density is low IG effect in these samples is not expected. 【0022】これに対して図2、図3に示すごとく、エピタキシャル堆積処理温度が1150℃並びに1200 [0022] Figure 2 contrast, as shown in FIG. 3, an epitaxial deposition process temperature is 1150 ° C. and 1200
℃で、10K/sおよび15K/sで冷却したときでは、全ての抵抗率の試料においてエピタキシャル後の1 At ° C., in the when cooled at 10K / s and 15K / s, 1 after the epitaxial in a sample of all the resistivity
段目の熱処理温度にかかわらず、さらには低温での核生成処理を含まない1000℃での1段階熱処理でも欠陥密度は10 6 〜10 7 cm -2の高い値を示している。 Regardless heat treatment temperature of stage, more defect density in a single step heat treatment at 1000 ° C. without the nucleation process at low temperature shows high values of 10 6 ~10 7 cm -2. これは、1150℃と1200℃でのエピタキシャル堆積処理では、1100℃よりも多くの欠陥核が消滅するものの、この温度から10K/s以上の速度で冷却することにより、エピタキシャル後の熱処理での欠陥生成が増大したものと考えられる。 This defect in the epitaxial deposition process at 1150 ° C. and 1200 ° C., although than 1100 ° C. A number of defect nuclei disappear, by cooling at 10K / s or faster from the temperature, the heat treatment after epitaxial it is considered that generation has increased. 【0023】 【発明の効果】実施例から明らかなように、1150℃ As is apparent from the examples according to the present invention, 1150 ° C.
以上の高温でエピタキシャル堆積処理を施した後に10 10 after performing epitaxial deposition process at a temperature higher than
K/s以上の速度で冷却することで、高密度の内部欠陥を発生させ、IG効果を増大させることができた。 By cooling in K / s or faster, to generate high-density internal defects, we were possible to increase the IG effect. すなわち、エピタキシャル工程の高温熱処理による酸素の外方拡散によりデバイス活性領域が充分に確保されること、ならびに欠陥密度は高温から急冷した後の析出処理温度に大きな依存性がないことを考えると、エピタキシャル工程において高温からの急冷処理を施すことにより、デバイスプロセスにおける初期の700〜1000 That is, the device active region is sufficiently ensured by oxygen outdiffusion by high-temperature heat treatment in the epitaxial process, and the defect density considering that there is no significant dependence on the precipitation treatment temperature after rapid cooling from a high temperature, epitaxial by performing quenching from high temperatures in the process, the initial in the device process 700 to 1000
℃のプロセスにおいて充分に欠陥の生成が可能であり、 It is possible sufficiently the generation of defects at ℃ process,
EG処理や特別に結晶欠陥を生成させるためのIG処理を施さなくても、デバイスプロセス全体を通じてゲッタリング効果の維持が可能となる。 Even without applying the IG process to EG treatment and generating a special crystal defects, it is possible to maintain the gettering effect throughout the device process.

【図面の簡単な説明】 【図1】エピタキシャル工程での堆積処理温度及び冷却速度が欠陥密度に及ぼす影響を示すグラフであり、縦軸は欠陥密度、横軸はエピタキシャル工程後の2段階熱処理における1段目の熱処理温度を示し、Aは堆積処理後の冷却速度が5K/s、Bは10K/s、Cは15K/ Deposition treatment temperature and cooling rate in the BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] epitaxial step is a graph showing the effect on the defect density and the vertical axis defect density and the horizontal axis in the two-stage heat treatment after epitaxial step shows the heat treatment temperature in the first stage, a cooling rate after the deposition process is 5K / s, B is 10K / s, C is 15K /
sの場合で、いずれも堆積処理温度が1100℃の場合である。 In case of s, either the deposition process temperature is the case of 1100 ° C.. 【図2】エピタキシャル工程での堆積処理温度及び冷却速度が欠陥密度に及ぼす影響を示すグラフであり、縦軸は欠陥密度、横軸はエピタキシャル工程後の2段階熱処理における1段目の熱処理温度を示し、Aは堆積処理後の冷却速度が5K/s、Bは10K/s、Cは15K/ [Figure 2] deposition process temperature and the cooling rate in the epitaxial step is a graph showing the effect on the defect density and the vertical axis defect density, the horizontal axis represents the heat treatment temperature of the first stage in the two-stage heat treatment after epitaxial step shown, the cooling rate after a deposition process 5K / s, B is 10K / s, C is 15K /
sの場合で、いずれも堆積処理温度が1150℃の場合である。 In case of s, either the deposition process temperature is the case of 1150 ° C.. 【図3】エピタキシャル工程での堆積処理温度及び冷却速度が欠陥密度に及ぼす影響を示すグラフであり、縦軸は欠陥密度、横軸はエピタキシャル工程後の2段階熱処理における1段目の熱処理温度を示し、Aは堆積処理後の冷却速度が5K/s、Bは10K/s、Cは15K/ [3] the deposition process temperature and the cooling rate in the epitaxial step is a graph showing the effect on the defect density and the vertical axis defect density, the horizontal axis represents the heat treatment temperature of the first stage in the two-stage heat treatment after epitaxial step shown, the cooling rate after a deposition process 5K / s, B is 10K / s, C is 15K /
sの場合で、いずれも堆積処理温度が1200℃の場合である。 In case of s, either the deposition process temperature is the case of 1200 ° C..

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平7−22429(JP,A) 特開 昭59−54220(JP,A) 特開 平3−77330(JP,A) 特開 平5−155700(JP,A) (58)調査した分野(Int.Cl. 7 ,DB名) H01L 21/322 ────────────────────────────────────────────────── ─── of the front page continued (56) reference Patent flat 7-22429 (JP, a) JP Akira 59-54220 (JP, a) JP flat 3-77330 (JP, a) JP flat 5 155700 (JP, a) (58 ) investigated the field (Int.Cl. 7, DB name) H01L 21/322

Claims (1)

  1. (57)【特許請求の範囲】 【請求項1】 シリコン半導体基板に1150℃以上でエピタキシャル成長をさせた後、該基板を10K/s以上の速度で冷却し、基板内にイントリンシックゲッタリング能を付与した半導体基板の製造方法。 (57) After epitaxial growth in [Claims 1. A silicon semiconductor substrate 1150 ° C. or higher, the substrate was cooled at 10K / s or faster, the intrinsic gettering ability in the substrate manufacturing method of imparting a semiconductor substrate. 【請求項2】 請求項において、エピタキシャル成長後の熱処理の温度範囲が700〜1000℃である半導体基板の製造方法。 2. The method of claim 1, a semiconductor substrate manufacturing method of the temperature range of heat treatment after epitaxial growth is 700 to 1000 ° C..
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US5994761A (en) 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
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US6828690B1 (en) 1998-08-05 2004-12-07 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
DE69933777T2 (en) 1998-09-02 2007-09-13 Memc Electronic Materials, Inc. A process for producing a silicon wafer with ideal sauerstoffausfällungsverhalten
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
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US6284384B1 (en) * 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
WO2002084728A1 (en) 2001-04-11 2002-10-24 Memc Electronic Materials, Inc. Control of thermal donor formation in high resistivity cz silicon
US6955718B2 (en) 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
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