JP3381816B2 - Semiconductor substrate manufacturing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an epitaxial wafer in which an epitaxial layer used as a semiconductor substrate is grown on a substrate, and an internal defect nucleus is introduced by performing a specific heat treatment during the process of epitaxial growth. the method of manufacturing a semiconductor substrate imparted with intrinsic gettering capability to.

[0002]

2. Description of the Related Art Currently, high integration of silicon semiconductor devices is rapidly progressing, and characteristics required for silicon wafers are becoming more and more severe. In a highly integrated device, if a so-called device active region in which the device is formed contains a crystal defect or a metal impurity other than a dopant, electrical characteristics such as an increase in leak current are deteriorated.

Conventionally, a CZ-Si substrate grown by the CZ method has been used for a highly integrated silicon semiconductor device. However, supersaturated interstitial oxygen of about 10 ¹⁸ atoms / cm 3 is used for these CZ-Si substrates. It is included in the order of ³ , and it is well known that crystal defects such as oxygen precipitates, dislocations, and stacking faults are induced in the device process.

However, conventionally, LOCOS formation and WELL
Since heat treatment was performed at a high temperature of 1100 to 1200 ° C. for several hours to form a diffusion layer, so-called DZ (crystal defect not present in several tens of μm near the surface due to outward diffusion of interstitial oxygen near the surface of the substrate). Denuded Zone)
The layer was formed naturally, and the generation of crystal defects in the device active region on the wafer surface was naturally suppressed.

However, with the miniaturization of semiconductor devices, when high-energy ion implantation is used for WELL formation and the device process is performed at a low temperature of 1000 ° C. or lower, the above oxygen outward diffusion does not sufficiently occur, It has become difficult to form the DZ layer near the surface. For this reason, the oxygen of the substrate has been lowered, but it has been difficult to completely suppress the generation of crystal defects.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Epitaxial wafers obtained by growing an epitaxial layer containing almost no crystal defects on a substrate are widely used in today's highly integrated devices. However, even if an epitaxial wafer with high crystal perfection is used,
Contamination of metal impurities in the epitaxial film in the subsequent device process deteriorates the device characteristics.

Therefore, a gettering technique for trapping metal impurities at a location (sink) away from the device active region is required. Conventionally, back surface straining is caused by intrinsic gettering (IG) or sand blast, which uses crystal defects caused by oxygen that are naturally induced during heat treatment of a device process as a sink, growth of Si ₃ N ₄ film or Poly-Si film, etc. Extrinsic gettering (EG) has been used.

However, in the epitaxial process, 1050
CZ-Si due to high temperature heat treatment of ~ 1200 ° C
Oxygen precipitation nuclei existing in the substrate shrink and disappear, and it is difficult to sufficiently induce crystal defects in the substrate in the subsequent device process. Therefore, a new problem arises that the IG effect on metal impurities is reduced not only in the initial stage of the device process but also throughout the process.

For this reason, as the gettering method, in addition to EG, an IG in which a crystal defect intentionally generated by heat-treating the wafer before and after the epi step is used as a sink is used. This heat treatment is basically a high-temperature heat treatment (1000 to 1200 ° C.) for reducing the oxygen concentration on the wafer surface by outward diffusion of oxygen and suppressing the formation of oxygen precipitates in the device active region. It is composed of a low temperature heat treatment (600 to 800 ° C.) and a medium temperature heat treatment for growth (800 to 1000 ° C.), which causes a problem of cost increase.

In addition to the cost problem, the EG process has a problem that particles are generated due to peeling of silicon pieces from the strained layer.

[0011] The present invention, in view of the problems mentioned above, without the need for EG and IG treatment increase the cost, stable method for manufacturing a semiconductor substrate having both a device active region having an interior IG area and high crystallinity It is intended to be provided.

[0012]

The inventors of the present invention have variously studied the generation of the internal IG region for the purpose of a semiconductor substrate having both a stable internal IG region and a device active region having high crystallinity. In the process, it was found that after the epitaxial growth of the silicon wafer at 1150 ° C. or higher, the substrate is once cooled at a rate of 10 K / s or higher, whereby defect nuclei in the internal IG region can be generated and imparted, Completed the invention.

The present invention provides a silicon semiconductor substrate 115.
After epitaxial growth at 0 ° C or higher, the substrate is
By cooling at 0K / s or faster, the intrinsic gettering ability was imparted to the substrate, further, by performing the heat treatment in the temperature range of 700 to 1000 ° C. For example, after the epitaxial growth, intrinsic
Manufacturing method for obtaining semiconductor substrate capable of exerting gettering ability
Is .

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION According to the manufacturing method of the present invention, a silicon wafer is kept at a high temperature of 1150 ° C. or higher for a predetermined time during epitaxial growth, and then cooled at a specific cooling rate to prevent oxygen precipitation during the subsequent heat treatment. It is characterized by promoting and imparting IG capability. This phenomenon occurs only inside the substrate in which oxygen is supersaturated, and does not occur from the absence of oxygen in the epitaxial layer that becomes the device active region, without degrading the quality of the epitaxial layer having extremely high crystallinity. It is possible to secure a stable IG region and a device active region having good crystallinity.

In the present invention, the processing temperature for epitaxial growth is preferably 1150 ° C. to 1250 ° C., and the cooling rate is preferably 10 K / s to 100 K / s. 10 during heat treatment after epitaxial growth
^In order to generate high density defects of ⁶ to 10 ⁷ cm ^-2 , each lower limit of this temperature range and cooling rate is necessary.
If the respective upper limits are exceeded, the silicon wafer will slip or warp, so the above range is preferred.

The silicon wafer according to the present invention, in the heat treatment in the temperature range of 700 to 1000 ° C. after epitaxial growth, does not depend on the heat treatment temperature and is 10 ⁶ to 10 ⁷
It is characterized in that defects with a high density of cm ⁻² are generated. This is done early in the device process.
It is possible to sufficiently generate defects by the oxidation or nitriding treatment at 00 to 1000 ° C., which shows that the IG effect is maintained throughout the device process. Therefore, the present invention is extremely effective in terms of the manufacturing cost of the silicon wafer, because the EG process and the IG process for generating crystal defects before and after the epitaxial process are not required.

[0017]

[Embodiment] Five kinds of samples having different resistivities depending on the added amount of boron (resistivity: 4 mΩcm, 7 mΩcm, 11
mΩcm, 50mΩcm, 500mΩcm) P type (1
00) 8-inch CZ-Si wafer (oxygen concentration; 11 ×
10 ¹⁷ atoms / cm ³ ) was used.

These samples are used as a lamp heating type horizontal CV.
1150 in hydrogen atmosphere by D epitaxial device
After baking at 60 ° C. for 60 seconds, a deposition process was performed. In the deposition process, trichlorosilane was used as a source gas, and the deposition process was performed for 180 seconds at three temperatures of 1100 ° C., 1150 ° C. and 1200 ° C. to deposit an epitaxial layer of about 3 μm.

After the deposition, from each temperature, 5K / s, 10K / s
Cooling was performed at three different speeds, s and 15 K / s. After that, heat treatment was performed at 1000 ° C. for 16 hours in a dry oxygen atmosphere and the following two-step heat treatment was performed. That is, 700 ° C,
After heat treatment was performed for 4 hours at each temperature of 800 ° C. and 900 ° C., heat treatment was performed for 16 hours at 1000 ° C.

Light-etching was performed on these heat-treated samples, and the samples were observed with an optical microscope. The observation results are shown in FIG. 1 to FIG.
The case of 0 ° C., 1150 ° C. and 1200 ° C. is shown. In each figure, each A figure has a cooling rate of 5K /
s, each B diagram is 10 K / s, each C diagram is 15 K / s, the vertical axis of the graph shows the defect density, and the horizontal axis shows the first-stage heat treatment temperature in the two-stage heat treatment after the epitaxial process. The results of the one-step heat treatment at 1000 ° C. are indicated by black marks in the figure.

As is apparent from FIGS. 1 to 3, when the epitaxial deposition processing temperature is 1100 ° C. and 115
When treated at 0 ° C. and 1200 ° C. and then cooled at 5 K / s, the defect density decreases as the first stage heat treatment temperature after epitaxial increases. This is because by performing the epitaxial deposition process and the first-stage heat treatment after the epitaxial growth, micro defects smaller than or equal to the critical size that can exist at each temperature are reduced and eliminated, and in the next heat treatment at 1000 ° C. Only the nucleus of has grown. In these samples, the defect density is low and the IG effect is not expected.

On the other hand, as shown in FIGS. 2 and 3, the epitaxial deposition treatment temperature is 1150 ° C. and 1200 ° C.
When cooled at 10 K / s and 15 K / s at a temperature of 1 ° C after the epitaxial growth in all resistivity samples.
Irrespective of the heat treatment temperature of the first step, the defect density shows a high value of 10 ⁶ to 10 ⁷ cm ⁻² even in the one-step heat treatment at 1000 ° C. not including the nucleation treatment at a low temperature. In the epitaxial deposition treatment at 1150 ° C. and 1200 ° C., more defect nuclei than 1100 ° C. disappear, but by cooling from this temperature at a rate of 10 K / s or more, defects in the heat treatment after epitaxial growth It is considered that the production was increased.

[0023]

As is apparent from the examples, the temperature is 1150 ° C.
After performing the epitaxial deposition treatment at the above high temperature, 10
By cooling at a rate of K / s or higher, high density internal defects were generated and the IG effect could be increased. That is, considering that the device active region is sufficiently secured by the outward diffusion of oxygen by the high temperature heat treatment in the epitaxial process, and that the defect density does not largely depend on the precipitation treatment temperature after quenching from high temperature, By performing the quenching process from a high temperature in the process, the initial 700 to 1000 in the device process
It is possible to generate enough defects in the process of ℃,
It is possible to maintain the gettering effect throughout the device process without performing EG treatment or IG treatment for generating crystal defects.

[Brief description of drawings]

FIG. 1 is a graph showing the influence of a deposition treatment temperature and a cooling rate in an epitaxial process on defect density, where the vertical axis represents the defect density and the horizontal axis represents the first-stage heat treatment temperature in the two-stage heat treatment after the epitaxial process. The cooling rate after the deposition process is 5 K / s, B is 10 K / s, and C is 15 K / s.
In the case of s, the deposition processing temperature is 1100 ° C. in all cases.

FIG. 2 is a graph showing the influence of the deposition processing temperature and cooling rate in the epitaxial process on the defect density, where the vertical axis represents the defect density and the horizontal axis represents the first-stage heat treatment temperature in the two-stage heat treatment after the epitaxial process. The cooling rate after the deposition process is 5 K / s, B is 10 K / s, and C is 15 K / s.
In all cases, the deposition processing temperature is 1150 ° C.

FIG. 3 is a graph showing the influence of the deposition processing temperature and cooling rate in the epitaxial process on the defect density, where the vertical axis represents the defect density and the horizontal axis represents the first-stage heat treatment temperature in the two-stage heat treatment after the epitaxial process. The cooling rate after the deposition process is 5 K / s, B is 10 K / s, and C is 15 K / s.
In all cases, the deposition processing temperature is 1200 ° C.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-22429 (JP, A) JP-A-59-54220 (JP, A) JP-A-3-77330 (JP, A) JP-A-5- 155700 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/322

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor substrate in which a silicon semiconductor substrate is epitaxially grown at 1150 ° C. or higher and then cooled at a rate of 10 K / s or higher to impart intrinsic gettering ability to the substrate. 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the temperature range of the heat treatment after the epitaxial growth is 700 to 1000 ° C.