JPS5994809A - Production of semiconductor element - Google Patents

Production of semiconductor element

Info

Publication number
JPS5994809A
JPS5994809A JP20480782A JP20480782A JPS5994809A JP S5994809 A JPS5994809 A JP S5994809A JP 20480782 A JP20480782 A JP 20480782A JP 20480782 A JP20480782 A JP 20480782A JP S5994809 A JPS5994809 A JP S5994809A
Authority
JP
Japan
Prior art keywords
substrate
epitaxial layer
heat treatment
concentration
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20480782A
Other languages
Japanese (ja)
Inventor
Ritsuo Takizawa
滝沢 律夫
Akira Osawa
大沢 昭
Koichiro Honda
耕一郎 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20480782A priority Critical patent/JPS5994809A/en
Publication of JPS5994809A publication Critical patent/JPS5994809A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • H01L21/02661In-situ cleaning

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To make it possible to produce semiconductor element with minimized minute defect which may appear in the epitaxial layer, by providing a method having the steps of allowing a growth of silicon single crystal layer on a substrate constituted by silicon single crystal in which the oxygen concentration is a specific value in terms of ppma and the carbon concentration is not smaller than 1ppma, and effecting a heat treatment on the silicon single crystal layer. CONSTITUTION:A heat treatment is conducted on a substrate having an oxygen (O) concentration of 25-50ppma and a carbon (C) concentration of 1ppma or higher, at a temperature range 600-800 deg.C within a nitrogen (N2) gas atmosphere. This heat treatment contributes to the minimization of minute defects which may exist in the epitaxial layer. In an example of the method, an epitaxial layer of silicon (Si) is formed on a substrate by a known method such as CVD method, and 700 deg.C-48hr heat treatment is effected on the substrate within a nitrogen (N2) gas atmosphere, following by an element forming step. According to this method, any defect caused in the epitaxial layer is absorbed by minute defect in the substrate, so that the number of defects in the epitaxial layer is diminished to ensure an improved property of the semiconductor element produced by this method.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は半導体素子の製造方法に関する。詳しくは、シ
リコン(Sl)結晶基板上に形成されたシリコン(Sl
)エピタキシャル層中に発生する微小欠陥をその後のイ
ントリンシックゲッタリング法にもとづく工程によりゲ
ッタして除去する工程を含む半導体素子の製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In detail, silicon (Sl) formed on a silicon (Sl) crystal substrate
) A method for manufacturing a semiconductor device including a step of gettering and removing minute defects generated in an epitaxial layer by a subsequent step based on an intrinsic gettering method.

(2)  技術の背景 シリコン(Si)結晶よりなるエピタキシャル屑は、主
としてノ々イボ〜ラデノ々イスに使用されているが、近
年の素子の高集積化に伴ない積層欠陥、転移、微小欠陥
等、結晶欠陥のないものが要求されている。高集積度半
導体素子にあっては動作領域の寸法が極度に小さく、相
対的に結晶欠陥の大きさが無視しえない状態にあり、そ
の影響が看做し難いものとなっているからである。
(2) Background of the technology Epitaxial scraps made of silicon (Si) crystals are mainly used for non-irregular and non-irradiated devices, but as devices become more highly integrated in recent years, stacking faults, dislocations, micro defects, etc. , those without crystal defects are required. This is because in highly integrated semiconductor devices, the dimensions of the operating area are extremely small, and the relative size of crystal defects cannot be ignored, making their effects difficult to ignore. .

ところが、上記のエピタキシャル層中には、積層欠陥、
転位、微小欠陥(シャロービット)等の結晶欠陥が存在
している。そのうち特に問題となっているのは表面近傍
に発生する微小欠陥(シャロービット)〒あり、単位I
n R1t当りの個数にしてto7((1m/α2〕程
度含まれ、これらが続くデ・ぐイスプロセスにおいて大
きな積層欠陥に成長して素子の特性不良等、歩留り低下
の原因となる。
However, in the above epitaxial layer, stacking faults,
Crystal defects such as dislocations and micro defects (shallow bits) are present. Of these, a particular problem is microscopic defects (shallow bits) that occur near the surface, with units of I
The number of defects per nR1t is about to7 ((1 m/α2)), and these will grow into large stacking faults in the subsequent de-glue process, causing poor device characteristics and a decrease in yield.

(3)  従来技術と問題点 そのため従来技術においては、上記の微小欠陥を除去す
るために、基板表面に幾何学的不整状態を形成する、ま
たは、窒化シリコン(st3n4)等の薄膜デポジショ
ンを行なう等の方法により外部から微小欠陥の原因とな
る車金層等をゲッタする方法、いわゆる、エクストリン
シックゲッタリング方法が使用されていたが、ノぐイポ
ーラデ、6イスは製造プロセスが複雑であるため、プロ
セス中にゲッタ効果が消失してしまう場合が多く有効で
あるとは言い雛い。
(3) Prior art and problems Therefore, in the prior art, in order to remove the above-mentioned micro defects, a geometrical irregularity is formed on the substrate surface, or a thin film of silicon nitride (st3n4) is deposited. The so-called extrinsic gettering method, which is a method of gettingtering the car metal layer etc. that causes micro defects from the outside by methods such as In many cases, the getter effect disappears during the process, so it is difficult to say that it is effective.

一方、最近、酸素原子(0)、炭素原子(C)等の不純
物を比較的多量に含有するシリコン(Sl)基板に対し
て高温熱処理を行なうことにより、基板表層の酸素原子
(0)、をアウトディフュージョンさせて除去すると共
に、基板内部に酸素析出物(Sixty)等、あるいは
それに起因する結晶欠陥を形成した後、その後の素子形
成工程、特に、高温1稈において基板表層に発生する微
小欠陥や積層欠陥を前の工程において内部に形成された
結晶欠陥にゲッタさせ消滅させることにより、動作層を
無欠陥層、すなわち、デニーーデッドゾーンとする方法
が開発されている。この方法は基板の内部に発生した微
小欠陥が基板表層の有害不純物や欠陥を吸着するという
現象、いわゆるイントリンシックゲッタリング(1G)
現象を利用したもので工G法と呼ばれている。
On the other hand, recently, oxygen atoms (0) in the surface layer of the substrate have been removed by high-temperature heat treatment on silicon (Sl) substrates that contain relatively large amounts of impurities such as oxygen atoms (0) and carbon atoms (C). After out-diffusion and removing oxygen precipitates (Sixty), etc., or crystal defects caused by them, are formed inside the substrate, and in the subsequent element formation process, in particular, micro defects and A method has been developed in which the active layer is made into a defect-free layer, that is, a dense dead zone, by getting the stacking faults into crystal defects formed internally in a previous process and eliminating them. This method is called intrinsic gettering (1G), which is a phenomenon in which minute defects generated inside the substrate adsorb harmful impurities and defects on the surface layer of the substrate.
This method uses this phenomenon and is called the Engineering G method.

したがって、上記のlG法を、シリコン(Sl)エピタ
キシャル層内部の欠陥を除去するために応用できれば工
業的に有利である。
Therefore, it would be industrially advantageous if the above-mentioned IG method could be applied to remove defects inside a silicon (Sl) epitaxial layer.

(4)発明の目的 本発明の目的はこの要請に応えることにあ1)、シリコ
ン(Sl)結晶基板上にエピタキシャル成長法をもって
形成されたノリコン(Sl)結晶よ1)なる屑に素子を
形成する半導体素子の製造方法におイテ、上記エピタキ
シャル層中に発生する微小欠陥の帯を可能な限り低減す
る工程を含む、半導体素子の製造方法を提供することに
ある。
(4) Purpose of the Invention The purpose of the present invention is to meet this demand 1) by forming an element on scraps of Noricon (Sl) crystal formed by epitaxial growth on a silicon (Sl) crystal substrate. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which includes a step of reducing as much as possible the bands of micro defects occurring in the epitaxial layer.

(5)  発明の構成 本発明は、酸素(o ) (9度が25〜50 (:[
)])ma)であり、炭素(C)濃度がICppma)
以上であるシリコン(Sl)単結晶よりなる基板上にシ
リコン(Sl)結晶層を成長させ、その後600〜5o
o(℃:H二おいてなす熱処理を施す工程をよむことを
特徴とする、半導体素子の製造方法にある0 上記の工G法において、酸素原子(0)に起因して基板
内部に発生する微小欠陥の量は基板の初期炭素原子(0
)濃度によっても影響を受けることが知られている。
(5) Structure of the invention The present invention provides oxygen (o) (9 degrees is 25 to 50 (:[
)])ma), and the carbon (C) concentration is ICppma)
A silicon (Sl) crystal layer is grown on the substrate made of silicon (Sl) single crystal as described above, and then
o (°C: H2) In the method for manufacturing semiconductor devices, which is characterized by a step of performing a heat treatment at The amount of microdefects is determined by the initial carbon atoms (0
) It is known that it is also affected by concentration.

そこで、本発明の発明者は、シリコ7(Bi)結晶基板
において上記の目的を達するのに適当な酸素(0)及び
炭素(0)濃度と熱処理条件とが存在すれば、工ぎタキ
シャル層に対しても上記IC法を応用できる、すなわち
、エピタキシャル層に発生する欠陥を基板内部の微小欠
陥に吸着させることができるとの着想を得て、この着想
にもとづいて実験を重ね、熱処理条件については窒素(
N2)雰囲気中600〜5oo(℃)において24〜4
8〔時間〕の場合が最も適当であることを確材し、かつ
、その榮件のもと!初期酸素(り濃度が25(ppma
)以上のシリコン(Sl)結晶基板に対し熱処理による
酸素原子(0)減少率、すなわち欠陥発生率と初期炭素
原子(0)濃度との関係を調べた結果、図に示される如
き、一定の関係があることを発見した。すなわち、図は
上記の熱処理を窒素(N2)雰囲気中で700(’O〕
において48時間実行したときの初期炭素(C)#度(
ppma) (横軸)と酸素(0)減少率(%)(#¥
@)との関係を示したものである。上記酸素(0)濃度
、及び初期炭素(C) 71度は赤外分光器を使用して
測定されたものであり、酸素(0)減少率は、熱処理前
の酸素(0)濃度に対する熱処理後の酸素(0)!度の
割合を百分率で表わしたものである。図より明らかなと
おり、与えられた濃度の酸素原子(0)を含むシリコン
(Sl)基板においては、初期炭素(C)濃度が1 (
ppma)以上のときに顕著な酸素(0)減少率、すな
わち、欠陥発生率が得られることが確認された。一方、
シリコン(si)g板の酸素(0)濃度は25(ppm
a)以上であることが必要であるが、エピタキシャル層
の成長条件や基板のそり等の制約からその上限は50(
ppma)程変であることが確認さハたので、シリコン
(Sl)基板の酸素(0)濃度は25[ppma)以上
、50 (ppma)V下であることが望ましい。
Therefore, the inventors of the present invention believe that if suitable oxygen (0) and carbon (0) concentrations and heat treatment conditions exist in a silicon 7 (Bi) crystal substrate to achieve the above objectives, the engineered taxial layer I got the idea that the above IC method could also be applied to this, that is, the defects occurring in the epitaxial layer could be adsorbed to minute defects inside the substrate, and based on this idea, I conducted repeated experiments and determined the heat treatment conditions. nitrogen(
N2) 24-4 at 600-5oo(℃) in atmosphere
8 [hour] is the most appropriate case, and under that circumstance! Initial oxygen concentration is 25 (ppma
) As a result of investigating the relationship between the oxygen atom (0) reduction rate, that is, the defect generation rate, and the initial carbon atom (0) concentration by heat treatment for the above silicon (Sl) crystal substrate, a certain relationship was found as shown in the figure. I discovered that there is. That is, the figure shows the above heat treatment at 700 ('O) in a nitrogen (N2) atmosphere.
Initial carbon (C) # degrees (
ppma) (horizontal axis) and oxygen (0) reduction rate (%) (#¥
It shows the relationship with @). The above oxygen (0) concentration and initial carbon (C) 71 degrees were measured using an infrared spectrometer, and the oxygen (0) reduction rate is the oxygen (0) concentration after heat treatment relative to the oxygen (0) concentration before heat treatment. Oxygen (0)! It is expressed as a percentage. As is clear from the figure, in a silicon (Sl) substrate containing a given concentration of oxygen atoms (0), the initial carbon (C) concentration is 1 (
It was confirmed that a remarkable oxygen (0) reduction rate, that is, a remarkable defect generation rate, was obtained when the amount of oxygen (0) was greater than 100% (ppma). on the other hand,
The oxygen (0) concentration on the silicon (si) g plate is 25 (ppm)
a) or higher, but due to constraints such as epitaxial layer growth conditions and substrate warpage, the upper limit is 50 (
It has been confirmed that the oxygen (0) concentration of the silicon (Sl) substrate is 25 [ppma) or more and 50 (ppma) V or less.

上記の実験的事実にもとづき、本発明の発明者は、基板
の酸素(0)濃度が25〜50 (ppma ) 、炭
素(0) lrJ rlがL(ppma)以上であると
きに、窒素(N2)雰囲気中、600〜800〔℃〕に
おいて24〜48〔時間〕熱処理を行なったときに、エ
ピタキシャル層中の欠陥の減少に最も効果のあることを
確認した。
Based on the above experimental facts, the inventor of the present invention found that when the oxygen (0) concentration of the substrate is 25 to 50 (ppma) and the carbon (0) lrJ rl is more than L (ppma), nitrogen (N2 ) It was confirmed that heat treatment in an atmosphere at 600 to 800 degrees Celsius for 24 to 48 hours was most effective in reducing defects in the epitaxial layer.

(6)発明の実施例 本発明の一実施例に係る半導体装置の製造方法について
説明し、本発明の構成と特性の効果とを明らかにする。
(6) Embodiment of the Invention A method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained, and effects of the structure and characteristics of the present invention will be clarified.

一例として、チョクラルスキー法により製造され、酸素
(0)濃度が30 (ppma) 、炭素(C)強度が
1 (ppma)である、p型シリコン(p−8i)ウ
ェーハを使用した場合について述べる。
As an example, we will discuss the case of using a p-type silicon (p-8i) wafer manufactured by the Czochralski method and having an oxygen (0) concentration of 30 (ppma) and a carbon (C) intensity of 1 (ppma). .

上記基板上に、化学気相成長法(cvn法)等を使用し
てシリコン(Sl)よりなるエピタキシャル層を形成し
たのち、窒素(N2)雰囲気中、70o〔“C〕におい
て48〔時間〕基板の熱処理を行ない、続いて素子形成
工程を行う。
After forming an epitaxial layer of silicon (Sl) on the above substrate using a chemical vapor deposition method (CVN method) or the like, the substrate was heated at 70° C. for 48 hours in a nitrogen (N2) atmosphere. A heat treatment is performed, and then an element forming process is performed.

上記の工程によれば、エピタキシャル層に発生した欠陥
は基板内部の微小欠陥に吸肴され、従来107〔個/c
m2〕程度存在することが認められていたシリコン(S
l)エピタキシャル層中の欠陥が、1o3〜104〔個
/ホ2〕に低減され、素子の特性向上に有効に寄与する
ことが確認された。
According to the above process, defects generated in the epitaxial layer are absorbed by minute defects inside the substrate, and conventionally 107 [defects/c]
silicon (S), which was recognized to exist in the
l) It was confirmed that the number of defects in the epitaxial layer was reduced to 103 to 104 [defects/ho2], which effectively contributed to improving the characteristics of the device.

(7)発明の効果 以上費、明せるとおり、本発明によれば、シリコン(S
l)結晶基板上にエピタキシャル成長法をもって形成さ
れたシリコン(Sl)結晶よりなる層に素子を形成する
半導体素子の製造方法において、上記エピタキシャル層
中に発生する微小欠陥の量を可能な限り低減する工程を
含む、半導体装置の製造方法を提供することができる。
(7) Effects and costs of the invention As is clear, according to the present invention, silicon (S
l) In a method for manufacturing a semiconductor device in which the device is formed in a layer made of silicon (Sl) crystal formed by epitaxial growth on a crystal substrate, a step of reducing as much as possible the amount of micro defects occurring in the epitaxial layer. It is possible to provide a method for manufacturing a semiconductor device including:

【図面の簡単な説明】[Brief explanation of drawings]

図は、初期酸素(o )+a [25(ppma:)以
上のシリコン(Sl)基板に対I7、窒素(N2)雰囲
気斧、700(’O)において48〔時間〕熱処理を行
なったときの酸素(0)減少率(%)、すなわち、欠陥
発生率を、初期炭素(C)IAlf(ppma)を独立
変数トシテ表わしたものである。
The figure shows the initial oxygen (o) + a [25 (ppma:) or higher silicon (Sl) substrate when heat-treated at 700 ('O) for 48 [hours] in a nitrogen (N2) atmosphere ax at I7. (0) The reduction rate (%), that is, the defect occurrence rate, is expressed using the initial carbon (C) IAlf (ppma) as an independent variable.

Claims (1)

【特許請求の範囲】[Claims] 酸素濃度が25乃至50(ppma)であり、炭素濃度
が1(ppma)以上fあるシリコン結晶よりなる基板
上にシリコン結晶層を成長させ、その後600乃至5o
o(℃)においてなす熱処理なMfiす工程を含むこと
を特徴とする、半導体素子の製造方法。
A silicon crystal layer is grown on a substrate made of silicon crystal with an oxygen concentration of 25 to 50 (ppma) and a carbon concentration of 1 (ppma) or more.
1. A method for manufacturing a semiconductor device, comprising a step of heat treatment Mfi performed at a temperature of 0.0C (°C).
JP20480782A 1982-11-22 1982-11-22 Production of semiconductor element Pending JPS5994809A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20480782A JPS5994809A (en) 1982-11-22 1982-11-22 Production of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20480782A JPS5994809A (en) 1982-11-22 1982-11-22 Production of semiconductor element

Publications (1)

Publication Number Publication Date
JPS5994809A true JPS5994809A (en) 1984-05-31

Family

ID=16496685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20480782A Pending JPS5994809A (en) 1982-11-22 1982-11-22 Production of semiconductor element

Country Status (1)

Country Link
JP (1) JPS5994809A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050928A (en) * 1983-08-31 1985-03-22 Toshiba Corp Manufacture of semiconductor device
JPS63227026A (en) * 1987-03-17 1988-09-21 Fujitsu Ltd Gettering method for silicon crystal substrate
WO1998005063A1 (en) * 1996-07-29 1998-02-05 Sumitomo Sitix Corporation Silicon epitaxial wafer and method for manufacturing the same
JPH10229093A (en) * 1997-02-17 1998-08-25 Sumitomo Sitix Corp Production of silicon epitaxial wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5667922A (en) * 1979-11-07 1981-06-08 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation method of semiconductor system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5667922A (en) * 1979-11-07 1981-06-08 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation method of semiconductor system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050928A (en) * 1983-08-31 1985-03-22 Toshiba Corp Manufacture of semiconductor device
JPS63227026A (en) * 1987-03-17 1988-09-21 Fujitsu Ltd Gettering method for silicon crystal substrate
WO1998005063A1 (en) * 1996-07-29 1998-02-05 Sumitomo Sitix Corporation Silicon epitaxial wafer and method for manufacturing the same
EP0948037A1 (en) * 1996-07-29 1999-10-06 Sumitomo Metal Industries, Ltd. Silicon epitaxial wafer and method for manufacturing the same
EP0948037A4 (en) * 1996-07-29 2000-02-02 Sumitomo Metal Ind Silicon epitaxial wafer and method for manufacturing the same
US6277501B1 (en) 1996-07-29 2001-08-21 Sumitomo Metal Industries, Ltd. Silicon epitaxial wafer and method for manufacturing the same
KR100351532B1 (en) * 1996-07-29 2002-09-11 스미토모 긴조쿠 고교 가부시키가이샤 Silicon epitaxial wafer and method for manufacturing the same
JPH10229093A (en) * 1997-02-17 1998-08-25 Sumitomo Sitix Corp Production of silicon epitaxial wafer

Similar Documents

Publication Publication Date Title
US4561171A (en) Process of gettering semiconductor devices
JPH09199416A (en) Semiconductor substrate and manufacture thereof
JPH11314997A (en) Production of semiconductor silicon single crystal wafer
WO2010131412A1 (en) Silicon wafer and method for producing the same
JPS63227026A (en) Gettering method for silicon crystal substrate
JPS5994809A (en) Production of semiconductor element
JPH09148336A (en) Si semiconductor substrate and manufacturing method
WO2022158148A1 (en) Method for manufacturing epitaxial wafer
JPS60247935A (en) Manufacture of semiconductor wafer
JPH10144698A (en) Silicon wafer and its manufacture
JPS5818929A (en) Manufacture of semiconductor device
JP2725460B2 (en) Manufacturing method of epitaxial wafer
JPH0236060B2 (en) KAGOBUTSU HANDOTAINOSEICHOHOHO
JPS6326541B2 (en)
JPH0574784A (en) Manufacture of silicon substrate
JPS6164119A (en) Manufacture of semiconductor device
JP2588632B2 (en) Oxygen precipitation method for silicon single crystal
JPH0534319B2 (en)
JPS6012775B2 (en) Method for forming a single crystal semiconductor layer on a foreign substrate
JPH04175300A (en) Heat treatment of silicon single crystal
JPS62147722A (en) Epitaxial growth method
JPS62279625A (en) Epitaxial growth method
JPS58170020A (en) Manufacture of semiconductor device
JPH05283350A (en) Manufacture of epitaxial semiconductor wafer
JPH0653209A (en) Manufacture of semiconductor device