JPH0236060B2 - KAGOBUTSU HANDOTAINOSEICHOHOHO - Google Patents
KAGOBUTSU HANDOTAINOSEICHOHOHOInfo
- Publication number
- JPH0236060B2 JPH0236060B2 JP19167284A JP19167284A JPH0236060B2 JP H0236060 B2 JPH0236060 B2 JP H0236060B2 JP 19167284 A JP19167284 A JP 19167284A JP 19167284 A JP19167284 A JP 19167284A JP H0236060 B2 JPH0236060 B2 JP H0236060B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gaas
- layer
- temperature
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 64
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 61
- 239000000758 substrate Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 14
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 description 9
- 238000001947 vapour-phase growth Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- OEYOHULQRFXULB-UHFFFAOYSA-N arsenic trichloride Chemical compound Cl[As](Cl)Cl OEYOHULQRFXULB-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明はシリコン（Si）基板又はゲルマニウ
ム（Ge）基板上に砒化ガリウム（GaAs）層をエ
ピタキシヤル成長させる方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for epitaxially growing a gallium arsenide (GaAs) layer on a silicon (Si) or germanium (Ge) substrate.
（従来の技術）
半導体集積回路技術の急速な進展に伴い、大面
積の基板上に大規模集積回路を形成しようとした
り又は三次元回路を形成しようとする試みが成さ
れている。或いは又ソーラセルの研究も盛んとな
つている。そのためには、例えば、Si基板上に高
品質のGaAs単結晶層を形成することが望まれて
いる。しかしながら、従来はSi基板上にGaAs層
を直接成長させることが困難であつたため、Si基
板上に何等かのバツフア層を一旦成長させ、この
バツフア層上にGaAs層を成長させる試みがなさ
れていた。そして文献（Applied Physics
Letters 38（10）、15May 1981、p779〜781）にも
開示されているように、このバツフアとしてGe
の薄膜を使用する例が多い。(Prior Art) With the rapid progress of semiconductor integrated circuit technology, attempts have been made to form large-scale integrated circuits on large-area substrates or to form three-dimensional circuits. Research on solar cells is also gaining momentum. To this end, for example, it is desired to form a high-quality GaAs single crystal layer on a Si substrate. However, in the past, it was difficult to grow a GaAs layer directly on a Si substrate, so attempts were made to first grow a buffer layer of some kind on the Si substrate and then grow a GaAs layer on this buffer layer. . and the literature (Applied Physics
As disclosed in Letters 38(10), 15May 1981, p779-781), Ge
In many cases, a thin film is used.
（発明が解決しようとする問題点）
しかしながら、Si基板の（100）面上にGaAs
層を成長させると、Geバツフア層を介したとし
てもGaAs層がアンテイフエイズドメイン
（antiphase domain）構造となつてしまい、その
結果充分な良質な結晶性をもつたGaAs層が得ら
れなくなるという欠点があつた。(Problem to be solved by the invention) However, GaAs on the (100) plane of the Si substrate
When the layer is grown, even if a Ge buffer layer is used, the GaAs layer becomes an antiphase domain structure, and as a result, a GaAs layer with sufficient quality crystallinity cannot be obtained. It was hot.
また、GeとGaAsとを同一の成長装置内で連続
的に結晶成長させると、GaAs層中にGeのドーピ
ングがあるという欠点があつた。 Furthermore, when Ge and GaAs are successively grown in the same growth apparatus, there is a drawback that Ge is doped in the GaAs layer.
この発明の目的は、従来用いていたGeバツフ
ア層を形成せずに、Si又はGe基板上に単一のド
メインから成る高品質のGaAs層を成長させる方
法を提供することにある。 An object of the present invention is to provide a method for growing a high quality GaAs layer consisting of a single domain on a Si or Ge substrate without forming the conventionally used Ge buffer layer.
（問題点を解決するための手段）
この目的の達成を図るため、この発明の方法に
よれば、シリコン（Si）又はゲルマニウム（Ge）
基板の（100）面上に砒化ガリウム（GaAs）層
をエピタキシヤル成長させるに当り、
該シリコン又はゲルマニウム基板を、砒素圧の
下で前記基板の表面酸化膜を除去して清浄な基板
面を得る温度で、熱処理する工程と、
清浄された該基板上に、450℃以下の温度で、
200Å以下の厚さの砒化ガリウムのバツフア層を
成長させる工程と、
該バツフア層上に、通常の砒化ガリウム層の成
長温度で、該砒化ガリウム層を成長させる工程と
を含むことを特徴とする。(Means for solving the problem) In order to achieve this object, according to the method of the present invention, silicon (Si) or germanium (Ge)
When epitaxially growing a gallium arsenide (GaAs) layer on the (100) plane of a substrate, the silicon or germanium substrate is subjected to arsenic pressure to remove the surface oxide film of the substrate to obtain a clean substrate surface. a heat treatment step at a temperature of 450°C or less on the cleaned substrate;
The present invention is characterized by comprising the steps of: growing a gallium arsenide buffer layer with a thickness of 200 Å or less; and growing the gallium arsenide layer on the buffer layer at a normal gallium arsenide layer growth temperature.
（作用）
このように、この発明によれば、基板を高温熱
処理して清浄にした後、低温で薄いGaAsバツフ
ア層を成長させ、続いて通常のGaAs層の成長温
度でバツフア層上に目的とするGaAs層を成長さ
せるので、いわゆるオーバルデイフエクトのな
い、単一ドメインの結晶性の良いGaAs層が得ら
れる。(Operation) Thus, according to the present invention, after the substrate is heat treated at a high temperature and cleaned, a thin GaAs buffer layer is grown at a low temperature, and then a target layer is formed on the buffer layer at a normal GaAs layer growth temperature. Since a GaAs layer is grown that has a single domain, a GaAs layer with good crystallinity without so-called oval defects can be obtained.
また、この発明の方法によれば、Geのバツフ
ア層を用いる代わりにGaAsの薄いバツフア層を
用い、その上に本来のGaAs層を形成するので、
同一の成長装置内でGaAsバツフア層とGaAs層
とを連続成長させて高品質のGaAs層を得ること
が出来る。 Furthermore, according to the method of the present invention, instead of using a Ge buffer layer, a thin GaAs buffer layer is used, and the original GaAs layer is formed on top of it.
A high quality GaAs layer can be obtained by continuously growing a GaAs buffer layer and a GaAs layer in the same growth apparatus.
（実施例）
以下、図面を参照してこの発明の方法の一実施
例につき説明する。尚、この実施例では、基板と
してSi基板を用い及び原料としてトリメチルガリ
ウム（Ga（CH3）3）及びアルシン（AsH3）を用
い、気相成長法特にMOCVD法でSi基板上に
GaAs層を成長させる例につき説明する。(Example) An example of the method of the present invention will be described below with reference to the drawings. In this example, a Si substrate was used as the substrate, trimethyl gallium (Ga(CH 3 ) 3 ) and arsine (AsH 3 ) were used as the raw materials, and the material was grown on the Si substrate by vapor phase growth, particularly MOCVD.
An example of growing a GaAs layer will be explained.
第１図は、この発明の化合物半導体の成長方法
を実施する際の、基板を載置するサセプタの温度
変化を示す線図で、以下の説明では温度について
はこのサセプタの温度で説明するが、ガス流量、
ガスの流し方、反応管の形状、サセプタの形状、
サセプタを何度まで加熱しているか等によつて基
板の温度がサセプタの温度よりも100℃程度位ま
で低くなることもある。 FIG. 1 is a diagram showing the temperature change of a susceptor on which a substrate is placed when carrying out the compound semiconductor growth method of the present invention.In the following explanation, the temperature will be explained in terms of the temperature of this susceptor. gas flow rate,
How to flow gas, shape of reaction tube, shape of susceptor,
Depending on how high the susceptor is heated, the temperature of the substrate may be about 100°C lower than the temperature of the susceptor.
先ず、気相成長装置の反応管中のサセプタにSi
基板を載置した後、キヤリアガスとして例えば
H2を流しながらサセプタの温度を室温から昇温
させる（第１図に示す時間区間）。この昇温の
途中で、サセプタの温度が500〜600℃になつた
時、砒素圧下による高温熱処理を行うため、この
場合にはAsH3を流し始める。この時のAsH3の
分圧は少なくとも0.5Torr位となつていれば充分
である。尚、このAsH3は、後述する目的とする
GaAs層を成長させた後サセプタ温度が500℃以
下になるまで、流し続ける。 First, Si was added to the susceptor in the reaction tube of the vapor phase growth apparatus.
After placing the substrate, use a carrier gas such as
The temperature of the susceptor is raised from room temperature while flowing H 2 (time period shown in FIG. 1). During this temperature increase, when the temperature of the susceptor reaches 500 to 600° C., in order to perform high temperature heat treatment under arsenic pressure, in this case, AsH 3 is started to flow. It is sufficient that the partial pressure of AsH 3 at this time is at least about 0.5 Torr. The purpose of this AsH 3 is described later.
After growing the GaAs layer, continue flowing until the susceptor temperature drops below 500°C.
サセプタ温度が砒素圧の下でSi基板の表面酸化
膜を除去して清浄な基板面を得ることが出来る温
度、例えば900℃以上の温度好ましくは900〜950
℃に達したら、昇温をやめて、この温度に保持し
て高温熱処理を行う（第１図に示す時間区間）。
この場合、熱処理をH2とAsH3の雰囲気中で行い
その処理時間は５分程度で充分である。 The susceptor temperature is a temperature at which the surface oxide film of the Si substrate can be removed under arsenic pressure to obtain a clean substrate surface, for example, a temperature of 900°C or higher, preferably 900 to 950.
When the temperature reaches 0.degree. C., the temperature increase is stopped and the temperature is maintained to perform high-temperature heat treatment (time period shown in FIG. 1).
In this case, the heat treatment is performed in an atmosphere of H 2 and AsH 3 and the treatment time is about 5 minutes.
この高温熱処理後、温度を下げて（第１図に示
す時間区間）450℃以下の温度好ましくは400〜
450℃の温度に保持し、AsH3にGa（CH3）3を加え
た原料ガスを流し、清浄させたSi基板の（100）
基板面上にGaAsの薄膜をバツフア層として成長
させる（第１図に示した時間区間）。この
GaAsバツフア層の厚みを200Å程度以下とする。 After this high-temperature heat treatment, the temperature is lowered (time period shown in Figure 1) to a temperature of 450°C or less, preferably 400°C or less.
The (100) Si substrate was cleaned by maintaining the temperature at 450℃ and flowing a raw material gas containing AsH3 and Ga( CH3 ) 3 .
A GaAs thin film is grown as a buffer layer on the substrate surface (time interval shown in Figure 1). this
The thickness of the GaAs buffer layer is approximately 200 Å or less.
このGaAsバツフア層を成長完了後、再びサセ
プタ温度を昇温させて、本来の目的とるGaAs層
の通常の成長温度である650〜800℃程度にする
（第１図に示す時間区間）。この実施例ではこの
温度を700℃とする。この温度の昇温過程におい
て、GaAsバツフア層はアニールされることとな
り、その結果、このGaAsバツフア層は、その上
に形成されるGaAs層がオーバルデイフエクトの
ない結晶性の良い層となるような、良質なバツフ
ア層となる。 After the growth of this GaAs buffer layer is completed, the susceptor temperature is raised again to about 650 to 800° C., which is the normal growth temperature for the intended GaAs layer (time period shown in FIG. 1). In this example, this temperature is 700°C. During this temperature rising process, the GaAs buffer layer is annealed, and as a result, the GaAs buffer layer forms a layer with good crystallinity without oval defects. It becomes a high quality buffer layer.
次に、このサセプタを700℃に保持して、
GaAsバツフア層上にGaAs層を成長させる（第
１図の時間区間）。そのため、再びGa（CH3）3
を成長するのに適当な量のAsH3に加えて目的と
するGaAs層を成長させる。 Next, hold this susceptor at 700℃,
A GaAs layer is grown on the GaAs buffer layer (time interval in FIG. 1). So again Ga( CH3 ) 3
Add an appropriate amount of AsH 3 to grow the desired GaAs layer.
このGaAs層の成長が終つたら、サセプタ温度
を室温まで下げる（第１図に示す時間区間）。 After the growth of this GaAs layer is completed, the susceptor temperature is lowered to room temperature (time interval shown in FIG. 1).
このようにして、同一の気相成長装置内で連続
的に上述した各処理を行つて単一ドメインの高品
質のGaAs層をSi基板の（100）面上に成長させ
ることが出来、この一連の処理過程中にウエハ
（この場合、基板はもとより、基板に層が形成さ
れたものを総称してウエハという）を成長装置か
ら出したりすることがない。 In this way, a single-domain high-quality GaAs layer can be grown on the (100) plane of a Si substrate by performing the above-mentioned processes sequentially in the same vapor phase growth apparatus, and this series During the processing process, the wafer (in this case, not only the substrate but also a substrate on which a layer is formed is collectively referred to as a wafer) is not removed from the growth apparatus.
上述したSi基板の清浄のための高温熱処理は
H2中でも効果があるが、H2のみの雰囲気で行つ
た場合には、ペデスタル上に以前の成長時に折出
した多結晶のGaAsが再蒸発してウエハ上、特に
ウエハの周辺部に細かい粒子として付着し、ウエ
ハの周辺部にはGaAs層が得られなくなる恐れが
あつたり、或いは、ウエハの中央部では再付着の
GaAsがオーバルデイフエクトの核となる恐れが
ある。従つて、この発明では、熱処理に際し、
AsH3をH2と共に流しAsH3が分解して得られた
砒素の圧力により、ペデスタル上に折出した残存
GaAsの再蒸発を抑えることによつてウエハ上に
GaAsの細かい粒子が付着するのを防止してい
る。このため、ウエハ全面にわたつてオーバルデ
イフエクトのない単一のドメインの高品質の
GaAs成長層を得ることが出来る。 The high temperature heat treatment for cleaning the Si substrate mentioned above is
It is effective even in H 2 , but when carried out in an atmosphere of only H 2 , polycrystalline GaAs deposited on the pedestal during previous growth re-evaporates, leaving fine particles on the wafer, especially in the periphery of the wafer. There is a risk that a GaAs layer will not be obtained at the periphery of the wafer, or that re-deposition may occur at the center of the wafer.
There is a fear that GaAs will become the core of the oval defect. Therefore, in this invention, during heat treatment,
AsH 3 is poured with H 2 and AsH 3 decomposes, the resulting arsenic pressure causes the residual material to precipitate on the pedestal.
on the wafer by suppressing GaAs re-evaporation.
This prevents fine GaAs particles from adhering. This allows high-quality, single-domain, oval-defect-free production across the entire wafer.
A GaAs growth layer can be obtained.
又、低温で成長させるバツフア層であるが、そ
の場合の成長温度は400〜450℃が適当である。こ
れよりも高い温度に対すると高温になるに従つて
バツフア層上に成長した目的とするGaAs層の表
面が荒れて結晶性の悪い層となつてしまう。ま
た、逆にさらに低い温度にすると、成長速度が著
しく遅くなつてしまう。 Further, the buffer layer is grown at a low temperature, and in that case, the appropriate growth temperature is 400 to 450°C. If the temperature is higher than this, the surface of the target GaAs layer grown on the buffer layer becomes rough and becomes a layer with poor crystallinity as the temperature increases. On the other hand, if the temperature is lowered even further, the growth rate will be significantly slowed down.
さらに、バツフア層の厚みを200Å以下という
薄さにしたが、これより厚くすると、その上に成
長させるGaAs層にオーバルデイフエクトが生じ
たり単一のドメインになりにくくなつたして結晶
性が悪くなる。しかし、薄い方は数原子層程度の
薄さとなつてもよい。 Furthermore, although the thickness of the buffer layer was made as thin as 200 Å or less, if it was made thicker than this, oval defects would occur in the GaAs layer grown on top of it, and it would be difficult to form a single domain, resulting in poor crystallinity. Deteriorate. However, the thinner layer may be as thin as several atomic layers.
この発明は上述した実施例にのみ限定されるも
のではない。例えば、上述した実施例はSi基板上
にGaAs層を成長させる例につき説明したがGe基
板上にもSi基板の場合と同様な処理によつて高品
質のGaAs層を成長させることが出来る。その場
合には、基板の高温熱処理時のサセプタ温度を
600℃以上好ましくは700℃前後の温度とすれば充
分である。 The invention is not limited to the embodiments described above. For example, although the above embodiment describes an example in which a GaAs layer is grown on a Si substrate, a high quality GaAs layer can also be grown on a Ge substrate by the same process as that for a Si substrate. In that case, the susceptor temperature during high-temperature heat treatment of the substrate should be
It is sufficient to set the temperature to 600°C or higher, preferably around 700°C.
又、上述した実施例ではMOCVD法を用いて
GaAs層の成長を行つたが他の普通の気相成長法
で成長させることも出来る。その場合、原料とし
て、例えば、三塩化砒素（AsCl3）及びカリウム
（Ga）とか、Ga、アルシン及び塩酸とかを用い
ることが出来る。 In addition, in the above-mentioned example, MOCVD method was used.
Although the GaAs layer was grown, it can also be grown using other conventional vapor phase growth methods. In that case, as raw materials, for example, arsenic trichloride (AsCl 3 ) and potassium (Ga), Ga, arsine, and hydrochloric acid can be used.
さらに、キヤリアガスとしてH2以外の任意適
切なガスを用いることが出来る。 Furthermore, any suitable gas other than H 2 can be used as the carrier gas.
（発明の効果）
上述した説明からも明らかなように、この発明
によれば、高温熱処理でSi又はGeの基板の表面
は清浄にした後、低温で（100）基板面上に200Å
以下という薄膜のGaAsバツフア層を成長させ、
このバツフア層上に目的とするGaAs層を成長さ
せているので、高品質のGaAs層を成長させるこ
とが出来る。(Effects of the Invention) As is clear from the above description, according to the present invention, after the surface of a Si or Ge substrate is cleaned by high-temperature heat treatment, a 200 Å film is deposited on the (100) substrate surface at a low temperature.
We grow a thin GaAs buffer layer as shown below.
Since the target GaAs layer is grown on this buffer layer, a high quality GaAs layer can be grown.
又、この発明により得られたGaAs層のエツチ
ピツト密度は104cm-3と少なく、移動度について
も１×1016cm-3の電子密度に対して5200cm2
-1s-1というようにGaAs上に成長させたGaAs層
に近い値が得られているので、充分各種のGaAs
デバイスの製作に使用可能である。 In addition, the etch pit density of the GaAs layer obtained by this invention is as low as 10 4 cm -3 , and the mobility is 5200 cm 2 for an electron density of 1×10 16 cm -3 .
-1 s -1 , which is close to that of a GaAs layer grown on GaAs, is obtained, so it is possible to
It can be used for manufacturing devices.
さらに、Si又はGe基板はGaAs基板では得られ
ない大面積の基板が得られるので、この基板上に
この発明によりGaAsを成長させて大面積でしか
も高品質のGaAs層を得ることが出来、この
GaAs層に大規模集積回路や或いは三次元回路を
作り込んだり、又、このGaAs層を用いてソーラ
セルを作り上げることが出来る。 Furthermore, since a Si or Ge substrate can provide a large-area substrate that cannot be obtained with a GaAs substrate, it is possible to grow GaAs on this substrate according to the present invention to obtain a large-area, high-quality GaAs layer.
Large-scale integrated circuits or three-dimensional circuits can be fabricated in the GaAs layer, and solar cells can also be fabricated using the GaAs layer.
上述したように、基板上にGaAs層を成長させ
るための全処理工程を同一の気相成長装置内で、
ウエハの出し入れを行うことはなく、実施出来る
ので、ウエハが汚染されたり損傷したりすること
なく、よつてこの点からも高品質のGaAs層が得
られる。 As mentioned above, all the processing steps for growing a GaAs layer on a substrate can be performed in the same vapor phase growth apparatus.
Since the process can be carried out without having to take the wafer in and out, the wafer will not be contaminated or damaged, and from this point of view as well, a high quality GaAs layer can be obtained.
第１図はこの発明の化合物半導体の製造方法の
説明に供するサセプタの温度変化を示す線図であ
る。
FIG. 1 is a diagram showing temperature changes in a susceptor for explaining the compound semiconductor manufacturing method of the present invention.
Claims (1)
板の（100）面上に砒化ガリウム（GaAs）層を
エピタキシヤル成長させるに当り、 該シリコン又はゲルマニウム基板を、砒素圧の
下で前記基板の表面酸化膜を除去して清浄な基板
面を得る温度で、熱処理する工程と、 清浄された該基板上に、450℃以下の温度で、
200Å以下の厚さの砒化ガリウムのバツフア層を
成長させる工程と、 該バツフア層上に、通常の砒化ガリウム層の成
長温度で、砒化ガリウム層を成長させる工程とを
含むことを特徴とする化合物半導体の成長方法。 ２ 各前記工程を同一の成長装置内で連続して行
なうことを特徴とする特許請求の範囲第１項記載
の化合物半導体の成長方法。[Claims] 1. In epitaxially growing a gallium arsenide (GaAs) layer on the (100) plane of a silicon (Si) or germanium (Ge) substrate, the silicon or germanium substrate is grown under arsenic pressure. a step of heat-treating the substrate at a temperature that removes the surface oxide film of the substrate to obtain a clean substrate surface;
A compound semiconductor comprising the steps of: growing a gallium arsenide buffer layer with a thickness of 200 Å or less; and growing a gallium arsenide layer on the buffer layer at a normal gallium arsenide growth temperature. How to grow. 2. The method for growing a compound semiconductor according to claim 1, wherein each of the steps is performed successively in the same growth apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19167284A JPH0236060B2 (en) | 1984-09-14 | 1984-09-14 | KAGOBUTSU HANDOTAINOSEICHOHOHO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19167284A JPH0236060B2 (en) | 1984-09-14 | 1984-09-14 | KAGOBUTSU HANDOTAINOSEICHOHOHO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170715A JPS6170715A (en) | 1986-04-11 |
| JPH0236060B2 true JPH0236060B2 (en) | 1990-08-15 |
Family
ID=16278536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19167284A Expired - Lifetime JPH0236060B2 (en) | 1984-09-14 | 1984-09-14 | KAGOBUTSU HANDOTAINOSEICHOHOHO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236060B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH058961U (en) * | 1991-07-15 | 1993-02-05 | スタンレー電気株式会社 | Surface mount LED |
| JPH0579586U (en) * | 1991-05-28 | 1993-10-29 | エムケー精工株式会社 | Light emitting diode display |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2676144B2 (en) * | 1987-07-27 | 1997-11-12 | 日本電信電話株式会社 | Method for growing gallium arsenide |
| EP0603780B1 (en) * | 1992-12-21 | 1998-04-29 | Nippon Steel Corporation | Method of growing compound semiconductor on silicon wafer |
| US5833749A (en) | 1995-01-19 | 1998-11-10 | Nippon Steel Corporation | Compound semiconductor substrate and process of producing same |
| JP2010225981A (en) * | 2009-03-25 | 2010-10-07 | Fujitsu Ltd | Optical semiconductor device, integrated element and method of manufacturing optical semiconductor device |
| US10096473B2 (en) * | 2016-04-07 | 2018-10-09 | Aixtron Se | Formation of a layer on a semiconductor substrate |
-
1984
- 1984-09-14 JP JP19167284A patent/JPH0236060B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0579586U (en) * | 1991-05-28 | 1993-10-29 | エムケー精工株式会社 | Light emitting diode display |
| JPH058961U (en) * | 1991-07-15 | 1993-02-05 | スタンレー電気株式会社 | Surface mount LED |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6170715A (en) | 1986-04-11 |
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