KR100329776B1 - Method of fabricating semiconductor device for removing crystal-originated pit on silicon wafer - Google Patents
Method of fabricating semiconductor device for removing crystal-originated pit on silicon wafer Download PDFInfo
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- KR100329776B1 KR100329776B1 KR1019980057247A KR19980057247A KR100329776B1 KR 100329776 B1 KR100329776 B1 KR 100329776B1 KR 1019980057247 A KR1019980057247 A KR 1019980057247A KR 19980057247 A KR19980057247 A KR 19980057247A KR 100329776 B1 KR100329776 B1 KR 100329776B1
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- silicon
- surface defects
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 43
- 239000010703 silicon Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 230000007547 defect Effects 0.000 claims abstract description 24
- 239000007789 gas Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 235000012431 wafers Nutrition 0.000 abstract description 41
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 238000003475 lamination Methods 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
- H01L21/02049—Dry cleaning only with gaseous HF
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
본 발명은 반도체 기술에 관한 것으로, 특히 실리콘 웨이퍼의 표면결함 제거를 위한 반도체 소자 제조방법에 관한 것이며, 산소적층결함 또는 슬립을 유발하지 않으면서 실리콘 웨이퍼의 표면결함을 제거할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다. 본 발명은 실리콘 웨이퍼 표면에 존재하는 자연산화막을 HF 가스(또는 H2F2가스)를 사용하여 제거한 후 1000∼1200℃ 온도의 H2가스(또는 H2/Ar 가스) 분위기에서 급속열처리를 실시하여 실리콘 웨이퍼의 표면결함을 제거하는 기술이다. 이 경우, 열처리시 발생할 수 있는 산소적층결함이나 슬립을 방지하면서 실리콘 웨이퍼의 표면결함을 줄일 수 있으며, 고가의 에피성장 실리콘 웨이퍼를 사용하지 않고, 일반적인 성장방법으로 성장시킨 실리콘 잉곳을 사용하여 제조한 저가의 실리콘 웨이퍼(표면결함이 많은 상태)를 이용할 수 있도록 한다.The present invention relates to a semiconductor technology, and more particularly, to a semiconductor device manufacturing method for removing surface defects of a silicon wafer, and a semiconductor device manufacturing method capable of removing surface defects of a silicon wafer without causing oxygen lamination defects or slips. The purpose is to provide. The present invention removes the native oxide film on the surface of the silicon wafer using HF gas (or H 2 F 2 gas), and then performs rapid heat treatment in an H 2 gas (or H 2 / Ar gas) atmosphere at a temperature of 1000 to 1200 ° C. By removing the surface defects of the silicon wafer. In this case, it is possible to reduce the surface defects of the silicon wafer while preventing oxygen lamination defects or slips which may occur during heat treatment, and using silicon ingots grown by a general growth method without using expensive epi-grown silicon wafers. Low cost silicon wafers (high surface defects) are available.
Description
본 발명은 반도체 기술에 관한 것으로, 특히 실리콘 웨이퍼의 표면결함 제거를 위한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device for removing surface defects of a silicon wafer.
실리콘 웨이퍼는 반도체 메모리를 비롯한 반도체 제조 공정 전반에 가장 널리 사용되고 있다. 실리콘 웨이퍼는 Si 시드(seed)를 이용하여 실리콘 잉곳(ingot)을 성장시키고, 다이아몬드 등을 이용하여 이를 정밀하게 절단(slicing)하여 제조하고 있다.Silicon wafers are most widely used throughout semiconductor manufacturing processes, including semiconductor memories. Silicon wafers are manufactured by growing silicon ingots using Si seeds and precisely slicing them using diamonds or the like.
완성된 실리콘 웨이퍼에는 어느 정도의 표면결함(crystal originated pit)이존재하게 되는데, 이러한 표면결함을 줄이기 위해서 실리콘 웨이퍼의 원재료인 실리콘 잉곳의 성장속도를 늦추는 방법을 사용하였다.There is a certain amount of crystal originated pit in the finished silicon wafer. In order to reduce such surface defects, a method of slowing the growth rate of the silicon ingot, which is a raw material of the silicon wafer, has been used.
그러나, 이처럼 잉곳의 성장속도를 늦추어 표면결함을 줄이는 방법은 잉곳 생산성을 떨어뜨리게 되는 문제점이 있기 때문에, 종래에는 주로 실리콘 웨이퍼를 확산로에서 고온으로 열처리를 하는 방법을 사용하여 왔다.However, the method of reducing the surface defects by slowing the growth rate of the ingot has a problem of lowering the ingot productivity, and thus, conventionally, a silicon wafer has been mainly heat treated at a high temperature in a diffusion furnace.
그러나, 이와 같이 확산로에서 고온 열처리하는 경우, 실리콘 웨이퍼에 산소적층결함이 유발되는 문제점이 있었다. 한편, 확산로를 대신하여 급속열처리 장비를 이용하는 경우에도 1200℃ 이상의 고온에서 열처리를 진행하게 되므로 역시 실리콘 웨이퍼에 산소적층결함이나 슬립(slip)을 유발할 우려가 있다.However, when the high temperature heat treatment in the diffusion furnace in this way, there was a problem that the oxygen lamination defects in the silicon wafer. On the other hand, even in the case of using a rapid heat treatment equipment in place of the diffusion furnace, since the heat treatment is carried out at a high temperature of more than 1200 ℃ there is also a risk of causing oxygen deposition defects or slip (slip) on the silicon wafer.
또한, 1G DRAM이나 4G DRAM급의 초고집적 반도체 소자를 제조하기 위해서는 표면결함이 적은 에피성장(epitaxial growth) 실리콘 웨이퍼를 사용하게 되는데, 이 에피성장 실리콘 웨이퍼는 일반적인 웨이퍼에 비해 매우 고가이기 때문에 반도체 소자의 단가를 상승시키는 단점이 있었다.In addition, epitaxial growth silicon wafers with low surface defects are used to fabricate ultra-high density semiconductor devices of 1G DRAM or 4G DRAM class. There was a disadvantage of raising the unit price.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 산소적층결함 또는 슬립을 유발하지 않으면서 실리콘 웨이퍼의 표면결함을 제거할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device capable of removing surface defects of a silicon wafer without causing oxygen lamination defects or slips.
도 1은 어닐링에 의한 웨이퍼 표면의 원자 이동의 원리를 설명하기 위한 도면.BRIEF DESCRIPTION OF THE DRAWINGS The figure for demonstrating the principle of the atomic movement of the wafer surface by annealing.
도 2a는 종래기술에 따라 제조된 웨이퍼의 표면 사진.Figure 2a is a photograph of the surface of the wafer prepared according to the prior art.
도 2b는 본 발명에 따라 수소 어닐을 실시한 웨이퍼의 표면 사진.Figure 2b is a surface photograph of the wafer subjected to hydrogen annealing according to the present invention.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 실리콘 웨이퍼 표면의 자연산화막을 제거하는 제1 단계와, 1000∼1200℃ 온도의 수소 가스분위기에서 상기 실리콘 웨이퍼에 대한 급속열처리를 수행하는 제2 단계를 포함하여, 상기 실리콘 웨이퍼의 표면결함을 제거하는 것을 특징으로 하는 반도체 소자 제조방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, the first step of removing the natural oxide film on the surface of the silicon wafer, and performing a rapid heat treatment for the silicon wafer in a hydrogen gas atmosphere at a temperature of 1000 ~ 1200 ℃ Including a second step, there is provided a method for manufacturing a semiconductor device, characterized in that to remove the surface defects of the silicon wafer.
본 발명은 실리콘 웨이퍼 표면에 존재하는 자연산화막을 HF 가스(또는 H2/F2가스)를 사용하여 제거한 후 1000∼1200℃ 온도의 H2가스(또는 H2/Ar 가스) 분위기에서 급속열처리를 실시하여 실리콘 웨이퍼의 표면결함을 제거하는 기술이다. 이 경우, 열처리시 발생할 수 있는 산소적층결함이나 슬립을 방지하면서 실리콘 웨이퍼의 표면결함을 줄일 수 있으며, 고가의 에피성장 실리콘 웨이퍼를 사용하지 않고, 일반적인 성장방법으로 성장시킨 실리콘 잉곳을 사용하여 제조한 저가의 실리콘 웨이퍼(표면결함이 많은 상태)를 이용할 수 있도록 한다.The present invention removes the native oxide film on the surface of the silicon wafer using HF gas (or H 2 / F 2 gas), and then performs rapid heat treatment in an H 2 gas (or H 2 / Ar gas) atmosphere at a temperature of 1000 to 1200 ° C. It is a technique to remove the surface defects of the silicon wafer. In this case, it is possible to reduce the surface defects of the silicon wafer while preventing oxygen lamination defects or slips which may occur during heat treatment, and using silicon ingots grown by a general growth method without using expensive epi-grown silicon wafers. Low cost silicon wafers (high surface defects) are available.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
우선, 준비된 실리콘 웨이퍼 표면에 존재하는 자연산화막(native oxide)을 HF 가스를 사용하여 제거한다. 이때, 연속(in-situ) 공정을 위하여 급속열처리(RTA, rapid thermal annealing) 장비 내에 HF 가스를 주입하여 자연산화막을 제거할 수 있다.First, native oxide present on the prepared silicon wafer surface is removed using HF gas. In this case, the natural oxide layer may be removed by injecting HF gas into a rapid thermal annealing (RTA) device for an in-situ process.
다음으로, 자연산화막이 제거된 실리콘 웨이퍼를 1000∼1200℃ 온도의 H2가스 분위기에서 급속열처리를 실시한다. 이때, 급속열처리는 H2/Ar 혼합 가스 분위기에서 실시할 수도 있다.Next, the silicon wafer from which the natural oxide film was removed is subjected to rapid heat treatment in a H 2 gas atmosphere at a temperature of 1000 to 1200 ° C. At this time, rapid thermal annealing may be performed at H 2 / Ar mixed gas atmosphere.
예컨대, 80Torr 압력하의 1100℃ 온도에서 60초 정도 급속열처리를 실시하면 웨이퍼 표면의 실리콘(Si)이 마이그레이션(migratrion) 된다. 압력을 낮추면 그 이하의 온도에서도 실리콘의 마이크레이션이 일어난다.For example, when the rapid heat treatment is performed for about 60 seconds at a temperature of 1100 ° C. under 80 Torr pressure, silicon (Si) on the wafer surface is migrated. If the pressure is lowered, the silicon will micronize at temperatures below that.
첨부된 도면 도 1은 어닐링에 의한 웨이퍼 표면의 원자 이동의 원리를 설명하기 위한 도면으로, 수소 어닐의 경우 실리콘의 표면에너지 최소화 경향에 의해 수소 이동이 유발되며, 이는 웨이퍼 표면의 피크-밸리(peak-to-valley)값을 줄여주는 역할을 한다. 따라서, 웨이퍼 표면에 존재하는 표면결함이 실리콘 원자의 이동에 의해서 채워지게 되는 것이다.1 is a view for explaining the principle of atomic movement of the wafer surface by annealing. In the case of hydrogen annealing, hydrogen migration is caused by a tendency of minimizing the surface energy of silicon, which is a peak-valley of the wafer surface. -to-valley) to reduce the value. Therefore, surface defects existing on the wafer surface are filled by the movement of silicon atoms.
첨부된 도면 도 2a는 종래기술에 따라 제조된 웨이퍼의 표면 사진이며, 도 2b는 본 발명에 따라 수소 어닐을 실시한 웨이퍼의 표면 사진이다. 도면을 참조하면, 수소 어닐의 효과를 쉽게 확인할 수 있을 것이다.2A is a photograph of the surface of a wafer manufactured according to the prior art, and FIG. 2B is a photograph of the surface of a wafer subjected to hydrogen annealing according to the present invention. Referring to the drawings, it will be easy to see the effect of hydrogen annealing.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예를 들어, 전술한 실시예에서는 HF 가스를 사용하여 실리콘 웨이퍼 표면의 자연산화막을 제거하는 경우를 일례로 들어 설명하였으나, H2F2가스와 같은 다른 에천트를 사용하여 자연산화막을 제거할 수도 있다.For example, in the above-described embodiment, the case where the natural oxide film on the surface of the silicon wafer is removed using HF gas is described as an example. However, the natural oxide film may be removed using another etchant such as H 2 F 2 gas. have.
전술한 본 발명은 실리콘 웨이퍼의 표면결함을 크게 줄이는 효과가 있으며, 이로 인하여 1G DRAM이나 4G DRAM의 실리콘 웨이퍼로서 사용되는 표면결함이 적은 에피성장 실리콘 웨이퍼를 기존의 잉곳 성장방법을 그대로 사용하여 제조한 실리콘 웨이퍼로 대체할 수 있어 경제적인 측면에서 장점이 있다.The present invention described above has the effect of greatly reducing the surface defects of silicon wafers, and thus, epitaxial silicon wafers having low surface defects, which are used as silicon wafers of 1G DRAM or 4G DRAM, are manufactured using the conventional ingot growth method. It can be replaced with a silicon wafer, which is economically advantageous.
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| KR1019980057247A KR100329776B1 (en) | 1998-12-22 | 1998-12-22 | Method of fabricating semiconductor device for removing crystal-originated pit on silicon wafer |
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| KR1019980057247A KR100329776B1 (en) | 1998-12-22 | 1998-12-22 | Method of fabricating semiconductor device for removing crystal-originated pit on silicon wafer |
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| KR100593740B1 (en) * | 2004-09-16 | 2006-06-28 | 삼성전자주식회사 | Method of removing native oxide film |
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