JPS6164119A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6164119A
JPS6164119A JP59185840A JP18584084A JPS6164119A JP S6164119 A JPS6164119 A JP S6164119A JP 59185840 A JP59185840 A JP 59185840A JP 18584084 A JP18584084 A JP 18584084A JP S6164119 A JPS6164119 A JP S6164119A
Authority
JP
Japan
Prior art keywords
layer
substrate
ion
gaas
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59185840A
Other languages
Japanese (ja)
Inventor
Takeshi Konuma
小沼　毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59185840A priority Critical patent/JPS6164119A/en
Publication of JPS6164119A publication Critical patent/JPS6164119A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE:To obtain a GaAs layer which is excellent in crystallization and electric characteristics on an Si substrate by directly depositing the GaAs layer on a Ge ion implanted layer formed by implanting a Ge ion on the Si substrate or by growing the GaAs layer after depositing a Ge layer on the Ge ion implanted layer. CONSTITUTION:A Ge ion implanted layer 3 is formed by implanting a Ge ion on an Si substrate 1 using an ion implantation technique. The implanted ion is activated and a crystal defect due to implantation is recovered by heat treat ment for 10sec at 1,300 deg.C using a lamp annealing method. A Ge layer 4 is grown at growing speed of 1.2Angstrom /sec to the thickness of 0.5mum the temperature of the substrate being made at 650 deg.C by MBE method and then a GaAs layer 5 is grown on the Ge layer 4 at growing speed 0.1Angstrom /min to the thickness of 2mum the temperature of the substrate being at 620 deg.C by MBE method. This enables forming the GaAs layer which is excellent in crystallization electric characteristics on the Si substrate.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電気−光集積回路等複合デバイス用の基体とし
て用いるＳｉ基板上へのＧ　ａ　Ａ　ｓ結晶の成長方法
の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in the method of growing GaAs crystals on Si substrates used as substrates for composite devices such as electrical-optical integrated circuits.

従来例の構成とその問題点 Ｓｉ基板上へのＧ　ａ　Ａ　ｓの結晶成長は、Ｇ　ａ　
Ａ　ｓが高゛覗子移動度２発光機能を有し、一方Ｓ１は
大口径高品質結晶が得られ、かつデバイス製作技術が確
立しているので、Ｓｉ基板上に高集積デバイスを、Ｇ　
ａ　Ａ　ｓに高速デバイス、発光デバイス等を集積する
複合デバイスの基体として有望である。Structure of the conventional example and its problems The crystal growth of GaAs on the Si substrate is
A s has a high object mobility 2 light emitting function, while S 1 has a large-diameter high-quality crystal and has established device manufacturing technology, so it is possible to fabricate highly integrated devices on a Si substrate.
It is promising as a substrate for composite devices that integrate high-speed devices, light-emitting devices, etc. on aAs.

Ｓｉ基板上へのＧ　ａ　Ａ　ｓの成長法としては、Ｓｉ
基板上にＭＢＥ法（Ｈｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅ
ｐｉｔａｘｙ法）或はＭＯＣＶＤ法（Ｍｅｔａｌ　Ｏｒ
ｇａｎｉｃ　ＣｈｅｍｉｃａｌＶａｐｏｒ　Ｄｅｐｏｓ
ｉｔｉｏｎ）を用いてＧ　ａ　Ａ　ｓを堆積している。As a method for growing GaAs on a Si substrate, Si
The MBE method (Holecular Beam E
pitaxy method) or MOCVD method (Metal Or
ganic Chemical Vapor Depos
tion) to deposit GaAs.

この方法で成長したＧ　ａ　Ａ　ｓ層は、クラックが発
生する。双晶が発生する等結晶性の優れたものは得られ
ていない。この原因として、基板ＳｉとＧ　ａ　Ａ　ｓ
層の格子定数の不整合によると考えられている。これを
改良する方法として、Ｓｉ基板上にＧｅを堆積し、この
Ｇｅ層上にＧ　ａ　Ａ　ｓを堆積する方法が用いられて
いる。ＧｅとＧ　ａ　Ａ　ｇはほぼ格子定数が等しいの
で、Ｓｉ基板上に直接Ｇ　ａ　Ａ　ｓ層を堆積した場合
に比して結晶性はかなり向上するが、通常のＧ　ａ　Ａ
　ｓ基板上に成長したＧ　ａ　Ａ　ｓ層の移動度に比し
て１／２〜１７３に低下する。これはＳｉ基板とＧｅ層
の格子定数の違いが大きいだめ、Ｇｅ層の結晶性が悪い
だめと推測される。Cracks occur in the GaAs layer grown by this method. A product with excellent crystallinity such as generation of twins has not been obtained. The cause of this is that the substrate Si and GaAs
This is thought to be due to a mismatch in the lattice constants of the layers. As a method to improve this, a method has been used in which Ge is deposited on a Si substrate and Ga As is deposited on this Ge layer. Since Ge and GaAg have almost the same lattice constant, the crystallinity is considerably improved compared to when a GaAs layer is deposited directly on a Si substrate.
The mobility decreases to 1/2 to 173 times that of the GaAs layer grown on the S substrate. This is presumably due to the large difference in lattice constant between the Si substrate and the Ge layer, and the poor crystallinity of the Ge layer.

発明の目的 本発明はＳｉ基板上に結晶性、電気的相性の優れたＧ　
ａ　Ａ　ｓ層を得るだめの半導体装置の製造方法を提供
する。Purpose of the Invention The present invention provides a G film with excellent crystallinity and electrical compatibility on a Si substrate.
A method for manufacturing a semiconductor device that obtains an aAs layer is provided.

発明の構成 本発明の骨子とするところは、Ｓｉ基板上に結晶性、電
気的特性の優れたＧ　ａ　Ａ　ｓ層を得るため、Ｓｉ基
板にＧｅをイオン注入してＧｅイオン注入層を形成し、
Ｇｅイオン注入層上に直接Ｇ　ａ　Ａ　ｓ層を堆積する
か或はＧｅイオン注入層上にＧｅ層を堆積したる後Ｇ　
ａ　Ａ　ｓ層を成長させるものである。Structure of the Invention The gist of the present invention is to form a Ge ion-implanted layer by implanting Ge ions into the Si substrate in order to obtain a GaAs layer with excellent crystallinity and electrical properties on the Si substrate. ,
Depositing the Ga As layer directly on the Ge ion implantation layer or depositing the Ge layer on the Ge ion implantation layer and then depositing the G
This is to grow an aAs layer.

これにより結晶性、電気的特性の優れたＧ　ａ　Ａ　ｓ
層を得るものである。As a result, GaAs with excellent crystallinity and electrical properties
It's about gaining layers.

実施例の説明 （実施例１） 第１図は本発明の一実施例である。（ａ）に示すＳｉ基
板１に、イオン注入法を用いてＧｅ（ゲルマニウム）イ
オン２を注入してＧｅイオン注入層３を形成する（ｂ）
。イオン注入は加速エネルギー５０ＫｅＶ　　で注入量
５×１０１５側−２である。ランプアーニール法を用い
１３００℃で１０秒間熱処理し注入イオンの活性化と注
入によって生じた結晶欠陥を回復せしめる。ＭＢＥ法を
用いてＧｅ層４を基板温度を６５０℃として、成長速度
１．２人／ｓｅｃで０．６ｐｒｎ成長する（Ｃ）。次に
Ｇｅ層４の上にＧ　ａ　Ａ　ｓ層５をＭＢＥ法を用いて
基板温度６２０℃で成長速度０．Ｉ　Ａ　／　ｍｉｎで
２ｐｍ成長した（ｄ）。Ｇ　ａ　Ａ　ｓ層５はシリコン
を添加して不純物濃度約１０　’　５儒−３である。電
子移動度は７，５００，７／Ｖ、ｓｅｃでほぼＧａＡｓ
＋基板上に成長したＧ　ａ　Ａ　ｓ層の電子移動度の約
８６％であり良好な結晶性を示している。一方従来のＳ
ｉ基板上にＧｅ層を堆積した後Ｇ　ａ　Ａ　ｓ層を成長
した場合のＧ　ａ　Ａ　ｓ層の電子移動度ば３，５００
　ｃｒｌ　／　Ｖ　。Description of Examples (Example 1) FIG. 1 shows an example of the present invention. Ge (germanium) ions 2 are implanted into the Si substrate 1 shown in (a) using an ion implantation method to form a Ge ion implantation layer 3 (b)
. The ion implantation was performed at an acceleration energy of 50 KeV and an implantation amount of 5.times.10@15 -2. A heat treatment is performed at 1300° C. for 10 seconds using a ramp annealing method to activate the implanted ions and recover crystal defects caused by the implantation. Using the MBE method, the Ge layer 4 is grown at a substrate temperature of 650° C. at a growth rate of 1.2 people/sec to 0.6 prn (C). Next, a Ga As layer 5 is formed on the Ge layer 4 using the MBE method at a substrate temperature of 620° C. and a growth rate of 0. Grows 2 pm at IA/min (d). The GaAs layer 5 is doped with silicon and has an impurity concentration of about 10'5 F-3. The electron mobility is 7,500,7/V, sec, which is almost GaAs.
The electron mobility was approximately 86% of that of the GaAs layer grown on the + substrate, indicating good crystallinity. On the other hand, the conventional S
When the Ga As layer is grown after depositing the Ge layer on the i-substrate, the electron mobility of the Ga As layer is 3,500.
crl/V.

気であった。Ｇ　ａ　Ａ　ｓ層の結晶性が良好なのはＳ
ｉ基板上に成長したＧｅの結晶性が良いだめである。I was curious. The crystallinity of the GaAs layer is good because of S.
The crystallinity of Ge grown on the i-substrate is a good problem.

これはＳｉ基板上に直接Ｇｅ層を成長する場合に比して
、Ｇｅ注入層を介してＧｅ層を形成するので、格子定数
の整合が良くなるためと推察している。This is presumed to be because the Ge layer is formed via the Ge injection layer, which improves the matching of lattice constants, compared to the case where the Ge layer is grown directly on the Si substrate.

（実施例２） 第２図に他の実施例を示す。実施例１と同様に（ａ）の
Ｓｉ基板１にＧｅ　イオン２を注入し、Ｇｅイオン注入
層３を形成する（ｂ）。Ｇｅ　イオン注入層３を活性化
し、結晶性を回復するため熱処理し、しかる後ＭＢＥ法
でＧｅ　　イオン注入層３上にＧ　ａ　Ａ　ｓ層４と形
成する（Ｃ）。実施例１との差はＧｅ層を形成せずに直
接Ｇ　ａ　Ａ　ｓ層６をＧθイオン注入層３上に堆積し
ている。Ｇ　ａ　Ａ　ｓ層６はシリコンを添加して不純
物濃度約１０１５＝ｉ−３である。電子移動度は、ア、
○○ｏ（７／ｖ、ｓｅｃであった。実施列１に比して、
電子移動度は劣るが、従来のＳｉ基板上にＧ。(Example 2) FIG. 2 shows another example. As in Example 1, Ge ions 2 are implanted into the Si substrate 1 of (a) to form a Ge ion implanted layer 3 (b). The Ge ion-implanted layer 3 is activated and heat treated to restore crystallinity, and then a GaAs layer 4 is formed on the Ge ion-implanted layer 3 by MBE (C). The difference from Example 1 is that a Ga As layer 6 is directly deposited on the Gθ ion-implanted layer 3 without forming a Ge layer. The GaAs layer 6 is doped with silicon and has an impurity concentration of about 1015=i-3. The electron mobility is a,
○○o(7/v, sec. Compared to implementation row 1,
G on a conventional Si substrate, although the electron mobility is inferior.

層を堆積した後Ｇ　ａ　Ａ　ｓを成長する方法【比して
電子移動度は大きいし又Ｓｉ　基板上にＧ　ａ　Ａ　ｓ
層を直接堆積した場合は、クラック、双晶等が発生する
が、実施例２ではその発生はなかった。これはＧ。A method of growing GaAs after depositing a layer [Comparatively, the electron mobility is large and GaAs is
If the layers were directly deposited, cracks, twins, etc. would occur, but in Example 2, no such occurrences occurred. This is G.

をイオン注入することにより、Ｇｅ　イオン注入層の格
子常数が大きくなり、Ｇ　ａ　Ａ　ｓ層との格子常数と
の不整合が緩和されたためではないかと考えている。We believe that this is because the lattice constant of the Ge ion-implanted layer increases by ion implantation, and the mismatch between the lattice constant and the Ga As layer is alleviated.

実施例では、Ｇｅのイオン注入法としてＳｉ基板に直接
注入したが、ＳｉＯ２等を介して注入しても良い。Ｓｉ
Ｏ２の厚みとしてはＧｅ注入層のピーク濃度が５１表面
近傍に位置する様にするのが望ましい。又Ｇｅ層、Ｇａ
Ａｓ層の成長法としてＭＢＥ法を用いたが、ＭＯＣＶＤ
法、ＩＣＢＥ法（ＬｏｎＣｌｕｓｔｅｒ　Ｂｅａｍ　Ｅ
ｐｉｔａｘｙ、）　　等を用いても良いし、それらの組
合せでも良い。又選択的にＧｅ注入層と形成して選択的
にＧ　ａ　Ａ　ｓ層を成長しても良いことは勿論である
。In the embodiment, Ge was directly implanted into the Si substrate as the ion implantation method, but it may also be implanted through SiO2 or the like. Si
It is desirable that the thickness of O2 be such that the peak concentration of the Ge injection layer is located near the surface of 51. Also, Ge layer, Ga
The MBE method was used as the growth method for the As layer, but MOCVD
ICBE method (LonCluster Beam E
pitaxy, ), etc., or a combination thereof. Of course, it is also possible to selectively form a Ge injection layer and selectively grow a GaAs layer.

発明の詳細 な説明した様に本発明は、８１基板上に結晶性電気的特
性の良好なＧ　ａ　Ａ　ｓ層を形成することが出来る方
法で電気−光回路等に用いる複合デバイスの基体として
その工業的価値は大きい。DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention provides a method for forming a GaAs layer with good crystalline electrical properties on an 81 substrate as a substrate for a composite device used for electrical-optical circuits, etc. It has great industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（ｄ）　、　第２図（ａ）〜（Ｃ）は本
発明の一実施例を説明するだめの工程概略図である。 １　・・・・・Ｓｉ基板、２・・・・−・Ｇｅイオン、
３・・・・Ｇｅイオン注入層、４・・・・・Ｇｅ層、５
・・・・・・Ｇ　ａ　Ａ　ｓ層。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名蔦１
図FIGS. 1(a) to (d) and FIGS. 2(a) to (C) are process schematic diagrams for explaining one embodiment of the present invention. 1...Si substrate, 2...--Ge ion,
3...Ge ion implantation layer, 4...Ge layer, 5
...G a As layer. Name of agent: Patent attorney Toshio Nakao and 1 other person Tsuta 1
figure

Claims (2)

【特許請求の範囲】[Claims] （１）シリコン基板に、イオン注入法を用いてＧｅのイ
オン注入層を形成した後、上記Ｇｅイオン注入層上にＧ
ａＡｓ層を堆積することを特徴とする半導体装置の製造
方法。(1) After forming a Ge ion implantation layer on a silicon substrate using an ion implantation method, a Ge ion implantation layer is formed on the Ge ion implantation layer.
A method for manufacturing a semiconductor device, comprising depositing an aAs layer. （２）シリコン基板にイオン注入法を用いてＧｅイオン
注入層を形成する工程、上記Ｇｅイオン注入層上にＧｅ
を堆積する工程、上記Ｇｅ層上にＧａＡｓを堆積する工
程を有することを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。(2) Step of forming a Ge ion implantation layer on a silicon substrate using an ion implantation method, a step of forming a Ge ion implantation layer on the Ge ion implantation layer.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: depositing GaAs on the Ge layer; and depositing GaAs on the Ge layer.
JP59185840A 1984-09-05 1984-09-05 Manufacture of semiconductor device Pending JPS6164119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59185840A JPS6164119A (en) 1984-09-05 1984-09-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59185840A JPS6164119A (en) 1984-09-05 1984-09-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6164119A true JPS6164119A (en) 1986-04-02

Family

ID=16177795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59185840A Pending JPS6164119A (en) 1984-09-05 1984-09-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6164119A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62130511A (en) * 1985-12-02 1987-06-12 Hitachi Ltd Manufacture of semiconductor element
JPH01170081A (en) * 1987-12-25 1989-07-05 Sumitomo Electric Ind Ltd Semiconductor substrate provided with superconductor layer
US7459354B2 (en) 2001-01-29 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device including top gate thin film transistor and method for manufacturing an active matrix device including top gate thin film transistor
JP2010508676A (en) * 2006-11-02 2010-03-18 アイメック Removal of impurities from semiconductor device layers
US8686472B2 (en) 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62130511A (en) * 1985-12-02 1987-06-12 Hitachi Ltd Manufacture of semiconductor element
JPH01170081A (en) * 1987-12-25 1989-07-05 Sumitomo Electric Ind Ltd Semiconductor substrate provided with superconductor layer
US7459354B2 (en) 2001-01-29 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device including top gate thin film transistor and method for manufacturing an active matrix device including top gate thin film transistor
JP2010508676A (en) * 2006-11-02 2010-03-18 アイメック Removal of impurities from semiconductor device layers
US8686472B2 (en) 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate

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