JPH05283350A - Manufacture of epitaxial semiconductor wafer - Google Patents

Manufacture of epitaxial semiconductor wafer

Info

Publication number
JPH05283350A
JPH05283350A JP10607592A JP10607592A JPH05283350A JP H05283350 A JPH05283350 A JP H05283350A JP 10607592 A JP10607592 A JP 10607592A JP 10607592 A JP10607592 A JP 10607592A JP H05283350 A JPH05283350 A JP H05283350A
Authority
JP
Japan
Prior art keywords
thin film
epitaxial
wafer
heat treatment
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10607592A
Other languages
Japanese (ja)
Inventor
Hisashi Adachi
尚志 足立
Masataka Horai
正隆 宝来
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KYUSHU ELECTRON METAL CO Ltd
Nippon Steel Corp
Original Assignee
KYUSHU ELECTRON METAL CO Ltd
Sumitomo Sitix Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KYUSHU ELECTRON METAL CO Ltd, Sumitomo Sitix Corp filed Critical KYUSHU ELECTRON METAL CO Ltd
Priority to JP10607592A priority Critical patent/JPH05283350A/en
Publication of JPH05283350A publication Critical patent/JPH05283350A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a manufacturing method of an epitaxial semiconductor wafer which can form a high quality silicon epitaxial thin film by reducing defect density of the epitaxial thin film. CONSTITUTION:A thermal treatment such as a treatment for holding an IG- treated wafer at 1000 deg.C for 3 or more minutes is carried out in an atmosphere containing hydrogen before vapor growth of a silicon thin film; thereby, a starting point of defect generation of the silicon thin film is eliminated from a wafer substrate and a vapor growth thin film is formed thereafter. Thereby, a silicon epitaxial thin film of extremely high quality having epitaxial defect density of 0.2 pieces/cm<2> or less in the thin film can be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、デバイスプロセスに
おいて高信頼性デバイスを可能にした高品質のエピタキ
シャル半導体ウェーハの製造方法に係り、シリコン薄膜
の気相成長前に水素を含む雰囲気内で熱処理して、ウェ
ーハ基板からシリコン薄膜の欠陥発生起点を消滅させ、
高品質シリコンエピタキシャル薄膜を成膜できるエピタ
キシャル半導体ウェーハの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a high-quality epitaxial semiconductor wafer which enables a highly reliable device in a device process, and heat treatment is performed in an atmosphere containing hydrogen before vapor phase growth of a silicon thin film. To eliminate the defect origin of the silicon thin film from the wafer substrate,
The present invention relates to a method for manufacturing an epitaxial semiconductor wafer capable of forming a high quality silicon epitaxial thin film.

【0002】[0002]

【従来の技術】半導体シリコンウェーハにエピタキシャ
ル薄膜を成長させるプロセスは、通常、気相成長装置で
行われ、以下の如きプロセスからなる。まず、水素ガス
などの不活性ガス雰囲気内で所定の温度域まで昇温し、
引き続き塩化水素を含むガス 等によるエッチングを数
分行い、表面コンタミネーション除去及びウェーハ表面
の活性化を行った後、シラン系ガスを用いてウェーハ表
面にエピタキシャル薄膜を成長させるものである。
2. Description of the Related Art A process for growing an epitaxial thin film on a semiconductor silicon wafer is usually carried out in a vapor phase growth apparatus and comprises the following processes. First, raise the temperature to a predetermined temperature range in an atmosphere of an inert gas such as hydrogen gas,
Subsequently, etching with a gas containing hydrogen chloride or the like is performed for several minutes to remove surface contamination and activate the wafer surface, and then a silane-based gas is used to grow an epitaxial thin film on the wafer surface.

【0003】しかし、この塩化水素を含むガス等による
エッチングプロセスでは、表面コンタミネーションの除
去不足、及び結晶引上げ過程ですでに育成された微小欠
陥を完全に消滅させることができず、さらに塩化水素ガ
スの選択エッチング性によりウェーハ表面のピットを増
加させる傾向にある。従って、塩化水素系ガスエッチン
グ後にエピタキシャル薄膜を成長させる際、上記の欠陥
等を起点として薄膜内に積層欠陥、転位などの欠陥を発
生させる。
However, in this etching process using a gas containing hydrogen chloride or the like, surface contamination cannot be removed sufficiently and minute defects already grown in the crystal pulling process cannot be completely eliminated. The pits on the wafer surface tend to increase due to the selective etching property. Therefore, when an epitaxial thin film is grown after etching with hydrogen chloride gas, defects such as stacking faults and dislocations are generated in the thin film starting from the above defects and the like.

【0004】[0004]

【発明が解決しようとする課題】一方、デバイスプロセ
ス工程内での重金属汚染によるデバイス特性の劣化要因
の低減方法としてイントリンシックゲッタリング(以下
IGという)処理を用いることがある。このIG処理
は、1100℃以上の熱処理により表面近傍数十μm程
度の酸素の外方拡散(Outdiffusion)を行
い、無欠陥層といわれるデヌーディットゾーン(以下D
Z層という)を形成させ、引き続いて600〜800℃
程度の低温処理により、DZ層以外のバルク内に酸素析
出物を形成させるものであるが、実際にはDZ層は無欠
陥ではなく、微小酸素析出物が高密度に存在し、その欠
陥を起点として上述の如くエピタキシャル薄膜に欠陥を
発生させる。
On the other hand, an intrinsic gettering (hereinafter referred to as IG) process may be used as a method for reducing the factor of deterioration of device characteristics due to heavy metal contamination in the device process step. This IG treatment performs outdiffusion of oxygen in the vicinity of the surface by several tens of μm by heat treatment at 1100 ° C. or higher, and a denuded zone (hereinafter referred to as D
Z layer) is formed, and subsequently 600 to 800 ° C.
Although the oxygen precipitates are formed in the bulk other than the DZ layer by a low temperature treatment of about a certain degree, in reality, the DZ layer is not defect-free, and minute oxygen precipitates are present at a high density, and the defects are the starting points. As described above, defects are generated in the epitaxial thin film as described above.

【0005】かかる欠陥の発生に対して、塩酸ガス濃度
やエッチング温度の管理によりこれを抑制する方法が採
用されてきたが、抜本的な解決には至らなかった。
A method of suppressing the occurrence of such defects by controlling the concentration of hydrochloric acid gas and the etching temperature has been adopted, but it has not been radically solved.

【0006】また、今日の半導体回路素子の微細化及び
高集積化は止まるところを知らず、著しい高密度化が進
み、これに伴いエピタキシャル薄膜の欠陥密度の低減
化、すなわち高品質化の要求は一層厳しくなり、従来の
エピタキシャル薄膜プロセスでは実用上、対応できなく
なりつつある。
Further, the miniaturization and high integration of semiconductor circuit elements today are unavoidably stopped, and the density is remarkably increased. Along with this, the demand for the defect density reduction of the epitaxial thin film, that is, the higher quality is further demanded. It is becoming severer, and the conventional epitaxial thin-film process is no longer practically applicable.

【0007】この発明は、従来のエピタキシャル薄膜プ
ロセスを改良して、エピタキシャル薄膜の欠陥密度の低
減化を図り、高品質シリコンエピタキシャル薄膜を成膜
できるエピタキシャル半導体ウェーハの製造方法の提供
を目的としている。
It is an object of the present invention to provide a method for manufacturing an epitaxial semiconductor wafer by improving the conventional epitaxial thin film process, reducing the defect density of the epitaxial thin film, and forming a high quality silicon epitaxial thin film.

【0008】[0008]

【課題を解決するための手段】この発明は、半導体ウェ
ーハの表面にシリコン薄膜を気相成長させるエピタキシ
ャル半導体ウェーハの製造方法において、イントリンシ
ックゲッタリング能力を付与する処理を受けたウェーハ
に水素を含む雰囲気内で熱処理を施した後、前記ウェー
ハ表面にシリコン薄膜を気相成長させることを特徴とす
るエピタキシャル半導体ウェーハの製造方法である。
According to the present invention, in a method for manufacturing an epitaxial semiconductor wafer in which a silicon thin film is vapor-deposited on the surface of a semiconductor wafer, the wafer that has been treated to impart intrinsic gettering ability contains hydrogen. A method for manufacturing an epitaxial semiconductor wafer, characterized in that a silicon thin film is vapor-deposited on the surface of the wafer after heat treatment in an atmosphere.

【0009】また、この発明は、上記の構成において、
1000℃以上の温度で3分間以上保持する熱処理条件
を特徴とするエピタキシャル半導体ウェーハの製造方法
である。
Further, according to the present invention, in the above structure,
It is a method for manufacturing an epitaxial semiconductor wafer, which is characterized by heat treatment conditions of holding at a temperature of 1000 ° C. or higher for 3 minutes or longer.

【0010】この発明において、水素を含む雰囲気内で
の熱処理条件は、薄膜欠陥密度を0.2個/cm2以下
とするには1000℃以上の高温が必要であり、好まし
くは1000℃〜1200℃である。また、熱処理時間
は上記の効果を得るには少なくとも3分間以上が必要
で、好ましくは5分〜30分である。
In the present invention, the heat treatment conditions in an atmosphere containing hydrogen require a high temperature of 1000 ° C. or higher, and preferably 1000 ° C. to 1200, in order to achieve a thin film defect density of 0.2 defects / cm 2 or less. ℃. Further, the heat treatment time is required to be at least 3 minutes or more to obtain the above effect, and is preferably 5 minutes to 30 minutes.

【0011】また、上記の熱処理温度までの昇温速度や
その雰囲気は、通常のエピタキシャルに用いられる条件
でよく、また1000℃以上の温度に昇温した後、水素
を含む雰囲気内で3分間以上保持されるように設定でき
れば、この発明による熱処理前の状態は問わない。
The temperature rising rate up to the heat treatment temperature and the atmosphere therefor may be the same as those used in ordinary epitaxial growth. After the temperature is raised to 1000 ° C. or higher, the temperature is raised to 3 minutes or longer in an atmosphere containing hydrogen. The state before the heat treatment according to the present invention does not matter as long as it can be set to be held.

【0012】この発明において、熱処理雰囲気は水素1
00%が望ましいが、Ar、Heなどの不活性ガスとH
2ガスの混合雰囲気でもよい。
In the present invention, the heat treatment atmosphere is hydrogen 1
00% is preferable, but H and inert gas such as Ar and He
A mixed atmosphere of two gases may be used.

【0013】[0013]

【作用】この発明は、半導体シリコンウェーハ上にシリ
コン薄膜を気相成長させるプロセスの前工程として、高
温水素アニール処理を導入することにより、半導体基板
からエピタキシャル薄膜欠陥の発生起点を消滅させるこ
とを特徴としている。
The present invention is characterized in that the starting point of the epitaxial thin film defect is eliminated from the semiconductor substrate by introducing a high temperature hydrogen annealing treatment as a pre-step of the process of vapor phase growing a silicon thin film on a semiconductor silicon wafer. I am trying.

【0014】すなわち、シリコン基板内の微小欠陥及び
IGプロセスにより作成した半導体ウェーハにおける、
DZ層内の微小酸素析出物を水素による還元作用によ
り、縮小または消滅させることにより、シリコン基板表
面近傍を無欠陥にすることで、欠陥密度が0.1個/c
2以下の高品質エピタキシャル薄膜を形成可能にした
ものである。
That is, in the microwafer in the silicon substrate and the semiconductor wafer created by the IG process,
The fine oxygen precipitates in the DZ layer are reduced or eliminated by the reducing action of hydrogen to make the vicinity of the surface of the silicon substrate defect-free, so that the defect density is 0.1 / c.
It is possible to form a high-quality epitaxial thin film of m 2 or less.

【0015】[0015]

【実施例】実施例1 CZ法による単結晶シリコンウェーハを用いて、鏡面仕
上げを施し、さらに水素100%雰囲気で、800℃、
4時間の昇温過程の後、窒素雰囲気中で、1000℃、
16時間の熱処理を行い、故意に酸素析出物を生成させ
た。さらに、酸素析出物が露出するように鏡面研摩にて
表面を仕上げた。その後、断面TEMにて試験ウェーハ
の表面近傍の状態を観察した。観察結果を模式的に図1
のAに示す如く、ウェーハ1表面に酸素析出物2や転位
などの欠陥が露出していることを確認した。
EXAMPLES Example 1 A single crystal silicon wafer obtained by the CZ method was used for mirror finishing, and then in a 100% hydrogen atmosphere at 800 ° C.
After the temperature rising process for 4 hours, in a nitrogen atmosphere, 1000 ° C.,
Heat treatment was performed for 16 hours to intentionally generate oxygen precipitates. Further, the surface was finished by mirror polishing so that the oxygen precipitates were exposed. Then, the state near the surface of the test wafer was observed with a cross-sectional TEM. Figure 1 schematically showing the observation results
It was confirmed that defects such as oxygen precipitates 2 and dislocations were exposed on the surface of the wafer 1 as shown in A of FIG.

【0016】上記の試験ウェーハを用いて、気相成長装
置内を水素100%雰囲気となし、1150℃、30分
間のこの発明による熱処理を行った。その後、断面TE
Mにて試験ウェーハの表面近傍の状態を観察した結果、
図1のBに模式的に示す如く、この発明による熱処理を
行った試験ウェーハは、表面から約4μm程度まで完全
に酸素析出物、転位などの欠陥を消滅させていることを
確認した。
Using the above-mentioned test wafer, the inside of the vapor phase growth apparatus was kept in a 100% hydrogen atmosphere and heat treatment according to the present invention was performed at 1150 ° C. for 30 minutes. After that, cross section TE
As a result of observing the state near the surface of the test wafer with M,
As schematically shown in FIG. 1B, it was confirmed that the test wafer which had been subjected to the heat treatment according to the present invention completely eliminated defects such as oxygen precipitates and dislocations up to about 4 μm from the surface.

【0017】次に、上記の欠陥を露出させた試験ウェー
ハを用いて、熱処理雰囲気をAr、O2、N2の他ガスに
置換して1150℃、30分間の熱処理をそれぞれ行っ
た。同様に断面TEMにて試験ウェーハの表面近傍の状
態を観察した結果、熱解離が僅かに認められるものの、
欠陥を完全消滅させることはできなかった。
Next, using the test wafer in which the above defects were exposed, the heat treatment atmosphere was replaced with another gas of Ar, O 2 and N 2 and heat treatment was performed at 1150 ° C. for 30 minutes, respectively. Similarly, as a result of observing the state near the surface of the test wafer with a cross-sectional TEM, although thermal dissociation is slightly observed,
The defect could not be completely eliminated.

【0018】従って、この発明による水素雰囲気中での
高温熱処理が、微小欠陥の熱解離作用のほかに、還元作
用による微小欠陥の縮小、消滅を促進することが分か
る。
Therefore, it is understood that the high temperature heat treatment in the hydrogen atmosphere according to the present invention promotes the thermal dissociation action of the microdefects and also the reduction and disappearance of the microdefects by the reduction action.

【0019】実施例2 エピタキシャル薄膜欠陥密度が約5個/cm2となるよ
うに、事前にIG処理した試験ウェーハを作製した。こ
の試験ウェーハを用いて、気相成長装置内を水素100
%雰囲となし、処理温度を800℃、900℃、100
0℃、1100℃、1200℃と種々温度で、それぞれ
5分間の熱処理を行った。
Example 2 A test wafer was prepared by IG treatment in advance so that the defect density of the epitaxial thin film was about 5 defects / cm 2 . Using this test wafer, 100
% No atmosphere, processing temperature is 800 ℃, 900 ℃, 100
Heat treatment was performed for 5 minutes at various temperatures of 0 ° C., 1100 ° C. and 1200 ° C., respectively.

【0020】その後引き続いて、塩化水素ガスでウェー
ハエッチングし、さらにトリクロロシランガスにて気相
成長薄膜形成を行った。得られたエピタキシャルウェー
ハをライトエッチング(Wright Etchin
g)にて選択エッチングをおこない、光学顕微鏡にて薄
膜内のエピタキシャル欠陥密度を測定した。
Then, subsequently, the wafer was etched with hydrogen chloride gas, and a vapor phase growth thin film was formed with trichlorosilane gas. The obtained epitaxial wafer is subjected to light etching (Wright Etchin
g), selective etching was performed, and the epitaxial defect density in the thin film was measured with an optical microscope.

【0021】この発明による水素雰囲気中での高温熱処
理の温度依存性を調べ、図2に処理温度と薄膜内のエピ
タキシャル欠陥密度との関係で示す。すなわち、同一処
理時間内では、処理温度が高温であるほど、欠陥抑制効
果が高いことが分かる。
The temperature dependence of the high temperature heat treatment in the hydrogen atmosphere according to the present invention was investigated, and FIG. 2 shows the relationship between the treatment temperature and the epitaxial defect density in the thin film. That is, it can be seen that, within the same processing time, the higher the processing temperature, the higher the effect of suppressing defects.

【0022】次に、処理温度を1000℃として、処理
時間を種々変化させてこの発明による水素雰囲気中での
高温熱処理を行い、薄膜形成を行った後、薄膜内のエピ
タキシャル欠陥密度を測定した。図3に処理時間と薄膜
内のエピタキシャル欠陥密度との関係で示す如く、同一
処理温度では、処理時間が長いほど、欠陥抑制効果が高
いことが分かる。
Next, the treatment temperature was set to 1000 ° C., the treatment time was variously changed, the high temperature heat treatment in the hydrogen atmosphere according to the present invention was performed to form the thin film, and then the epitaxial defect density in the thin film was measured. As shown in the relationship between the processing time and the epitaxial defect density in the thin film in FIG. 3, it can be seen that, at the same processing temperature, the longer the processing time, the higher the defect suppressing effect.

【0023】すなわち、この発明による水素雰囲気中で
の高温熱処理は、1000℃で3分以上、好ましくは5
分以上の処理により、ウェーハの表面近傍の微小欠陥を
縮小消滅させ、高品質のエピタキシャル薄膜が得られる
ことが分かる。
That is, the high temperature heat treatment in a hydrogen atmosphere according to the present invention is performed at 1000 ° C. for 3 minutes or longer, preferably 5 hours.
It can be seen that the high-quality epitaxial thin film can be obtained by reducing and eliminating the minute defects near the surface of the wafer by the above treatment.

【0024】[0024]

【発明の効果】この発明は、IG処理されたウェーハを
シリコン薄膜の気相成長前に水素を含む雰囲気内で熱処
理、例えば1000℃で3分以上保持する処理を施すこ
とにより、ウェーハ基板からシリコン薄膜の欠陥発生起
点を消滅させることができるため、その後の気相成長薄
膜形成にて薄膜内のエピタキシャル欠陥密度が0.2個
/cm2以下と、極めて高品質のシリコンエピタキシャ
ル薄膜を成膜できる。
According to the present invention, a wafer subjected to IG treatment is subjected to a heat treatment in an atmosphere containing hydrogen before the vapor phase growth of a silicon thin film, for example, a treatment of holding the wafer at 1000 ° C. for 3 minutes or more. Since the origin of defects in the thin film can be eliminated, it is possible to form an extremely high-quality silicon epitaxial thin film with an epitaxial defect density of 0.2 or less / cm 2 in the thin film in the subsequent vapor phase growth thin film formation. ..

【図面の簡単な説明】[Brief description of drawings]

【図1】断面TEMにて試験ウェーハの表面近傍の状態
を観察した結果を模式的に示す説明図であり、Aはこの
発明の熱処理前、Bはこの発明の熱処理後の状態を示
す。
FIG. 1 is an explanatory view schematically showing a result of observing a state in the vicinity of a surface of a test wafer by a cross-sectional TEM, A shows a state before heat treatment of the present invention, and B shows a state after heat treatment of the present invention.

【図2】処理温度と薄膜内欠陥密度との関係を示すグラ
フである。
FIG. 2 is a graph showing the relationship between processing temperature and defect density in a thin film.

【図3】処理時間と薄膜内欠陥密度との関係を示すグラ
フである。
FIG. 3 is a graph showing the relationship between processing time and defect density in a thin film.

【符号の説明】[Explanation of symbols]

1 ウェーハ 2 酸素析出物 1 wafer 2 oxygen precipitate

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年5月12日[Submission date] May 12, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0015[Correction target item name] 0015

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0015】[0015]

【実施例】実施例1 CZ法による単結晶シリコンウェーハを用いて、鏡面仕
上げを施し、さらに窒素100%雰囲気で、800℃、
4時間の熱処理の後、窒素雰囲気中で、1000℃、1
6時間の熱処理を行い、故意に酸素析出物を生成させ
た。さらに、酸素析出物が露出するように鏡面研摩にて
表面を仕上げた。その後、断面TEMにて試験ウェーハ
の表面近傍の状態を観察した。観察結果を模式的に図1
のAに示す如く、ウェーハ1表面に酸素析出物2や転位
などの欠陥が露出していることを確認した。
EXAMPLES Example 1 A single crystal silicon wafer obtained by the CZ method was used to perform mirror finishing, and then in a 100% nitrogen atmosphere at 800 ° C.
After heat treatment for 4 hours, in a nitrogen atmosphere, 1000 ° C., 1
Heat treatment was performed for 6 hours to intentionally generate oxygen precipitates. Further, the surface was finished by mirror polishing so that the oxygen precipitates were exposed. Then, the state near the surface of the test wafer was observed with a cross-sectional TEM. Figure 1 schematically showing the observation results
It was confirmed that defects such as oxygen precipitates 2 and dislocations were exposed on the surface of the wafer 1 as shown in A of FIG.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0019[Name of item to be corrected] 0019

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0019】実施例2 エピタキシャル薄膜欠陥密度が約個/cm2となるよ
うに、事前にIG処理した試験ウェーハを作製した。こ
の試験ウェーハを用いて、気相成長装置内を水素100
%雰囲となし、処理温度を800℃、900℃、100
0℃、1100℃、1200℃と種々温度で、それぞれ
5分間の熱処理を行った。
Example 2 A test wafer was prepared by IG processing in advance so that the defect density of the epitaxial thin film was about 1 defect / cm 2 . Using this test wafer, 100
% No atmosphere, processing temperature is 800 ℃, 900 ℃, 100
Heat treatment was performed for 5 minutes at various temperatures of 0 ° C., 1100 ° C. and 1200 ° C., respectively.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェーハの表面にシリコン薄膜を
気相成長させるエピタキシャル半導体ウェーハの製造方
法において、イントリンシックゲッタリング能力を付与
する処理を受けたウェーハに水素を含む雰囲気内で熱処
理を施した後、前記ウェーハ表面にシリコン薄膜を気相
成長させることを特徴とするエピタキシャル半導体ウェ
ーハの製造方法。
1. A method of manufacturing an epitaxial semiconductor wafer in which a silicon thin film is vapor-deposited on a surface of a semiconductor wafer, after the wafer that has been subjected to a treatment for imparting intrinsic gettering capability is subjected to a heat treatment in an atmosphere containing hydrogen. A method for manufacturing an epitaxial semiconductor wafer, comprising vapor-depositing a silicon thin film on the wafer surface.
【請求項2】 1000℃以上の温度で3分間以上保持
する熱処理条件を特徴とする請求項1記載のエピタキシ
ャル半導体ウェーハの製造方法。
2. The method for producing an epitaxial semiconductor wafer according to claim 1, wherein the heat treatment condition is to hold the temperature at 1000 ° C. or higher for 3 minutes or more.
JP10607592A 1992-03-30 1992-03-30 Manufacture of epitaxial semiconductor wafer Pending JPH05283350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10607592A JPH05283350A (en) 1992-03-30 1992-03-30 Manufacture of epitaxial semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10607592A JPH05283350A (en) 1992-03-30 1992-03-30 Manufacture of epitaxial semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH05283350A true JPH05283350A (en) 1993-10-29

Family

ID=14424480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10607592A Pending JPH05283350A (en) 1992-03-30 1992-03-30 Manufacture of epitaxial semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH05283350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000014783A1 (en) * 1998-09-07 2000-03-16 Shin-Etsu Handotai Co., Ltd. Epitaxial wafer and method for producing the same
US6548886B1 (en) 1998-05-01 2003-04-15 Wacker Nsce Corporation Silicon semiconductor wafer and method for producing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548886B1 (en) 1998-05-01 2003-04-15 Wacker Nsce Corporation Silicon semiconductor wafer and method for producing the same
WO2000014783A1 (en) * 1998-09-07 2000-03-16 Shin-Etsu Handotai Co., Ltd. Epitaxial wafer and method for producing the same

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