JPS63198334A - Manufacture of semiconductor silicon wafer - Google Patents

Abstract

PURPOSE:To prevent an IG effect given by the influence of an EP growing atmosphere from decreasing by epitaxially growing on a silicon mirror-surface wafer, and then heat-treating it under specific conditions. CONSTITUTION:In the manufacture of a silicon wafer for a semiconductor device obtained from a semiconductor silicon rod manufactured by a pulling method, a silicon mirror-surface wafer is epitaxially (EP) grown, and intrinsic- getter(IG)-heat treated at 650-900 deg.C for 4-20 hours. When the thus EP-grown wafer is IG-treated at a low temperature, desired internal fine defects are formed only in a substrate, the EP layer remains with no defect, and desired gettering effect is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing silicon wafers used in semiconductor devices such as LSIs and VLSIs.

[Prior Art] Conventionally, mirror-finished wafers have been used as silicon substrates for ICs and LSIs.

Recently, as the integration and density of LSIs, VLSIs, and devices have become higher and higher, evictional wafers, which have minute changes in dopant concentration and fewer crystal defects, are attracting attention.

[Problems to be solved by the invention: Although high-quality epitaxial (hereinafter referred to as EP) manufacturing is required, it is necessary to prevent contamination and crystal defects from occurring during the manufacturing process of ICs, LSIs, and VLSIs. It is necessary to impart a gettering effect called an intrinsic getter (hereinafter referred to as IG). Therefore, for example, as disclosed in Japanese Patent Application Laid-Open No. 58-85534 and Japanese Patent Application Laid-Open No. 58-44724, prior to EP growth, IG heat treatment is performed to prevent defects from propagating to the EP layer. A surface defect-free layer (hereinafter referred to as DZ) is formed on the surface of the substrate.

That is, EP growth was performed using a substrate that had been heat-treated in two stages: high temperature and low temperature, in which DZ was formed by outward diffusion of oxygen at high temperature, and then IG heat treatment was performed at low temperature for about 10 hours. A method has been used to do this.

However, with this method, the EP growth furnace is heated to 1100°C.
Because of the high temperature and reducing atmosphere containing hydrogen gas, internal micro defects (hereinafter referred to as
(referred to as BMD) will dissolve again, making it impossible to obtain the desired gettering effect. FIG. 4 shows this situation.

In other words, if the mirror-finished wafer was subjected to the two-step IG heat treatment, the interstitial oxygen concentration would be reduced in the device process as shown in FIG. 5, and the desired IC effect would be obtained. Furthermore, in the case of EP-grown wafers, the interstitial oxygen concentration decreases only slightly in the device process, and no IC effect is obtained.

In this way, mirror wafers that have been subjected to IG heat treatment and further subjected to EP growth can be used for ICs, LSIs, and VLSIs, and have improved device performance, such as improved hold time, improved productivity, etc. It hardly contributes to improving the non-defective product rate.

[Means for Solving the Problems] As described above, the present invention is intended to solve the problem that when using an EP wafer in a device, the conventional IG heat treatment cannot provide a sufficient gettering effect. In a method for manufacturing silicon wafers for semiconductor devices obtained from semiconductor silicon wafers produced by a pulling method, after performing EP growth on a silicon mirror wafer, under a temperature range of 650 ° C. to 900 ° C. IG heat treatment is performed for 4 to 20 hours, and preferably, EP growth is performed at a temperature of 1100°C or higher, and furthermore, the silicon mirror surface is heated at a temperature of 1100°C or higher prior to epitaxial growth. And, it must have been subjected to hydrogen gas treatment or hydrogen chloride gas etching treatment for 3 minutes or more, and more preferably, the temperature of the heat treatment is increased sequentially from 650°C to 900°C. It is characterized by

[Function] The present invention provides a mirror-finished wafer with two conventional heat treatments: heat treatment for forming a DZ shadow in advance and IG heat treatment for imparting BMD.
The reason why the step heat treatment is not performed is that, as described above, the BMD imparted by the IG heat treatment will be redissolved during EP growth, making it impossible to obtain the desired gettering effect.

In the present invention, after EP growth is performed on a mirror-finished wafer substrate, one stage of low-temperature IG heat treatment is performed. Oxygen atoms, which form the nucleus of BMD, exist in the substrate, and EPM does not contain any oxygen atoms. Therefore, if the wafer is subjected to low-temperature IG treatment after EP growth as in the present invention, , the desired BMD is formed only in the substrate, and the EPN can remain defect-free.

Therefore, there is no need to form a DZ on the surface of the substrate on the side where the EP is to be grown prior to the EP growth, unlike the conventional method.

Hereinafter, the present invention will be further explained in detail with reference to Examples.

[Example 1] A silicon dislocation-free single crystal ingot obtained by the Koczochralski method was sliced into wafers, which were subjected to a chamfering process, a lapping process, an etching process, and a mirror polishing process.

The physical properties of this wafer (hereinafter referred to as the original wafer) are P-type conductivity, crystal orientation (100), and resistivity 10-20Ω.
Saliva, diameter 150mmφ, thickness 625μ, oxygen concentration 14~
18 x 10'' atoms/cc (1979 edition of Annual Book of ASTM Standards [The following measured values are expressed in accordance with this standard).

Similar to the conventional method, 20 wafers were then placed in a heat treatment furnace and treated at 1100°C for 4 hours for outward diffusion of oxygen.
70 to form Z, and then to form BMD.
After heat treatment at 0° C. for 10 hours, an EP layer of about 20 μm was grown thereon using 5iC14 gas to obtain an IC substrate.

[Example 2] The original wafer of Example 1 was set in an epitaxial growth furnace, and an EP layer of about 20 μm was grown thereon using 5iC14 gas as in Example 1 to obtain an IC substrate.

[Example 3] The IC substrate obtained in Example 2 was further heated with Ar
A heat treatment was performed at 700° C. for 10 hours in an atmosphere to obtain another IC substrate.

[Example 4] An M○S memory IC was manufactured using the IC substrates obtained in Examples 1 to 3, and its hold time was measured.

The results are shown in FIG.

The horizontal axis in FIG. 1 represents the hold time, and the vertical axis represents the number of samples.

In the figure.

Curve A is EP obtained by Example 1, that is, the conventional method.
Curve B of the IC fabricated using a wafer as a substrate corresponds to Example 2, that is, EP was applied to a mirror-finished wafer that was not subjected to any heat treatment.
Curve C of the IC fabricated using the grown substrate corresponds to Example 3, which is one embodiment of the present invention, that is, the substrate was subjected to IG heat treatment after EP growth was performed on a mirror-surfaced wafer that was not subjected to any heat treatment. The distribution of the hold time with respect to the number of samples is shown for each of the ICs manufactured in .

As can be seen, the hold time of the first embodiment, that is, the conventional method, is short, and the hold time of the obtained IC is long in the case of the third embodiment.

That is, it can be seen that the EP wafer obtained by the present invention improves the performance of ICs compared to that obtained by the conventional method.

Further, in Example 3 according to the present invention, after IC fabrication, E
It was confirmed that a DZ of approximately 3 μm was formed at the interface between the P layer and the wafer substrate. This is considered to be because DZ is naturally formed at the start of EP growth using 5iC1 gas.

Note that FIG. 3 shows the interstitial oxygen concentration in the wafer after each process in Example 3 and the value of the interstitial oxygen concentration when it is finally made into a device. Similarly, FIG. 4 shows the interstitial oxygen concentration in the wafer after each process of Example 1,
It shows the value of interstitial oxygen concentration when the device is finally manufactured.

[Example 5] Raw wafers were heated in an EP furnace in an H2 gas atmosphere at 118
Except for the pretreatment at 0°C for 5 minutes, all the
An EP layer was grown in the same manner as in Example 3 to obtain an IC substrate.

[Example 6] The IC substrate obtained in Example 5 was heat treated at 700° C. for 4 hours in an Ar atmosphere to obtain another IC substrate.

[Example 7] The IC substrate obtained in Example 5 was subjected to a heat treatment in which the temperature was increased to 650'C or 900°C in sequence over 4 hours in an Ar atmosphere to obtain another IC substrate.

Two methods of increasing the temperature were tested: one in which the temperature was increased stepwise and one in which the temperature was increased smoothly.

[Example 8] Using the IC substrates obtained in Examples 5, 6 and 7, MOS
A memory cell C was prepared and its hold time was measured.

The results are shown in FIG.

The horizontal axis in FIG. 2 represents the hold time, and the vertical axis represents the number of samples.

In the figure, curve A represents the EP obtained in Example 1, that is, the conventional method.
The curve of the IC fabricated using a wafer as a substrate is as shown in Example 5.
The curve E of an IC manufactured using a substrate obtained by performing EP growth on the substrate after 5 minutes of pretreatment is the same as that obtained in Example 6-7, that is, Example 5, which is an embodiment of the present invention. This figure shows the distribution of hold times for each sample number for ICs manufactured using substrates obtained by further heat-treating the IC substrates.

As can be seen, the hold time of the IC obtained in Example 1, that is, the conventional method, is short, and in the case of Examples 5, 6, and 7, the hold time of the obtained IC is long.

That is, it can be seen that the EP wafer obtained by the present invention improves the performance of ICs compared to that obtained by the conventional method.

Note that Examples 5.6 and 7 according to the present invention are IC
After fabrication, a D of approximately 10μ is applied to the interface between the EP layer and the wafer substrate.
It was confirmed that Z was formed.

This is 11.0% before EP growth. This is because the pretreatment was carried out in , and the value is larger than that in Example 1.

Therefore, it is shown that devices that require control of the DZ width can be handled by appropriately selecting the temperature and time in the H process.

Also, 11. in Example 5 above. Experiments similar to those in Example 5 and below were also conducted using hydrogen chloride gas instead of the gas, but almost the same results were obtained.

As mentioned above, Ar gas was used as the heat treatment atmosphere in each example.
Similar results can be obtained with nitrogen, and similar results can be obtained with oxygen or a mixture of nitrogen and oxygen by simply removing the oxide film formed during heat treatment before the device fabrication process.

[Effects of the Invention] According to the present invention, the effect of the applied IG is not reduced due to the influence of the EP growth atmosphere, unlike in the conventional case.

Furthermore, as can be seen from the examples of the present invention, for devices that require control of the DZ width, before EP growth,
In the H or hydrogen chloride treatment, this can be handled by appropriately selecting the temperature and time.

Based on the above-mentioned effects, if the substrate according to the present invention is finally used in a device, the desired gettering effect will be exhibited, and both the device performance and the yield rate will improve.

Furthermore, if one embodiment of the present invention is used, the manufacturing process does not require the conventional two-step heat treatment for forming Z and for applying IG, but only heat treatment 1 for applying IG. Because it can be done just by doing the steps,
The time required for the process is greatly reduced and productivity is improved.

Patent applicant: Komatsu Electronics Kinen Co., Ltd. 1: EI TfiT Hold time 1st factor Bold tie lゎNo. 214 x 10”, Itoms/cc XIO”atoIIS7cc % 1. Indication of the case Patent Application No. 29556 of 1988 2. Name of the invention 3. Person making the amendment Relationship to the case Patent applicant 4. Date of amendment order April 28, 1988 5. Subject of the amendment (Attachment-1) Page 18 of [Detailed Description of the Invention J] of the Specification of the Application
After the row (last row),

[Brief explanation of the drawing]

FIG. 1 is a diagram comparing the hold time of a device obtained by an embodiment of the present invention with that of a device obtained by a conventional method. FIG. 2 is a diagram comparing the hold time of a device obtained by another embodiment of the present invention with that of a device obtained by a conventional method. FIG. 3 is a diagram showing interstitial oxygen levels in a wafer after passing through each process in an embodiment of the present invention. FIG. 4 is a diagram showing the interstitial oxygen concentration in the wafer after passing through each step of the conventional method. FIG. 5 is a diagram showing the interstitial oxygen concentration in a wafer after passing through each step of another conventional method. A: IC manufactured using a wafer using a conventional method
Distribution of hold time with respect to the number of samples 1; Izumi. B: Distribution curve of hold time versus number of samples for ICs manufactured using wafers using another conventional method. C...Distribution curve of hold time with respect to the number of samples of ICs manufactured using a wafer according to an embodiment of the present invention. D...Distribution curve of hold time with respect to the number of samples for ICs manufactured using wafers according to yet another conventional method. E... Provides a section for the number of samples of ICs manufactured using wafers according to another embodiment of the present invention. Shock 1 yen-2) Drawing surface-sec. Hold time Figure 1 Hold time Figure 2

Claims (1)

[Claims] 1. In a method for manufacturing silicon wafers for semiconductor devices, after epitaxial growth is performed on a silicon mirror-finished wafer, heat treatment is performed at a temperature range of 650° C. to 900° C. for 4 hours to 20 hours. A method for manufacturing silicon wafers for semiconductor devices. 2. The method of manufacturing a silicon wafer for a semiconductor device according to claim 1, wherein the epitaxial growth is performed at a temperature of 1100° C. or higher. 3. Manufacturing a silicon wafer for semiconductor devices according to claim 1 or 2, wherein the silicon mirror-finished wafer is subjected to hydrogen gas treatment at 1100° C. or higher for 3 minutes or more prior to epitaxial growth. Method. 4. The silicon wafer for semiconductor devices according to claim 1 or 2, wherein the silicon mirror-finished wafer is subjected to hydrogen chloride gas etching treatment at 1100° C. or higher for 3 minutes or more prior to epitaxial growth. manufacturing method. 5. The method for manufacturing a silicon wafer for a semiconductor device according to any one of claims 1 to 4, wherein the temperature of the heat treatment is gradually increased from 650°C to 900°C.