JPH03185831A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03185831A
JPH03185831A JP32378989A JP32378989A JPH03185831A JP H03185831 A JPH03185831 A JP H03185831A JP 32378989 A JP32378989 A JP 32378989A JP 32378989 A JP32378989 A JP 32378989A JP H03185831 A JPH03185831 A JP H03185831A
Authority
JP
Japan
Prior art keywords
temperature range
temperature
substrate
defects
hours
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32378989A
Other languages
Japanese (ja)
Inventor
Hiroaki Yamamoto
博昭 山本
Noboru Soga
曽我 昇
Tetsuo Akagi
哲郎 赤城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Electronic Metals Co Ltd filed Critical Komatsu Electronic Metals Co Ltd
Priority to JP32378989A priority Critical patent/JPH03185831A/en
Publication of JPH03185831A publication Critical patent/JPH03185831A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a nondefective layer also under the interface between a substrate and an epitaxial layer, by holding a semiconductor silicon substrate in a first specified temperature range, increasing the temperature at a specified rate, from the first temperature range to a second specified temperature range, and holding the substrate for a period shorter than or equal to a specified interval. CONSTITUTION:A semiconductor silicon substrate 1 is held for 8 hours or less in a first temperature range from 450 deg.C to 600 deg.C. The temperature is increased from the first temperature range to the second temperature range from 750 deg.C to 900 deg.C, at a rate of 5 deg.C/min. The substrate is held for 4 hours or less in the second temperature range. An epitaxial layer 2 is formed on the surface of the semiconductor silicon substrate 1 after the holding in the second temperature range is finished. That is, by setting the second temperature range to be from 750 deg.C to 900 deg.C, the size of a defect is restricted within a radius capable of dissolution and outward diffusion in the temperature range of a subsequent epitaxial process. Hence the dissolution and outward diffusion of defects are progressed. Thereby a nondefective layer 4 of about 10mum in thickness is formed under the interface between the substrate surface and the epitaxial layer.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置の製造方法において、とくに半導
体シリコン基板表面にエピタキシャル成長を行なうもの
にあって、成長に先立ち、基板に対し不純物等の除去の
ため施されるイントリンシック・ゲッタ(以下IGとい
う)技術を用いた半導体装置の製造方法に関わる。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, in particular a method in which epitaxial growth is performed on the surface of a semiconductor silicon substrate. The present invention relates to a method for manufacturing semiconductor devices using intrinsic getter (hereinafter referred to as IG) technology.

[従来の技術] 従来、その表面にエピタキシャル成長を行なう半導体シ
リコン基板に適用される技術として、たとえば、特公昭
62−16537号公報に開示されているように、ゲッ
ターサイトとして働く酸素析出核(以下欠陥という)を
、デバイス作製領域に近くなるよう基板表層にまで形成
させ、不純物の捕捉効果を高めたものがある。この従来
技術は、基本的には欠陥が、エピタキシャル成長を行な
う前の基板本体表面にまで達していることが重要な点で
、この熱処理方法により、それまでエピタキシャル成長
前に必要とされていたボリシング工程を省くことができ
るようにしている。
[Prior Art] Conventionally, as a technology applied to a semiconductor silicon substrate on which epitaxial growth is performed, for example, as disclosed in Japanese Patent Publication No. 62-16537, oxygen precipitated nuclei (hereinafter referred to as defects) that act as getter sites have been disclosed. ) is formed on the surface layer of the substrate close to the device fabrication area to enhance the effect of trapping impurities. The important point in this conventional technology is that the defects basically reach the surface of the substrate body before epitaxial growth, and this heat treatment method eliminates the borizing process that was previously required before epitaxial growth. I'm trying to make it possible to omit it.

[発明が解決しようとする課題] しかしながら、前記従来技術による1000℃〜130
0℃の熱処理工程後では、基板中に成長の進んだ欠陥が
多く発生する。これらの欠陥の大きさは、次のエピタキ
シャル成長工程の温度範囲(1100〜1200℃)で
溶体化可能な臨界半径以上であるため、そのまま残存し
、エピタキシャル層へ伝播する。
[Problems to be Solved by the Invention] However, according to the prior art, the
After the heat treatment process at 0° C., many defects with advanced growth occur in the substrate. Since the size of these defects is larger than the critical radius that can be dissolved in the temperature range (1100 to 1200° C.) of the next epitaxial growth step, they remain as they are and propagate to the epitaxial layer.

いわゆる欠陥の突き抜は現象が起きる。そうして、結局
は不良品を発生させることになる。
A so-called defect penetration phenomenon occurs. This ultimately results in the production of defective products.

[課題を解決するための手段] 本発明は、上記従来技術の欠点を解決すべくなされたも
ので、半導体装置の製造方法において、半導体シリコン
基板を450℃乃至600℃の第一の温度域で8時間以
下保持する工程と、第一の温度域から、750℃乃至9
00℃の第二の温度域まで5℃/分以下の速度で昇温し
て、この第二の温度域で4時間以下保持する工程と、第
二の温度域での保持終了後の前記半導体シリコン基板表
面に、エピタキシャル層を形成する工程とから成ること
を特徴としている。
[Means for Solving the Problems] The present invention has been made to solve the above-mentioned drawbacks of the prior art, and includes a method for manufacturing a semiconductor device, in which a semiconductor silicon substrate is heated in a first temperature range of 450°C to 600°C. A step of holding for 8 hours or less and a temperature range of 750°C to 9°C from the first temperature range.
A step of increasing the temperature to a second temperature range of 00°C at a rate of 5°C/min or less and holding it in this second temperature range for 4 hours or less, and after the holding in the second temperature range is completed, the semiconductor It is characterized by comprising a step of forming an epitaxial layer on the surface of a silicon substrate.

[作用] 本発明は、第二の温度域を750℃〜900℃に設定す
ることで、形成される欠陥の大きさを、次のエビタキシ
ャル工程の温度範囲で溶体化や外方拡散可能な半径にと
どめる。したがって、エビタキシャル工程では、欠陥の
溶体化や外方拡散が行なわれる。これにより、基板表面
にはエピタキシャル層との界面下にさらに、 10μI
程度の無欠陥層が形成される。
[Function] By setting the second temperature range to 750°C to 900°C, the present invention can reduce the size of defects that can be dissolved and outwardly diffused in the temperature range of the next epitaxial process. Stay within the radius. Therefore, in the epitaxial process, defects are dissolved into solution and diffused out. As a result, an additional 10μI was added to the substrate surface below the interface with the epitaxial layer.
A defect-free layer with a certain degree is formed.

前記のように、もし第二の温度域を従来のように100
0℃〜1300℃にすれば、半導体基板中に生じる欠陥
は、臨界半径を越えて成長が進み、その後のエビタキシ
ャル工程の雰囲気では再び溶体化することがない。残存
した欠陥は、エピタキシャル成長にともない伝播してし
まう危険性が大きい。
As mentioned above, if the second temperature range is 100
If the temperature is 0° C. to 1300° C., defects occurring in the semiconductor substrate will grow beyond the critical radius and will not be dissolved again in the atmosphere of the subsequent epitaxial process. There is a high risk that the remaining defects will propagate during epitaxial growth.

これに対し、本発明に採用した、750℃〜900℃の
第二の温度域では、欠陥は基板全体に発生はするものの
、充分に成長せず、したがって次のエピタキシャル成長
の雰囲気では溶体化が起きたり、表面近傍にあるものは
基板外へ拡散したりしてしまう。
On the other hand, in the second temperature range of 750°C to 900°C adopted in the present invention, although defects occur throughout the substrate, they do not grow sufficiently, and therefore, solutionization occurs in the atmosphere for the next epitaxial growth. Or, those near the surface may diffuse out of the substrate.

このように、本発明は、エピタキシャル成長工程の雰囲
気を利用して、基板本体表面に、エピタキシャル層と同
時に無欠陥層をも形成するものである。
In this manner, the present invention utilizes the atmosphere of the epitaxial growth process to form a defect-free layer on the surface of the substrate body at the same time as the epitaxial layer.

なお、第一の温度域(450℃乃至600℃)は、欠陥
の核となる酸素析出核を作り込む温度として重要である
。この温度域で8時間以下保持するのは、欠陥密度を確
保するために必要なのもので、8時間で、この密度がほ
ぼ平衡に達するから、これ以上保持する必要はない。第
二の温度域の750℃乃至900℃は、作り込まれた欠
陥が臨界半径以上に成長しないために採用された温度域
である。この温度域まで5℃/分以下で昇温していくの
は、5℃/分を越える速度で急激に上げると5450℃
〜600℃の熱処理中に作り込んだ欠陥が成長できずに
消失するおそれがある。さらに、第二の温度域で、4時
間以下の保持にとどめるのは、作り込んだ欠陥のうち、
次のエビタキシャル工程の温度雰囲気で、エピタキシャ
ル層の界面下近傍にあるものは消失するが、基板内部の
ものは消失しない程度にまで成長させるために必要とな
るからである。
Note that the first temperature range (450° C. to 600° C.) is important as a temperature for creating oxygen precipitation nuclei that become the core of defects. Holding in this temperature range for 8 hours or less is necessary to ensure the defect density, and since this density almost reaches equilibrium in 8 hours, there is no need to hold it any longer. The second temperature range of 750° C. to 900° C. is a temperature range adopted to prevent the created defects from growing beyond the critical radius. Raising the temperature to this temperature range at a rate of 5°C/min or less is 5450°C if the temperature is rapidly raised at a rate exceeding 5°C/min.
There is a possibility that defects created during heat treatment at ~600°C cannot grow and disappear. Furthermore, in the second temperature range, the retention time is limited to 4 hours or less because of the defects created.
This is necessary in order to grow the epitaxial layer to such an extent that in the temperature atmosphere of the next epitaxial step, the material near the interface of the epitaxial layer disappears, but the material inside the substrate does not disappear.

[実施例1] 酸素濃度14.0X10”atoms/cc [Old
 ASTM規格による]の鏡面シリコンウェーハを、第
一の温度域(600℃〉で4時間保持した後、第二の温
度域(SOO℃)まで、0.5℃/分で昇温して、昇温
後2時間保持した。さらに、上記条件で熱処理した鏡面
ウェーハの上に5μ園の厚さでシリコンエピタキシャル
層を常法により成長させた。
[Example 1] Oxygen concentration 14.0×10”atoms/cc [Old
A mirror-finished silicon wafer (according to ASTM standard) was held at the first temperature range (600°C) for 4 hours, and then heated at a rate of 0.5°C/min to the second temperature range (SOO°C). After heating, the wafer was held for 2 hours.Furthermore, a silicon epitaxial layer was grown to a thickness of 5 μm by a conventional method on the mirror-finished wafer heat-treated under the above conditions.

こうして処理を終えたシリコンウェーハを、1000℃
で16時間熱処理し、骨間して欠陥の観察を行なった。
The silicon wafer that has been processed in this way is heated to 1000℃.
After heat treatment for 16 hours, defects were observed between the bones.

第1図は、この骨間面の拡大図である。第1図からも明
らかなように、本実施例によるものは、エピタキシャル
層の下、シリコン基板本体表層にも、無欠陥層が10〜
30μ園、制御よく形成され、さらに基板内部には、ゲ
ッタ効果を発揮する結晶欠陥が充分に作られている。
FIG. 1 is an enlarged view of this interosseous surface. As is clear from FIG. 1, in this example, there is a defect-free layer of about 10 to 100% below the epitaxial layer and also on the surface layer of the silicon substrate body.
The crystal defects of 30 μm are formed in a well-controlled manner, and there are enough crystal defects inside the substrate to exhibit the getter effect.

[実施例2] 酸素濃度14.0X10”atoms/cc [01d
 ASTM規格による]のエツチドシリコンウェーハを
、第一の温度域(600℃)で4時間保持した後、第二
の温度域(800℃)まで、0.5℃ノ分で昇温して、
昇温後2時間保持した。さらに、上記条件で熱処理した
エツチドウェーハを15μmM面研磨し、その上に5μ
mの厚さでシリコンエピタキシャル層を常法により成長
させた。
[Example 2] Oxygen concentration 14.0×10”atoms/cc [01d
After holding an etched silicon wafer (according to ASTM standard) in a first temperature range (600°C) for 4 hours, the temperature was raised to a second temperature range (800°C) at a rate of 0.5°C,
After raising the temperature, it was held for 2 hours. Furthermore, the etched wafer heat-treated under the above conditions was subjected to 15 μm M surface polishing, and then 5 μm
A silicon epitaxial layer was grown to a thickness of m by a conventional method.

こうして処理を終えたシリコンウェーハを、1000℃
で16時間熱処理し、襞間して欠陥の観察を行なった。
The silicon wafer that has been processed in this way is heated to 1000℃.
The film was heat-treated for 16 hours, and then folded and observed for defects.

結果は、実施例1と同様であった。The results were similar to Example 1.

なお、上記2つの実施例のほかに、第一の温度域、第二
の温度域、保持時間、及び第一の温度域から第二の温度
域への昇温速度を、それぞれ本発明の構成に従って種々
変化させて同様の処理を行なったが、上記2つの実施例
とほぼ同様の結果が得られた。
In addition to the above two embodiments, the first temperature range, the second temperature range, the holding time, and the rate of temperature increase from the first temperature range to the second temperature range are each set according to the structure of the present invention. The same process was carried out with various changes according to the above, and almost the same results as in the above two examples were obtained.

[参考例1] 酸素濃度14.0X10”atoms/cc [Old
 ASTM規格による]の鏡面シリコンウェーハを、第
一の温度域(600℃)で4時間保持した後、1000
℃まで、0.5℃/分で昇温して、昇温後2時間保持し
た。さらに、上記条件で熱処理した鏡面ウェーハの上に
5μmの厚さでシリコンエピタキシャル層を常法により
成長させた。
[Reference Example 1] Oxygen concentration 14.0×10”atoms/cc [Old
According to the ASTM standard], a mirror-finished silicon wafer was held in the first temperature range (600°C) for 4 hours, and then heated to 1000°C.
The temperature was raised to 0.5°C/min and held for 2 hours after the temperature was raised. Further, a silicon epitaxial layer with a thickness of 5 μm was grown by a conventional method on the mirror-finished wafer heat-treated under the above conditions.

こうして処理を終えたシリコンウェーハを、1000℃
で16時間熱処理し、襞間して欠陥の観察を行なった。
The silicon wafer that has been processed in this way is heated to 1000℃.
The film was heat-treated for 16 hours, and then folded and observed for defects.

第2図は、この骨間面の拡大図である。第2図からも明
らかなように、本参考例によるものは、エピタキシャル
層より下の、基板本体表層の無欠陥層はほとんど形成さ
れておらず、エピタキシャル層へ欠陥の突き抜けも多数
見られる。
FIG. 2 is an enlarged view of this interosseous surface. As is clear from FIG. 2, in this reference example, almost no defect-free layer was formed on the surface layer of the substrate body below the epitaxial layer, and many defects penetrated into the epitaxial layer.

すなわち、この参考例のように、第2の温度域に相当す
る温度が、1000℃である場合は、結晶欠陥の成長が
進んで、サイズが巨大化し、エピタキシャル工程中にも
エピタキシャル層との界面下に欠陥が残留し、最終的に
は無欠陥でなければならないエピタキシャル層にまで欠
陥の突き抜けが起こることが分かる。
In other words, when the temperature corresponding to the second temperature range is 1000°C as in this reference example, the growth of crystal defects progresses, the size becomes huge, and the interface with the epitaxial layer occurs during the epitaxial process. It can be seen that defects remain underneath, and that defects eventually penetrate into the epitaxial layer, which should be defect-free.

[参考例2] 酸素濃度18.0X10”atoms/cc [Old
 ASTM規格による]のエツチドシリコンウェーハを
、第一の温度域(600℃)で4時間保持した後、10
00℃まで、0.5℃ノ分で昇温して、昇温後2時間保
持した。さらに、上記条件で熱処理したエツチドウェー
ハを15μm@面研磨し、その上に5μmの厚さでシリ
コンエピタキシャル層を常法により成長させた。
[Reference Example 2] Oxygen concentration 18.0×10”atoms/cc [Old
An etched silicon wafer (according to ASTM standard) was kept in the first temperature range (600°C) for 4 hours, and then
The temperature was raised to 00°C at a rate of 0.5°C and held for 2 hours after the temperature was raised. Further, the etched wafer heat-treated under the above conditions was polished to a depth of 15 .mu.m, and a silicon epitaxial layer was grown thereon to a thickness of 5 .mu.m by a conventional method.

こうして処理を終えたシリコンウェーハを、1000℃
で16時間熱処理し、襞間して欠陥の観察を行なった。
The silicon wafer that has been processed in this way is heated to 1000℃.
The film was heat-treated for 16 hours, and then folded and observed for defects.

結果は、参考例1と同様であった。The results were similar to those in Reference Example 1.

なお、上記2つの参考例のほかに、第一の温度域、保持
時間、及び第一の温度域から第二の温度域への昇温速度
を、それぞれ本発明の構成に従って種々変化させ、第二
の温度域に当る温度をtoo。
In addition to the above two reference examples, the first temperature range, the holding time, and the rate of temperature increase from the first temperature range to the second temperature range were variously changed according to the configuration of the present invention. The temperature in the second temperature range is too.

℃以上に設定して同様の処理を行なったが、上記2つの
参考例とほぼ同様の結果が得られた。
A similar process was carried out at a temperature higher than 0.degree. C., but almost the same results as in the above two reference examples were obtained.

[発明の効果] 本発明の製造方法によれば、第二の温度域が750℃乃
至900℃に設定されるため、欠陥のサイズが制御され
し、次のエピタキシャル層程の温度雰囲気で溶体化ある
いは外方拡散して、エピタキシャル層との界面下にも無
欠陥層を形成することができる。したがって、エピタキ
シャル層に欠陥の突き抜けも起きない。製品歩留が向上
する結果、生産性も上がる。
[Effects of the Invention] According to the manufacturing method of the present invention, since the second temperature range is set at 750°C to 900°C, the size of defects is controlled and solution treatment is performed in an atmosphere at a temperature similar to that of the next epitaxial layer. Alternatively, by outward diffusion, a defect-free layer can also be formed under the interface with the epitaxial layer. Therefore, defects do not penetrate through the epitaxial layer. As a result of improved product yield, productivity also increases.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明による製造方法を用いて作製したシリ
コン基板の骨間断面拡大図。 第2図は、従来の製造方法を用いて作製したシリコン基
板の骨間断面拡大図。 1・・・・シリコン基板 2・・・・エピタキシャル層 3・・・・欠陥 4・・・・無欠陥層 手続補正書 (方式) %式% 事件の表示 平成1年特許願第323789号 2゜ 発明の名称 半導体装置の製造方法 3゜ 補正をする者 事件との関係
FIG. 1 is an enlarged view of an interosseous cross section of a silicon substrate manufactured using the manufacturing method according to the present invention. FIG. 2 is an enlarged view of an interosseous cross section of a silicon substrate manufactured using a conventional manufacturing method. 1...Silicon substrate 2...Epitaxial layer 3...Defect 4...Defect-free layer Procedure amendment (method) % formula % Display of incident 1999 Patent Application No. 323789 2゜Title of invention: Method of manufacturing semiconductor devices 3゜Relationship with the amended case

Claims (1)

【特許請求の範囲】[Claims] 1 半導体シリコン基板を450℃乃至600℃の第一
の温度域で8時間以下保持する工程と、第一の温度域か
ら、750℃乃至900℃の第二の温度域まで5℃/分
以下の速度で昇温して、この第二の温度域で4時間以下
保持する工程と、第二の温度域での保持終了後の前記半
導体シリコン基板表面に、エピタキシャル層を形成する
工程とから成る半導体装置の製造方法。
1. A step of holding the semiconductor silicon substrate in a first temperature range of 450°C to 600°C for 8 hours or less, and a step of holding the semiconductor silicon substrate at a rate of 5°C/min or less from the first temperature range to a second temperature range of 750°C to 900°C. A semiconductor comprising the steps of raising the temperature at a rapid rate and holding it in this second temperature range for 4 hours or less, and forming an epitaxial layer on the surface of the semiconductor silicon substrate after the holding in the second temperature range is completed. Method of manufacturing the device.
JP32378989A 1989-12-15 1989-12-15 Manufacture of semiconductor device Pending JPH03185831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32378989A JPH03185831A (en) 1989-12-15 1989-12-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32378989A JPH03185831A (en) 1989-12-15 1989-12-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03185831A true JPH03185831A (en) 1991-08-13

Family

ID=18158634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32378989A Pending JPH03185831A (en) 1989-12-15 1989-12-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03185831A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587325A (en) * 1992-03-31 1996-12-24 Mitel Corporation Method of preparing antimony doped semiconductor with intrinsic gettering
WO2002025717A1 (en) * 2000-09-20 2002-03-28 Shin-Etsu Handotai Co.,Ltd. Silicon wafer and silicon epitaxial wafer and production methods therefor
WO2003009365A1 (en) * 2001-07-10 2003-01-30 Shin-Etsu Handotai Co.,Ltd. Silicon wafer manufacturing method, silicon epitaxial wafer manufacturing method, and silicon epitaxial wafer
US6537368B2 (en) 1997-02-26 2003-03-25 Memc Electronic Materials Spa Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
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Cited By (17)

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US5587325A (en) * 1992-03-31 1996-12-24 Mitel Corporation Method of preparing antimony doped semiconductor with intrinsic gettering
US6537368B2 (en) 1997-02-26 2003-03-25 Memc Electronic Materials Spa Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US6849119B2 (en) 1997-02-26 2005-02-01 Memc Electronic Materials, Inc. Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6896728B2 (en) 1997-04-09 2005-05-24 Memc Electronic Materials, Inc. Process for producing low defect density, ideal oxygen precipitating silicon
US7229693B2 (en) 1997-04-09 2007-06-12 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
US7442253B2 (en) 1997-04-09 2008-10-28 Memc Electronic Materials, Inc. Process for forming low defect density, ideal oxygen precipitating silicon
US6849901B2 (en) 1998-09-02 2005-02-01 Memc Electronic Materials, Inc. Device layer of a silicon-on-insulator structure having vacancy dominated and substantially free of agglomerated vacancy-type defects
US6713370B2 (en) 1998-09-02 2004-03-30 Memc Electronic Materials, Inc. Process for the preparation of an ideal oxygen precipitating silicon wafer capable of forming an enhanced denuded zone
US6686260B2 (en) 1998-09-02 2004-02-03 Memc Electronics Materials, Inc. Process for producing thermally annealed wafers having improved internal gettering
JP2009147357A (en) * 1998-09-02 2009-07-02 Memc Electron Materials Inc Silicon on insulator structure from low defect density single crystal silicon
US6666915B2 (en) 1999-06-14 2003-12-23 Memc Electronic Materials, Inc. Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
JP2002100631A (en) * 2000-09-20 2002-04-05 Shin Etsu Handotai Co Ltd Silicon wafer, silicon epitaxial wafer and method for manufacturing these
US6858094B2 (en) 2000-09-20 2005-02-22 Shin-Etsu Handotai Co., Ltd. Silicon wafer and silicon epitaxial wafer and production methods therefor
WO2002025717A1 (en) * 2000-09-20 2002-03-28 Shin-Etsu Handotai Co.,Ltd. Silicon wafer and silicon epitaxial wafer and production methods therefor
JPWO2003009365A1 (en) * 2001-07-10 2004-11-11 信越半導体株式会社 Method for manufacturing silicon wafer, method for manufacturing silicon epitaxial wafer, and silicon epitaxial wafer
WO2003009365A1 (en) * 2001-07-10 2003-01-30 Shin-Etsu Handotai Co.,Ltd. Silicon wafer manufacturing method, silicon epitaxial wafer manufacturing method, and silicon epitaxial wafer
US7033962B2 (en) 2001-07-10 2006-04-25 Shin-Etsu Handotai Co., Ltd. Methods for manufacturing silicon wafer and silicone epitaxial wafer, and silicon epitaxial wafer

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