JPS5856343A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the characteristic of a semiconductor element, and moreover to eliminate trouble at manufacture of semiconductor device by a method wherein the heat treatment is performed to a silicon substrate by the temperature rising speed of 5 deg.C/min or less, and at the maximum reaching temperature of 950 deg.C or less. CONSTITUTION:The heat treatment is performed to the silicon substrate by the temperaure rising speed of 5 deg.C/min or less, and at the maximum reaching temperature of 950 deg.C or less. By performing the treatment of substrate before formation of the semiconductor element by this way, the intrinsic gettering effect necessary and sufficient after completion of the semiconductor element can be obtained, and moreover generation of trouble to be caused by excess growth of internal crystal defects is eliminated. Accordingly, the treatment thereof has a large effect for enhancement of characteristic of the semiconductor device and elimination of trouble.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pretreatment process in semiconductor device manufacturing, that is, a substrate treatment process before semiconductor element formation.

(3,1) In general, factors that have a large effect on the characteristic defects of semiconductor devices include so-called process-induced defects and harmful impurities induced by the manufacturing process. These defects and impurities not only reduce the lifetime of carriers, but also have a serious adverse effect on device characteristics due to spike diffusion and the like in the impurity diffusion process.

In order to prevent the occurrence of these defects in the device operating area and to remove harmful impurities,
In addition, crystal defects are intentionally generated, and a denuded zone (De
By forming a region called nad@dZon (hereinafter referred to as Z) and gettering harmful impurities mixed in D and Z to internal crystal defects, the region related to device operation is cleaned by K. , the so-called intrinsic gettering method
(hereinafter referred to as the IQ method) has been incorporated into the manufacturing process.

While giving IG effect, is it good? In order to enable effective gettering, KD, Z, and width are set to the minimum necessary, and the density of internal crystal defects is as large as possible (preferably, 10'/- or more).

The currently known methods for forming D, Z, and internal crystal defects will be explained below with reference to the drawings. 3.2) Stepwise heat treatment is the first method for forming D, Z, and internal crystal defects. . In this method, Ueno 1 is subjected to three stages of heat treatment as described below.

[)N, in an atmosphere, the wafer was exposed to a temperature of 1100°C.
Heat treatment is performed at S degrees for 20 hours.

As a result of this heat treatment, as schematically shown in the cross-sectional view of the wafer in FIG. 1(a), the wafer is out-diffused to the outside of the interstitial oxygen lamp existing near the surface of the wafer 1. At the same time, inside the wafer, internal crystal defect nuclei that existed in the wafer formation state 11 (as-grown state) disappear or dissolve into solid solution.
There are a few internal crystal defects indicated by ○ in the figure.

CB) Next, internal crystal defect nuclei are shown schematically in a cross-sectional view of the same wafer (by performing heat treatment at a temperature of 700 to 800 degrees Celsius in an Nt atmosphere for 40 hours at S degrees, so-called low-temperature annealing). In the process of forming dense scales, interstitial oxygen inside the core is a factor in forming crystal defects.

(C) Further - also in a N atmosphere, at a temperature of 1
Heat treatment is performed at 050°C for about 20 hours.

By this heat treatment, the internal crystal defect nuclei formed by the heat treatment in FIG. 1 (as schematically shown in the sectional view of Q, CB) are made to grow into internal crystal defects having a gettering effect.

The above three-step heat treatment method [A), CB), and (C) requires high temperatures and long periods of time, so even if a sufficiently thick protective film is formed on the surface, polishing, etc. Surface treatment is required.

2. Accurate control of width is difficult and may cause wafer warpage or distortion.

(3,3) In order to solve the pre-IC problems of the stepwise heat treatment method explained in (3,2) above, and as a method for forming Z and internal crystal defects, the present inventor proposed the patent application No. 56-0350.
The continuous increasing temperature heat treatment method proposed by No. 24 will be explained.

This heat treatment method is composed of the following method (AI) [B] or [A)+(B)K.

[A,] For silicon wafers/SK with an interstitial oxygen concentration higher than 1.5×10”7m, heat treatment is performed at a temperature increase rate of 5 to 14° C./coat.

[A,] Interstitial oxygen concentration K is 1.5 x 10", /'
Kudzu・[For silicon wafers below 5℃/-
Heat treatment is performed at the following temperature increase rate.

(B) After the heat treatment of [A,] or [A,], 1
Heat treatment is performed at least once at 4° C./− and the following lifting speed l.

Figures 2 (a) to (c) are diagrams showing changes in the size versus density distribution of internal crystal defects or defect nuclei due to the present thermal zone evacuation method. In Figure 2, the vertical axis is the size of internal crystal defects or defect nuclei. , 111117 indicates the critical size that disappears at the start of heating heat treatment and the wrinkles disappear at the beginning of the heating process. , Ml indicates the critical size for annihilation of internal crystal defects at the highest temperature used in the semiconductor device manufacturing process, and the horizontal axis indicates the density of internal crystal defects or defect nuclei.

FIG. 2(a) shows the state before the start of cryo-heat treatment, that is, the 6-eno-formation state. In this state, there are internal crystal defects or defect nuclei of various sizes of MK in the wafer, but interstitial oxygen The larger the number, the larger the size and density of the distribution. However, the usual cz method (Czochritskim
ethod) In silicon wafers produced by VC, all -r crystal defects are smaller in size than the dashed line.

Figure 2 (bl Fi temperature increasing heat treatment [A,] Hiiha [At]
Shows the later state. In this state, most of the crystal defect nuclei grow into crystal defects, and the crystal defect size 20 distribution moves upward in the figure □, and some of them even exceed the critical size indicated by the broken line. Some crystal defect nuclei smaller than the critical size for the heating start temperature shown by the broken line IK, which existed in the wafer forming layer shown by the power tube 21W(a)K, disappear or dissolve into solid solution.

The density of internal crystal defects formed by this heating heat treatment is controlled by the interstitial oxygen concentration and the heating rate. That is, when the interstitial oxygen fI11 degrees is high or the temperature increase rate is low, the density of internal crystal defects becomes high.

On the other hand, when the width of D and Z is h'''CFi, the heating rate is low and the maximum temperature reached is low.

2. The width becomes thinner.

In order to obtain the required internal crystal defect density and Z width, it is necessary to select the combination of the above-mentioned dormitories, and in this temperature rising heat treatment method, method [A)] or [A,] is selected as described above. ing.

FIG. 2(e) shows the temperature increase heat treatment [A,] or [A,]
Next, the state after the above-mentioned temperature raising heat treatment CB) is performed one or more times - In this state, the formed internal crystal defects are completely removed.
It has become larger than the critical value for crystal defect annihilation at the maximum temperature used in his wafer process, shown by the broken line (■). 6. This temperature-raising heat treatment [B] is aimed at growing the size of internal crystal defects. zrtc twitter before VINIA heat treatment M heat section l) or iiha [As
), the temperature increase rate or the maximum temperature is set.

According to the above-mentioned results, the growth time of internal crystal defects required for the IG method has been shortened, and
It is possible to form a thin layer, Z, with good controllability to increase the efficiency of the simultaneous KIG effect. -).

(3,4) As revealed in (33), both the internal crystal defect density and the width of Z have a close correlation with the heating rate. Take density, Z
In order to satisfy both the width and controllability requirements,
In some cases, it may be preferable for the present inventor to apply the second son method as explained below in accordance with Japanese Patent Application No. 56-035023.

This heat treatment method is described below as method CA, ), ten (B).
Consists of K.

(A) A silicon wafer is subjected to heat treatment at a temperature of 950° C. or higher for 10 minutes or more.

CB) After the heat treatment in [A] above, heat treatment is performed at least once at a temperature increase rate of 14° C./- or less, especially for thin or Z
In order to obtain , at least the first heating rate lI
It is desirable that r be below 5°C/-mu.

The first heat treatment of the present method [A) F'i is performed to eliminate crystal defect nuclei near the surface of the sea urchin and out-diffusion of interstitial oxygen, which is a factor in the formation of defect nuclei.

Temperature-raising heat treatment (B: This is a method based on the same idea as the temperature-raising heat treatment in (3, 3) before l, but by pre-heating the heat treatment (A), the temperature increase rate can be slowed down. Even if crystal defects or defect nuclei are not formed up to the surface vicinity K related to the concentrating operation, it becomes possible to control the internal crystal defect density, Z, and @.

(35) The elevated temperature heat treatment method explained in (3, 3) and (34) above is the first (B) elevated temperature heat treatment, that is, [A,] or [At ) of (3, 3) or (3,4
) In (B), the density and width of the internal crystal defects, Z, are substantially determined, and the internal crystal defects are grown to a size exceeding a specific critical size by the second (B) and subsequent temperature-raising heat treatments. By tightening the wafer, it imparts a mechanical effect to the wafer.

However, in the semiconductor device fabrication process, the wafer is usually further subjected to several high-temperature heat treatments.

The high-temperature heat treatment during the manufacturing process of these conductors has the effect of growing internal crystal defects, similar to the effect of (3,2) (C) above. If the shredded wafer has internal crystal defects that have already grown, the resulting stress may cause damage during high-temperature heat treatment during the semiconductor device manufacturing process.
Dislocations (called slip lines) occur on the wafer,
This may adversely affect the characteristics or lifespan of the formed semiconductor device.

Therefore, in order to provide the necessary and sufficient IQ effect, and to eliminate the occurrence of slits and lines that can cause problems in the formed semiconductor device, we have set the targets for K, slits, Z, and internal crystal defects during the completion of the semiconductor device. In order to achieve this state during the semiconductor device manufacturing process, it is necessary to form the state of internal crystal defects or defect nuclei in advance in the wafer pretreatment process, taking into consideration the influence of heat treatment during the semiconductor device manufacturing process.

(3, 6) It is an object of the present invention to obtain a wafer pretreatment method that eliminates Z and internal crystal defects when a semiconductor device is completed.

The object of the present invention is to prepare silicon sea urchin/1 at 5°C.
/-, achieved by performing pre-heat treatment including heat treatment to a maximum temperature of 950°C or less at the following temperature increase rate,
The heat treatment time, etc. (a) Wafer pretreatment process l! Effects of heat treatment on bales during the semiconductor device manufacturing process.

Can) interstitial oxygen in silicon wafers! Initial value of 11jjL.

(cl The amount of decrease in interstitial oxygen #If during wafer pretreatment and semiconductor device manufacturing process that gives the optimal value of the dense layer and size of internal crystal defects after semiconductor device completion [Initial value of interstitial oxygen concentration and semiconductor device completion difference with the latter value].

(37) Prior to the example, the third
An example of experimental results will be described with reference to FIGS. 5 to 5.

Figure 3 is a diagram showing an example of an experimental result of pre-wafer heat treatment for internal crystal defects or defect nucleation.
Place at ℃ for 4 hours.

[B] Maximum temperature reached 1fT at a heating rate of 2℃/-.
C1 increases temperature 1j.

(C) Maximum temperature reached T″cK3 hour tube.

Continue to implement. Initial lattice barrier element concentration [01] 1
．． A MO8FET was formed after performing the preheat treatment shown in FIG. 3 on a wafer of 8 X I O"/-, and the interstitial oxygen concentration was measured after the wafer preheat treatment and after the completion of the MO8FET. The results are shown in FIG. In the figure, the horizontal axis shows the maximum temperature II'T (°C), and the vertical axis shows the amount of decrease Δ[01) (xtosma/ed) in the interstitial oxygen concentration from the initial value.
After the wafer pretreatment shown in IA diagram 3, the song 11BFiMO8F
Shown after ET is completed.

When the cumulative total of semiconductor device manufacturing heat treatment steps is relatively long as in this experimental example, the amount of decrease in interstitial oxygen concentration Δ[01] after the semiconductor device is completed is determined by the wafer preheat treatment as shown by curve B in Figure 4. When the maximum temperature T is in the high temperature range of 1000℃ or 1100℃, and in the low temperature range especially 900℃
8! There is almost no difference between the two cases.

On the other hand, regarding Δ[01) after the wafer pre-heat treatment, if the maximum temperature T of the wafer pre-treatment is in the low temperature range with the boundary around 950°C as in the curve 1mA in Figure 4, it is in the high temperature range. It is extremely small compared to the case. The amount of decrease Δ[0 amount] in the interstitial oxygen concentration is caused by the oxygen moving to the crystal defect portion, and means the growth of internal crystal defects.

FIGS. 5(&) to (e)K illustrate changes in the size versus density distribution of internal crystal defects or defect nuclei in this experimental example. However, when the maximum temperature 1fT is in the above-mentioned low temperature range, it is shown by a solid line, and when it is in a high temperature range, it is shown by a broken line. After completing step (C) above, (dl indicates an example of the semiconductor device manufacturing process, and (el indicates the state after the semiconductor device is completed).

Furthermore, each i! below is parallel to the horizontal axis in the figure. shows the annihilation critical size of internal crystal defects or defect nuclei with respect to the degree of
The IFi wafer pretreatment starting temperature 1[,l corresponds to the first heat treatment temperature in the semiconductor device manufacturing process.

By performing the heat treatment (A) on the wafer that was initially in a state of failure as shown in FIG. 5(a), defective nuclei are formed as shown in FIG. 5(a). j! Then, defect nuclei grow due to the temperature-raising heat treatment (B)c, and exceed a critical size after the constant-temperature heat treatment (C) is completed.

If the highest attained ii degree is at a low temperature, [B]
] by! Even after that, it is still in the stage of a defective nucleus,
The decrease in interstitial oxygen is slight. On the other hand, when the highest temperature fT reaches a high temperature, the defect nucleus breaks out and grows to the defect K, resulting in a large decrease in interstitial oxygen.

For wafers whose maximum temperature fT during pre-wafer heat treatment remains at a low temperature, the maximum temperature fT reached during the semiconductor device manufacturing process is
By heat treatment at a temperature fK exceeding fT, defect nuclei gradually grow and reach the stage of defects, and the interstitial oxygen concentration decreases.

On the other hand, the internal crystal defects formed at the maximum during the pre-wafer heat treatment do not grow much, and the decrease in interstitial oxygen 1111& during this period is slight.

When the cumulative heat treatment process for semiconductor device manufacturing is long, as in this experimental example, after the semiconductor device is completed, internal crystal defects are sufficiently removed by eIG even in wafers where the maximum temperature lT of the pre-wafer heat treatment remains at a low temperature. grow until it becomes effective. On the other hand, for wafers that have been subjected to pre-wafer heat treatment to a high degree of completion, there is a high risk of the failure described in (35).

(38) The present invention will be specifically explained below using examples with reference to the drawings.

FIG. 6 shows the relationship between time and temperature for an embodiment of the invention.

(A) A silicon wafer is heated to a temperature of, for example, 1100°C
Heat treatment is performed for 0 minutes.

This high-temperature heat treatment allows the surface of the wafer to Nearby defect nuclei disappear or dissolve into solid solution.

At the same time, interstitial oxygen, which is a factor in the formation of defect nuclei existing near the surface, is out-engineered.

Here, unless the nuclear heat treatment temperature is 950° C. or higher, it is difficult to sufficiently clean the vicinity of the wafer surface. Additionally, setting the temperature to 1,300°C or higher is undesirable because the effect of heat on the wafer will be excessive.The heat treatment time must be at least 10 minutes to obtain the full effect of the heat treatment, and it takes about 60 minutes and more. It is enough if you do it.

Furthermore, in order to preserve the wafer surface, it is desirable to start the heat treatment after forming a protective film such as silicon diilide (SiOr) on the surface. It is also possible to form a Sin film on the wafer surface.

After the N3 heat treatment of the previous process [A], as shown by a in FIG. 6, the temperature-lowering treatment in which the temperature is once lowered to, for example, 650°C VC does not have a large effect on the effects of the present invention. Therefore, there is no problem even if the wafer is removed from the furnace and cooled.

Next, constant temperature heat treatment which is a feature of the present invention CB) and elevated temperature heat treatment [C].

[B] The silicon wafer is subjected to constant-temperature heat treatment at, for example, a temperature of 650° C. for a time determined by a method to be described later.

(C) Temperature increase rate for silicon wafer, e.g. 2C/a
-1, heat treatment is performed to raise the temperature to a maximum temperature of, for example, 900°C.

1. Determine the heat treatment time with reference to FIG. 7. In FIG.
) and the time tC of the heat treatment [C], which is the total time t.

After completion of the semiconductor device, the amount of decrease in interstitial oxygen degree that gives the optimum value for the density and size of internal crystal defects Δ[O1] Δ(Of) = (Of) o (O1] f However, (Ol
)o: The initial value of the lattice oxygen concentration r [01)f An example of the value of the interstitial oxygen concentration after the semiconductor device is completed is 1.1.1
Take 5XIO'''/cli and 0.2X10''/j,
Converting the effect of heat treatment during the semiconductor device manufacturing process
911! f and time 1050℃, 1 hour 7? - solid line, 1
The dashed line indicates 2 hours at 050°C, and the broken line indicates 3 hours at 1050°C.

Now, the initial value [0I)o of the interstitial oxygen concentration of a given wafer is 1.7X10'·/-,
The optimal value for the amount of decrease in interstitial oxygen concentration is 0.75X 10”
/afT4? , when the converted value of the heat treatment during the semiconductor device manufacturing process is 1050°C and 1 hour, t=
You will get 5 hours and 40 minutes.

However, the time tc of the temperature raising heat treatment [C] is t = (900-65'O) ÷ 2; 2 hours and 5 minutes in this example, so the time tc of the constant temperature heat treatment (PCB) is BIi t B = The optimum value is t t c = 3 hours and 35 minutes.

Constant-temperature heat treatment (CB) and later corresponds to the case where the highest attainment 11& of the experimental example mentioned in K (3, 7) is completed at a low temperature of 950°C or less, and as mentioned above, constant-temperature heat treatment (:B) K
Therefore, the defective nucleus has the shape a! Constant temperature heat treatment [B) Vc
The temperature at which the above effects can be obtained is from 7,550℃ to 7,550℃.
Approximately 50°C is appropriate.

Temperature increasing heat treatment (C) is ヂWFfl'蛯もy constant temperature heat treatment rB
), the main objective is to increase the size of the defect nuclei that are formed, but at the same time, the defect nucleus density g is also increased, and this increase in the defect nucleus density is achieved by increasing the heating rate by 5℃/- , it is noticeable when you are at the bottom of the mountain. As mentioned above, constant temperature heat treatment [B] was performed by selecting tC=t for the time tK determined from FIG.
Even if omitted, defect nuclei with the same density and size are formed.

In order to sufficiently increase the density of internal crystal defect nuclei, the valve speed of the heating heating section IF (C) is set to 5°C/- or less as described above, and in order to prevent the excessive size of defect nuclei from growing. As mentioned above, the maximum temperature reached is 950°C or less, and this condition will be explained later and is also suitable for controlling the width of Z. The size of the semiconductor device fI# manufacturing process, especially the first hot part f
! If the growth has not exceeded the critical size at 1 temperature, the above-mentioned temperature raising heat treatment [C] is followed by foot warming heat treatment [D].
It is necessary to carry out

[D] Place the silicon wafer at the maximum temperature of [C] for, for example, 3 hours.

This constant-temperature heat treatment [D] is performed as necessary, and the time is determined according to the semiconductor device manufacturing process.

This concludes the Ueno preheat treatment according to the present invention for forming the density and size of internal crystal defects or defect nuclei.

On the other hand, before’D, Z by heat treatment.

is also formed. The factors that determine the width of D and Z are:
There are the temperature and time of the constant temperature heat treatment (A) and CB), and the temperature increase rate and maximum temperature of the layer temperature heat treatment [C], and the temperature of CA] and the maximum temperature of [C] are high;
When the time of A] is long and the temperature increase rate of (C') is fast,
Z.

becomes wider.

For the example described above, the constant temperature heat treatment [ARK] was used to obtain widths of D, Z, of about 10-m.

As a result of manufacturing a semiconductor device as planned using the silicon wafer of this example, it was confirmed that it had a sufficient IC effect and that problems caused by the generation of slip lines were eliminated.

(3, 9) As is clear from the examples above, the wafer pre-heat treatment according to the present invention can be carried out by adjusting the initial value of the wafer's lattice temperature, the height of the heat treatment temperature in the semiconductor device manufacturing process, and the time required for the wafer. The long and short of TI! This makes it possible to process a semiconductor device completed in 2008 using a unified method regardless of the magnitude of the IC effect required.

(3,10) The original 8AFf, As explained above,
At a rising m' rate of 5°C/- or less relative to the silicon wafer,
Shark high luck i! By performing preheat treatment including heat treatment at a temperature of 950 degrees Celsius or less, a sufficient IC effect can be obtained after the completion of the semiconductor device, and the occurrence of failures due to excessive growth of internal crystal defects can be eliminated, Semiconductor iMfIt
It has a great effect on improving the characteristics of the system and eliminating obstacles.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are schematic cross-sectional views of a sea urchin showing Z and internal crystal defect growth according to the prior art, and FIG.
at to (c) are diagrams showing the growth of internal crystal defect size and density according to the prior art, Figure 3 is a diagram showing the relationship between temperature and time in the experimental example, and Figure 4 is the interstitial fiber in the experimental example. Figure 5 is a diagram showing the amount of decrease in concentration; Figure 5 is a diagram showing the growth of internal crystal defect size and density in the Fi test example; Figure 6 is a diagram showing the relationship between temperature l and time in the example of the present invention; The figure is an example of a chart for determining heat treatment time. Figure 1 Figure 2 ((2) (b) (C) Figure 3
Figure 4 Figure 5 Figure 5

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, which comprises performing heat treatment on a silicon substrate at a temperature increase rate of 5°C/- or less and a maximum source R of 950°C or less.