JP6945805B2 - Manufacturing method of epitaxial wafer - Google Patents

Description

The present invention relates to a method for manufacturing an epitaxial wafer.

Epitaxial wafers are used as substrates for semiconductor elements used in power supply circuits and the like used in mobile terminals and AC adapters. In such semiconductor devices, it is required to reduce the substrate resistance as much as possible for the purpose of lowering the on-resistance from the demand for power saving. Another method of reducing the on-resistance is to thin the semiconductor device substrate, but there is a limit to thinning the semiconductor device substrate due to the characteristics of the semiconductor device device. Therefore, an epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with a high concentration of dopant, and an epitaxial wafer using the low resistivity substrate as a semiconductor element substrate is manufactured. As such an epitaxial wafer, Patent Documents 1 to 5 disclose an epitaxial wafer in which an epitaxial layer is grown on a low resistivity substrate.

The silicon single crystal substrate that is the basis of such an epitaxial wafer is manufactured based on an ingot that is doped with a high-concentration dopant and pulled up. However, if an n-type dopant such as Sb (antimony) or As (arsenic) is used as this dopant, the doped dopant will evaporate during pulling. Therefore, if the silicon single crystal substrate on which the epitaxial layer is grown is an n-type, a silicon single crystal substrate doped with phosphorus (red phosphorus) having a relatively low volatility as a dopant is used. Then, an epitaxial wafer having a low resistivity is manufactured by vapor-depositing an epitaxial layer on the main surface of the prepared silicon single crystal substrate.

However, when the epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with phosphorus at a high concentration, many stacking defects (stacking faults) occur on the main surface of the epitaxial wafer after the vapor phase growth. When a semiconductor element is manufactured using an epitaxial wafer in which this stacking defect is generated, the characteristics (mainly withstand voltage characteristics) of the semiconductor element (device) are deteriorated. Therefore, it is necessary to reduce the number of stacking defects generated to a level that does not affect the characteristics of the device.

Regarding the reduction of stacking defects of phosphorus-doped epitaxial wafers, for example, Patent Document 1 states that the main surface of a silicon single crystal substrate is vapor-phase etched with hydrogen chloride gas before epitaxial growth, and then at a temperature of 1100 ° C. or higher. It is described that the lamination defect can be reduced by performing the heat treatment for a time exceeding 30 seconds and within 5 minutes.

Further, in Patent Document 2, stacking defects are reduced by performing epitaxial growth on a phosphorus-doped silicon single crystal substrate under conditions of a temperature of 1040 ° C. or higher and 1130 ° C. or lower and a growth rate of 2 μm / min or lower. It is stated that it can be done.

JP-A-2017-5049 Japanese Unexamined Patent Publication No. 2017-195273 Japanese Unexamined Patent Publication No. 2012-156303 Japanese Unexamined Patent Publication No. 2014-82242 Japanese Unexamined Patent Publication No. 2005-79134

As described above, Patent Documents 1 and 2 disclose a method for reducing stacking defects when a phosphorus-doped silicon single crystal substrate is used. However, in order to further reduce stacking defects, Patent Documents 1 and 2. Apart from the methods 1 and 2, it is useful to provide a method capable of reducing stacking defects.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce stacking defects generated in an epitaxial wafer in a method of growing an epitaxial layer on a phosphorus-doped silicon single crystal substrate.

The stacking defects observed on the main surface of the epitaxial wafer are crystal defects generated on the low resistance substrate, and as a result of research and investigation, the surface layer and bulk of the silicon single crystal substrate are supersaturated with dissolved phosphorus. It became clear that a large number of phosphorus precipitates were generated.

Therefore, it is considered that the mechanism is that the deposition defects are observed by propagating the phosphorus precipitates existing near the surface layer to the main surface of the epitaxial wafer as the starting point. This stacking defect tends to increase as the resistivity of the silicon single crystal substrate decreases. It is considered that this is because more dopants are incorporated in the crystal in an inert state in the crystal aiming at lower resistivity, and precipitates appear in the final cooling process in the silicon crystal pulling process.

For the purpose of reducing phosphorus precipitates on the main surface of a silicon single crystal substrate, even if the outermost surface is modified and heat-treated, for example, by RTA (Rapid Thermal Anneal) treatment, vapor phase etching is performed after that. The qualified surface is removed and the precipitates present in the bulk are exposed to the surface.

The present inventor has found a condition capable of effectively reducing phosphorus precipitates generated on a silicon single crystal substrate, and completed the present invention.

That is, the present invention
A preparatory step to prepare a phosphorus-doped silicon single crystal substrate,
A heat treatment step of performing a heat treatment of maintaining the silicon single crystal substrate at an isothermal temperature of 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer.
A growth step of growing an epitaxial layer on the main surface of the silicon single crystal substrate after the heat treatment,
It is characterized by having.

As described above, by performing the heat treatment for maintaining the isothermal temperature at 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer before the epitaxial growth, the phosphorus precipitates generated on the main surface and bulk of the silicon single crystal substrate are eliminated or reduced. It is possible to reduce stacking defects starting from this precipitate.

Further, even if the heat treatment is performed at a temperature of 700 ° C. or higher and lower than 1050 ° C. at an isothermal temperature for 30 seconds or longer, if a cooling process is included after that, new phosphorus precipitates may appear.

Therefore, when shifting from the heat treatment step to the growth step, it is preferable to maintain or raise the temperature of the silicon single crystal substrate at an isothermal temperature. Further, it is preferable that after the silicon single crystal substrate is put into the reaction furnace, the process proceeds to the growth step without lowering the temperature of the silicon single crystal substrate. According to this, since the cooling process is not included, the appearance of new phosphorus precipitates can be suppressed, and by extension, the stacking defects starting from the phosphorus precipitates can be reduced.

Further, the heat treatment step includes an etching step of vapor-phase etching with hydrogen chloride gas while heating the main surface of the silicon single crystal substrate, and a post-etching heat treatment step of heat-treating the silicon single crystal substrate after vapor phase etching. With
In the post-etching heat treatment step, the temperature is maintained at an isothermal temperature of 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer.

In this way, by performing the etching process with hydrogen chloride gas as a part of the heat treatment process, the main surface of the silicon single crystal substrate can be cleaned, and the generation of defects other than phosphorus precipitates (for example, minute pits) can be further suppressed. can. Further, when the etching step is performed, the outermost surface of the substrate is removed, and as a result, phosphorus precipitates existing in the bulk of the substrate may be exposed on the surface. However, after the etching step and before the growth step, the temperature is 700 ° C. By performing a heat treatment that keeps the temperature equal to or higher than 1050 ° C. for 30 seconds or longer, the phosphorus precipitates existing on the main surface after the etching step can be eliminated or reduced. As a result, stacking defects can be further reduced.

The temperature of the etching step can be 700 ° C. or higher and lower than 1050 ° C. According to this, the phosphorus precipitate existing on the substrate can be eliminated or reduced while etching the surface of the substrate with hydrogen chloride gas.

Further, the heat treatment step includes a pre-etching heat treatment step of heat-treating the silicon single crystal substrate before vapor phase etching, and the temperature of the pre-etching heat treatment step is 700 ° C. or higher and lower than 1050 ° C. Can be done.

According to this, by carrying out the pre-etching heat treatment step at a temperature of 700 ° C. or higher and lower than 1050 ° C., the phosphorus precipitate existing on the substrate can be eliminated or reduced while removing the natural oxide film on the substrate surface.

Further, the heat treatment step includes an etching step of vapor-phase etching with hydrogen chloride gas while heating the main surface of the silicon single crystal substrate, and a pre-etching heat treatment step of heat-treating the silicon single crystal substrate before the vapor phase etching. And a post-etching heat treatment step of heat-treating the silicon single crystal substrate after the vapor phase etching.
The temperature of the pre-etching heat treatment step, the temperature of the etching step, and the temperature of the post-etching heat treatment step can be the same temperature, and can be 700 ° C. or higher and lower than 1050 ° C.

As described above, by carrying out a series of heat treatments including the pre-etching heat treatment step, the etching step and the post-etching heat treatment step at the same temperature and at a temperature of 700 ° C. or higher and lower than 1050 ° C., the cooling process is performed during this heat treatment. It can be avoided from being contained, the generation of new phosphorus precipitates due to the cooling process can be suppressed, and the existing phosphorus precipitates can be eliminated or reduced. Further, by carrying out a series of heat treatments at the same temperature, it becomes easy to control the temperature of each step.

Further, in the preparation step, a silicon single crystal substrate doped with ^{phosphorus of 5 × 10 19} atоms / cm ^{3 or more is prepared.} In this way, in a low resistivity substrate doped with a high concentration of phosphorus, phosphorus precipitates, which are the starting points of stacking defects, are likely to be generated, but before epitaxial growth, the temperature is isothermal at 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer. By carrying out the heat treatment for holding, the generation of phosphorus precipitates can be reduced. That is, when the present invention is applied to a low resistivity substrate, stacking defects of an epitaxial wafer can be effectively reduced.

Further, in the heat treatment step, it is preferable to maintain an isothermal temperature of 750 ° C. or higher and 850 ° C. or lower. By setting this temperature condition, the effect of reducing stacking defects becomes remarkable.

Further, the growth step includes a first growth step and a second growth step in which the growth rate is higher than that of the first growth step following the first growth step, and the first growth. In the process, the growth rate is gradually increased.

As shown in Patent Document 2, when the rate of epitaxial growth is slowed down, the occurrence of stacking defects tends to be suppressed. In the present invention, in the growth step, the first growth step and the second growth step in which the growth rate is higher than that of the first growth step are carried out following the first growth step, so that the second growth The occurrence of stacking defects can be suppressed as compared with the case where epitaxial growth is performed only in the process, and the epitaxial layer having a desired film thickness can be grown in a shorter time than in the case where epitaxial growth is performed only in the first growth step. Further, since the growth rate is gradually increased in the first growth step, the suppression of stacking defects, which is an effect of the low growth rate, and the improvement of productivity, which is the effect of the high growth rate, are achieved. It is possible to achieve both. In this way, it is possible to obtain an epitaxial wafer in which the occurrence of stacking defects is suppressed while suppressing the decrease in productivity.

Further, the first film thickness, which is the film thickness of the epitaxial layer to be grown in the first growth step, is preferably smaller than the second film thickness, which is the film thickness of the epitaxial layer to be grown in the second growth step. .. At this time, the first film thickness can be 5 to 10% of the total film thickness of the first film thickness and the second film thickness combined. As a result, it is possible to further suppress the decrease in productivity while suppressing the occurrence of stacking defects.

It is a figure which showed the image of the defect (phosphorus precipitate) existing in the silicon single crystal substrate where phosphorus was doped with high concentration. It is a figure which showed the image of the defect (phosphorus precipitate) existing in the silicon single crystal substrate where phosphorus was doped with high concentration, and is the figure which showed the defect image different from the defect of FIG. It is a figure which observed the change of the phosphorus precipitate at the time of heat treatment by the in-situ observation by TEM, and showed how the phosphorus precipitate disappeared at the time of temperature rise. It is a schematic diagram of a single-wafer type vapor deposition apparatus. It is a flowchart exemplifying the manufacturing process of a silicon epitaxial wafer. It is a figure which illustrated the temperature profile in each process of FIG. It is a figure which compared the number of stacking defects of an epitaxial wafer in an Example and a comparative example.

First, the morphology of defects existing on the substrate before epitaxial growth and the composition thereof will be described. 1 and 2 show images of defects present in a silicon single crystal substrate heavily doped with phosphorus. The four defect images in FIG. 1 show images for the same defect. Specifically, the defect image on the upper left is a BF (Bright Field) image of a TEM (Transmission Energy Microscope). The remaining image shows an element image map obtained by EDX (Energy Dispersive X-ray Microscope, Energy Dispersive X-ray Analysis). As the element image map, the map of the P (phosphorus) image is shown in the upper right, the map of the O (oxygen) image is shown in the lower left, and the map of the Si (silicon) image is shown in the lower right. FIG. 2 shows a BF image (upper left image) for a defect generated at a position different from that of FIG. 1, an EDX map of a P (phosphorus) image (upper right image), and an EDX map of an O (oxygen) image (lower left). The EDX map (lower right image) of the Si (silicon) image is shown.

As shown in FIGS. 1 and 2, phosphorus is detected at a high concentration on the EDX map in the blackest contrast portion in the BF image. In addition, the EDX map of silicon shows the contrast indicating silicon. On the other hand, the EDX map of oxygen does not show a clear contrast, that is, the oxygen concentration is low in the defects of FIGS. 1 and 2. From the above, it can be inferred that these defects are SiP composed of phosphorus and silicon that do not contain oxygen.

FIG. 3 shows how the defects (phosphorus precipitates) shown in FIGS. 1 and 2 are heated, changes in the phosphorus precipitates are observed by in-situ observation by TEM, and disappear when the temperature rises. Explaining the procedure of the experiment of FIG. 3, the silicon single crystal substrate before epitaxial growth is thinned (0.1 μm) and then inserted into the TEM apparatus. The holder used for insertion into the TEM device is a holder that can be heated up to 1200 ° C. Then, the thinned sample inserted into the TEM device was heat-treated with the temperature profile shown in the lower part of FIG.

The upper part of FIG. 3 shows a TEM observation image of the sample at each time point of the temperature profile shown in the lower part of FIG. Specifically, the leftmost image shows an observation image at room temperature a before heating to 700 ° C. The second image from the left shows the observation image at time point b immediately after the sample is heated to 700 ° C. and reaches 700 ° C. The third image from the left shows the observation image at the time point c when the sample was held at 700 ° C. for 60 minutes at an isothermal temperature. The fourth image from the left shows the observation image at time point d after cooling the sample to room temperature after time point c. All observation positions are corrected in a timely manner by in-situ observation, and the observed and recorded images have almost the same field of view.

In the observation image before heating, a large number of black spots showing defects (phosphorus precipitates) appear. On the other hand, in the observation image immediately after reaching 700 ° C. and the observation image after maintaining the isothermal temperature at 700 ° C. for 60 minutes, it can be seen that the defects (black spots) disappear or shrink. Further, in the observation image obtained through the cooling process after heating, it was confirmed that the defect reappears at the same position or a new defect appears at another position (for example, the position of reference numeral 100). It is considered that this phenomenon appeared as a precipitate of phosphorus that could not be dissolved due to the difference in solid solubility between high temperature and low temperature.

In the present embodiment, the epitaxial wafer is manufactured based on the findings of FIGS. 1 to 3. First, the configuration of the vapor phase growth apparatus used for manufacturing the epitaxial wafer will be described with reference to FIG. In the vapor phase growth apparatus 1 of FIG. 4, the silicon single crystal substrates W are charged one by one, and the epitaxial layer of the silicon single crystal is vapor-deposited on the main surface of the charged silicon single crystal substrate W. It is configured as a single-leaf vapor phase growth device. Specifically, the vapor phase growth apparatus 1 is a susceptor that horizontally supports the reaction furnace 2 into which the silicon single crystal substrate W to be processed is charged and the silicon single crystal substrate W arranged in the reaction furnace 2 and charged. 3, a heating unit 6 arranged so as to surround the reaction furnace 2 and heating the inside of the reaction furnace 2, and a temperature measuring unit 7 for measuring the temperature of the silicon single crystal substrate W arranged in the reaction furnace 2 are included. Consists of. The susceptor 3 supports the substrate W from the back surface side thereof. Further, the susceptor 3 is provided so as to be rotatable around its central axis.

On one end side of the reaction furnace 2, a gas supply port 4 for supplying various gases is formed on the main surface of the silicon single crystal substrate W in the reaction furnace 2. The gas supplied from the gas supply port 4 is a silicon source, an etching gas (chlorine-based gas such as hydrogen chloride gas), a carrier gas (for example, hydrogen), a dopant gas for adjusting the conductivity type and conductivity of the epitaxial layer, and the like. Is.

Further, on the side of the reactor 2 opposite to the gas supply port 4, a gas discharge port 5 for discharging the gas that has passed on the main surface of the silicon single crystal substrate W is formed. The heating unit 6 may be, for example, halogen lamps provided above and below the reaction furnace 2. The temperature measuring unit 7 can be, for example, a pyrometer (radiation thermometer) that measures the surface temperature of the silicon single crystal substrate W in a non-contact manner with the silicon single crystal substrate W.

Next, a method of manufacturing a silicon epitaxial wafer using the vapor phase growth apparatus 1 will be described. First, a silicon single crystal substrate W as a growth substrate for growing the epitaxial layer is prepared (S1 in FIG. 5). For example, a silicon single crystal ingot is produced by immersing a seed crystal silicon rod in the liquid surface of a molten liquid obtained by putting polycrystalline silicon and phosphorus for adjusting the resistance into a quartz crucible and pulling it up. Next, the produced silicon single crystal ingot is cut out to a predetermined thickness, and the cut out wafer is roughly polished, etched, polished, or the like to produce a silicon single crystal substrate. To this silicon single crystal substrate, for example, 5 × 10 ¹⁹ atоms / cm ³ or more or 8 × 10 ¹⁹ atоms / cm ³ or more is added as a dopant when the silicon single crystal ingot is produced. The resistivity of the prepared silicon single crystal substrate W is, for example, 1.2 mΩ · cm or less. The silicon single crystal ingot is not limited to the CZ method, and other methods such as the FZ method may be adopted.

The prepared substrate W is washed in advance to make the surface clean enough, and then transported to the susceptor 3 in the reactor 2, and a series of steps of S2 and the following in FIG. 5 are performed. Specifically, first, as a baking step, the substrate W is heat-treated by flowing hydrogen gas into the reaction furnace 2 and heating the substrate W to a predetermined temperature by the heating unit 6 (S2). The power supply of the heating unit 6 is controlled by the thermometer side unit 7 so that the surface temperature of the substrate W becomes a predetermined temperature. By this baking step, the natural oxide film on the surface of the substrate W is removed. The baking step includes a step of raising the temperature to a predetermined temperature and a step of holding the temperature at the temperature after the temperature rise for a predetermined time. As shown in FIG. 6, the temperature after the temperature rise in the baking step is, for example, the same temperature as the subsequent heat treatment step (etching step, purging step, isothermal holding step), and is set to a temperature of 700 ° C. or higher and lower than 1050 ° C. The temperature can be preferably 750 ° C. or higher and 850 or lower. In the example of FIG. 6, the heat treatment temperature is 750 ° C.

Next, an etching step of performing vapor phase etching on the substrate W is performed (S3). In the etching step, the main surface of the substrate W is vapor-phase etched by supplying hydrogen chloride gas (HCl gas) onto the main surface of the substrate W while heating the substrate W to a predetermined temperature. In addition to hydrogen chloride gas, hydrogen gas is also supplied to the reaction furnace 2 during the etching step. Further, the supply time and supply amount of hydrogen chloride gas are set so that the etching amount is 0.025 μm or more and 1.000 μm or less. Stacking defect nuclei such as phosphorus precipitates (those that cause stacking defects existing in a silicon single crystal substrate) are in a region of 0.025 μm or more in the depth direction (thickness direction) of the substrate W from the main surface of the substrate W. Since it is localized in, stacking defects can be effectively suppressed when the etching amount is 0.025 μm or more. On the other hand, if the etching amount exceeds 1.000 μm, the productivity of the epitaxial wafer decreases. From the above, the etching amount is preferably set in the range of 0.025 μm or more and 1.000 μm or less. The etching rate is set to be, for example, 0.04 μm / min or more and 0.37 μm / min or less.

Further, in the etching step, as shown in FIG. 6, for example, the temperature of the baking step is maintained. Further, the temperature of the etching step can be the same temperature as that of the subsequent heat treatment step (purge step, isothermal holding step), and specifically, the temperature can be 700 ° C. or higher and lower than 1050 ° C. The temperature can be preferably 750 ° C. or higher and 850 or lower.

When the etching step is completed, a purging step of discharging the hydrogen chloride gas in the reaction furnace 2 to the outside of the reaction furnace is performed (S4). In the purging step, while maintaining the temperature of the etching step, the supply of hydrogen chloride gas to the reactor 2 is stopped, and only hydrogen gas is supplied.

Next, in order to eliminate or reduce the stacking defect nuclei such as phosphorus precipitates present on the main surface and bulk of the substrate W after vapor phase etching, the temperature of the substrate W is 700 ° C. or higher and lower than 1050 ° C. (preferably). An isothermal holding step of maintaining an isothermal temperature for 30 seconds to 450 seconds or more at a temperature of 750 ° C. or higher and 850 ° C. or lower is performed (S5). This isothermal holding step is a heat treatment step for the purpose of reducing phosphorus precipitates. In the example of FIG. 6, the temperature of the isothermal holding step is the same as the temperature of the purging step. Further, in the isothermal holding step, for example, hydrogen gas can be supplied into the reaction furnace 2 and the flow rate of the hydrogen gas can be the same as the flow rate of the purging step. When the heat treatment temperature is the same in the purge step and the isothermal holding step as in the example of FIG. 6, the purging step and the isothermal holding step are regarded as one heat treatment step, and the condition of the heat treatment step is set to 700 ° C. The conditions are such that the temperature is maintained at the same temperature for 30 seconds to 450 seconds or more at a temperature equal to or higher than 1050 ° C. (preferably a temperature of 750 ° C. or higher and 850 ° C. or lower). The time of the isothermal holding step is preferably long when the temperature of the isothermal holding step is low, and may be short when the temperature is high, but is at least 30 seconds or more.

Next, a growth step of vapor-depositing an epitaxial layer of silicon single crystal on the main surface of the substrate W is performed (S6). In the growth step, for example, trichlorosilane (TCS) as a raw material gas and hydrogen gas as a carrier gas for diluting the trichlorosilane are supplied into the reaction furnace 2. Further, the temperature inside the reactor 2 (substrate W) is controlled to, for example, a temperature of 1040 ° C. or higher and 1200 ° C. or lower. Conditions such as temperature, gas (raw material gas, carrier gas) flow rate, and growth time are set so that the growth rate and film thickness of the epitaxial layer become predetermined values.

Further, in the growth step, in order to suppress stacking defects and achieve both productivity of the epitaxial wafer, as shown in FIGS. 5 and 6, growth is performed in the first growth step (S7) in which the growth rate is slow. It is preferable to carry out the second growth step (S8) in which the speed is increased. In the first growth step, for example, conditions (temperature, gas flow rate) related to the growth rate are controlled so that the growth rate increases linearly with the passage of time. In the example of FIG. 6, as the first growth step, an example is shown in which the temperature of the substrate W is linearly increased with the passage of time so that the growth rate is linearly increased with the passage of time. In FIG. 6, the temperature is changed from 750 ° C. to 1150 ° C. at a constant rate of temperature rise. The flow rate of the raw material gas may be constant, or may be linearly increased with the passage of time as in the case of temperature. As the first growth step, conditions (temperature, gas flow rate) related to the growth rate may be controlled so that the growth rate becomes a constant value that does not change with the passage of time. Even in this case, the growth rate (constant value) of the first growth step is made smaller than the growth rate of the second growth step.

On the other hand, in the second growth step, the conditions (temperature, gas flow rate) related to the growth rate are controlled so that the growth rate is faster than the growth rate in the first growth step (for example, 3 μm / min or more). .. In the second growth step of FIG. 6, epitaxial growth is carried out at a constant growth rate by maintaining the conditions (temperature and gas flow rate) at the end of the first growth step.

Further, when the film thickness of the epitaxial layer grown in the first growth step is the first film thickness and the film thickness of the epitaxial layer grown in the second growth step is the second film thickness, for example, the first film thickness is the first film thickness. 2 The value can be smaller than the film thickness. Further, the first film thickness can be, for example, 5 to 10% of the total film thickness of the total of the first film thickness and the second film thickness. According to this, the ratio of the low growth rate to the entire growth process can be reduced, and as a result, the decrease in the productivity of the epitaxial wafer can be suppressed. Further, by ensuring that the first film thickness is at least 5% of the total film thickness, it is possible to suppress stacking defects that appear in the epitaxial layer. The resistivity of the epitaxial layer to be grown in the growth step may be a low resistivity as in the substrate W or a higher resistivity than the substrate W.

Then, after the temperature in the reactor 2 is lowered at a constant speed, the manufactured epitaxial wafer is taken out from the reactor 2. The steps S2 to S5 in FIG. 5 correspond to the heat treatment steps of the present invention. The step S1 corresponds to the preparatory step of the present invention. The step S2 corresponds to the pre-etching heat treatment step of the present invention. The step S3 corresponds to the etching step of the present invention. The steps S4 and S5 correspond to the post-etching heat treatment step of the present invention. The step S6 corresponds to the growth step of the present invention.

As described above, in the present embodiment, since the gas phase etching with hydrogen chloride gas is performed before the epitaxial growth, it is possible to remove the laminated defect nuclei such as phosphorus precipitates existing on the main surface of the silicon single crystal substrate. Further, immediately before the epitaxial growth (after the vapor phase etching and before the epitaxial growth), an isothermal holding step of maintaining the isothermal temperature at a temperature of 700 ° C. or higher and lower than 1050 ° C. (750 ° C. in the example of FIG. 6) for 30 seconds to 450 seconds or more is carried out. Therefore, phosphorus precipitates existing on the main surface and bulk of the silicon single crystal substrate after vapor phase etching can be eliminated or reduced, and as a result, stacking defects of the epitaxial wafer can be effectively reduced as shown in Examples described later. can.

Further, as shown in FIG. 6, a series of heat treatment steps of baking step, etching step, purging step and isothermal holding step are performed before epitaxial growth. In this series of heat treatment steps, the temperature is 700 ° C. or higher and lower than 1050 ° C. Since the temperature is kept constant at the same temperature, the cooling process can be excluded from the series of heat treatment steps. As a result, the generation of phosphorus precipitates during the cooling process can be suppressed, and the generation of stacking defects starting from the phosphorus precipitates can be suppressed.

Further, in addition to the isothermal holding step, the baking step, the etching step and the purging step are also kept at the isothermal temperature at a temperature of 700 ° C. or higher and lower than 1050 ° C. Can be extinguished or reduced, and phosphorus precipitates at the end of the isothermal holding step (at the start of the growth step) can be further reduced.

Further, the process shifts to the first growth step (S7 of FIGS. 5 and 6) while maintaining the temperature of the isothermal holding step (S6 of FIGS. 5 and 6), that is, the substrate temperature is not lowered during the shift. Therefore, the appearance of phosphorus precipitates due to the temperature drop (cooling process) can be suppressed, and the occurrence of stacking defects starting from the phosphorus precipitates can be suppressed.

Hereinafter, the present invention will be specifically described with reference to Examples and Comparative Examples, but these are not limited to the present invention.

(Example 1)
Six silicon single crystal substrates having a diameter of 200 mm and a thickness of 735 μm and whose main surface was mirror-polished so as to have a resistivity of 1.2 mΩ · cm or less were prepared. The resistivityes A1 and A2 of the two boards are set to be the same, the resistivityes B1 and B2 of the other two boards are set to be the same, and the resistivityes C1 and C2 of the remaining two boards are set to be the same. It is set. The magnitude relation of these resistivitys is B1, B2 <C1, C2 <A1, A2. The phosphorus concentration of each substrate is 5 × 10 ¹⁹ atоms / cm ³ or more, but the phosphorus concentration of the substrates having resistivityes B1 and B2 is the highest, which is 8 × 10 ¹⁹ atоms / cm ³ or more. ..

Six silicon epitaxial wafers were produced by performing the steps S2 to S8 shown in FIG. 5 on each of the prepared six substrates using the same vapor deposition apparatus as in FIG. At this time, the steps S2 to S8 were carried out according to the temperature profile of FIG. In the etching step of S4, the flow rate of hydrogen chloride gas was set to 1.0 slm, and the etching amount of the substrate was set to 0.045 μm. The total time of the purging step of S4 and the isothermal holding step of S5 was 120 seconds. In the growth step of S6 (the first growth step of S7 and the second growth step of S8), a silicon epitaxial layer having a total thickness of 4 μm was grown, of which 5 to 10% of the thickness was the first of S7. It was grown in the growth process of. Then, the produced silicon epitaxial wafer was measured by a defect measuring device (MAGICS manufactured by Lasertec Co., Ltd.), and the lamination defects generated in each silicon epitaxial wafer were measured.

(Example 2)
Silicon epitaxial wafers were produced under the same conditions as in Example 1 except that the temperature of the heat treatment steps of S2 to S5 was set to 850 ° C., and the stacking defects generated in each of the produced silicon epitaxial wafers were measured.

(Comparison example)
Silicon epitaxial wafers were produced under the same conditions as in Example 1 except that the temperature of the heat treatment steps of S2 to S5 was set to 1100 ° C., and the stacking defects generated in each of the produced silicon epitaxial wafers were measured.

(Comparison of the number of stacking defects)
FIG. 7 shows the number of stacking defects measured in Examples 1 and 2 and Comparative Example. In the comparative example, the number of stacking defects is 4000 (pieces / wafer) or more regardless of the wafer having the resistivity of the substrate. In particular, wafers with resistivityes B1 and B2 (phosphorus concentration of 8 × 10 ¹⁹ atоms / cm ³ or more) have a stacking defect number of about 7,000 (pieces / wafer), which is larger than the number of stacking defects having other resistivity. ing.

On the other hand, in Examples 1 and 2, the number of stacking defects is 500 (pieces / wafer) or less regardless of the wafer having any substrate resistivity, and the number of stacking defects is significantly reduced. This is because the phosphorus precipitates present on the substrate are effectively reduced as shown in FIGS. 1 to 3 by performing a heat treatment of maintaining the isothermal temperature at 750 ° C. or 850 ° C. for 30 seconds to 450 seconds or more before epitaxial growth. It is thought that this is the effect of being able to do it. Further, in both Examples 1 and 2, the number of stacking defects of substrate resistivity B1 and B2 (phosphorus concentration is 8 × 10 ¹⁹ atоms / cm ³ or more) is the number of stacking defects of other substrate resistivityes A1, A2, C1 and C2. The level is the same as that of the above, and the effect of reducing the number of stacking defects from the comparative example is remarkable.

As described above, the lamination defects of the epitaxial wafer are reduced by performing the heat treatment for maintaining the isothermal temperature for 30 seconds to 450 seconds or more at a temperature of 700 ° C. or higher and lower than 1050 ° C. (preferably 750 ° C. or higher and 850 ° C. or lower) before the epitaxial growth. can.

The present invention is not limited to the above embodiment. The above embodiment is an example, and any one having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect and effect may be used. It is included in the technical scope of the present invention.

For example, in FIGS. 5 and 6, an example in which the gas phase etching is performed before the epitaxial growth is described, but the gas phase etching may not be performed. In this case, the effect of reducing stacking defects can be obtained by carrying out the baking step at a temperature of 700 ° C. or higher and lower than 1050 ° C. (preferably 750 ° C. or higher and 850 ° C. or lower) under the condition of maintaining an isothermal temperature for 30 seconds to 450 seconds or longer. Can be done.

Further, in FIG. 6, an example is shown in which all the steps of S2 to S5 are carried out at a temperature of 700 ° C. or higher and lower than 1050 ° C. The effect of reducing stacking defects can be obtained if the process of maintaining the isothermal temperature for 30 seconds to 450 seconds or more at a temperature lower than (preferably 750 ° C. or higher and 850 ° C. or lower) is included. In this case, the heat treatment conditions immediately before epitaxial growth (after vapor phase etching and before the growth step) are maintained at an isothermal temperature of 700 ° C. or higher and lower than 1050 ° C. (preferably 750 ° C. or higher and 850 ° C. or lower) for 30 seconds to 450 seconds or longer. The condition is preferable because the effect of reducing stacking defects becomes remarkable.

Further, the steps S2 to S5 may be carried out at different temperatures. In this case, changing the temperature of each of the steps S2 to S5 within the temperature range of 700 ° C. or higher and lower than 1050 ° C. so as not to include the cooling process is effective in reducing phosphorus precipitates and the accompanying stacking defects. Is the target.

Further, the temperature may be raised in the transition from the heat treatment step before the epitaxial growth to the growth step. Specifically, for example, the growth step is composed of a single step having a constant growth rate, and the temperature of this growth step is made higher than the temperature of the heat treatment step before that. In this case, the growth step is carried out after the heat treatment step is completed and the temperature rise process is performed. Also in this case, since the cooling process is not included in the transition from the heat treatment step to the growth step, the effect of reducing phosphorus precipitates and the stacking defects associated therewith can be obtained.

1 Vapor deposition equipment 2 Reaction furnace 3 Suceptor 4 Gas supply port 5 Gas discharge port 6 Heating unit 7 Temperature measurement unit

Claims (11)

A preparatory step to prepare a phosphorus-doped silicon single crystal substrate,
A heat treatment step of performing a heat treatment of maintaining the silicon single crystal substrate at an isothermal temperature of 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer.
A growth step of growing an epitaxial layer on the main surface of the silicon single crystal substrate after the heat treatment,
Equipped with a,
The heat treatment step includes an etching step of vapor-phase etching with hydrogen chloride gas while heating the main surface of the silicon single crystal substrate, and a post-etching heat treatment step of heat-treating the silicon single crystal substrate after vapor phase etching. ,
In the post-etching heat treatment step, the temperature is maintained at an isothermal temperature of 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer.
A method for manufacturing an epitaxial wafer, wherein the temperature of the etching step is 700 ° C. or higher and lower than 1050 ° C. The method for manufacturing an epitaxial wafer according to claim 1, wherein the temperature of the silicon single crystal substrate is maintained at an equal temperature or raised when the heat treatment step is shifted to the growth step. The method for producing an epitaxial wafer according to claim 1 or 2, wherein after the silicon single crystal substrate is put into a reaction furnace, the silicon single crystal substrate is transferred to the growth step without lowering the temperature of the silicon single crystal substrate. The heat treatment step includes a pre-etching heat treatment step of heat-treating the silicon single crystal substrate before the vapor phase etching.
The method for manufacturing an epitaxial wafer according to any one of claims 1 to 3, wherein the temperature of the pre-etching heat treatment step is 700 ° C. or higher and lower than 1050 ° C. The fourth aspect of the present invention is characterized in that the temperature of the pre-etching heat treatment step, the temperature of the etching step, and the temperature of the post-etching heat treatment step are the same temperature, and are 700 ° C. or higher and lower than 1050 ° C. The method for manufacturing an epitaxial wafer according to the description. A preparatory step to prepare a phosphorus-doped silicon single crystal substrate,
A heat treatment step of performing a heat treatment of maintaining the silicon single crystal substrate at an isothermal temperature of 700 ° C. or higher and lower than 1050 ° C. for 30 seconds or longer.
A growth step of growing an epitaxial layer on the main surface of the silicon single crystal substrate after the heat treatment,
Equipped with a,
The heat treatment step includes an etching step of vapor-phase etching with hydrogen chloride gas while heating the main surface of the silicon single crystal substrate, and a pre-etching heat treatment step of heat-treating the silicon single crystal substrate before the vapor phase etching. The silicon single crystal substrate after the vapor phase etching is provided with a post-etching heat treatment step for heat-treating the silicon single crystal substrate.
Manufacture of an epitaxial wafer, wherein the temperature of the pre-etching heat treatment step, the temperature of the etching step, and the temperature of the post-etching heat treatment step are the same temperature, and are 700 ° C. or higher and lower than 1050 ° C. Method. The method for producing an epitaxial wafer according to any one of claims 1 to 6 , wherein in the preparation step, a silicon single crystal substrate doped with ^{phosphorus of 5 × 10 19} atоms / cm ^{3 or more is prepared.} The method for manufacturing an epitaxial wafer according to any one of claims 1 to 7 , wherein in the heat treatment step, the temperature is kept isothermal at 750 ° C. or higher and 850 ° C. or lower. The growth step includes a first growth step and a second growth step following the first growth step, in which the growth rate is higher than that of the first growth step.
The method for manufacturing an epitaxial wafer according to any one of claims 1 to 8 , wherein the growth rate is gradually increased in the first growth step. The first film thickness, which is the film thickness of the epitaxial layer grown in the first growth step, is smaller than the second film thickness, which is the film thickness of the epitaxial layer grown in the second growth step. The method for manufacturing an epitaxial wafer according to claim 9. The production of the epitaxial wafer according to claim 10 , wherein the first film thickness is 5 to 10% of the total film thickness of the first film thickness and the second film thickness combined. Method.

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