JP4760822B2 - Epitaxial wafer manufacturing method - Google Patents

Description

  The present invention relates to an improvement of an epitaxial wafer used for a semiconductor integrated circuit element, and the generation of epitaxial defects is caused by applying specific cooling during single crystal pulling growth with a resistivity of 0.008 to 0.025 Ω · cm. In addition, the present invention relates to a method for manufacturing an epitaxial wafer having excellent uniformity of oxygen precipitate density in the surface and excellent lG (Intrinsic Gettering) effect.

  High integration of silicon semiconductor devices is progressing remarkably, and higher quality of the silicon wafer itself of the substrate on which the devices are formed is demanded more severely. In other words, as the circuit pattern becomes finer with higher integration, in the device active region where the device on the wafer is formed, crystal defects such as dislocations that cause an increase in leakage current and a decrease in carrier lifetime and Reduction and removal of metal impurities is more strictly required than ever before.

In response to such a demand, an epitaxial wafer in which an epitaxial layer containing almost no crystal defects is grown on the wafer has been developed and is often used in the manufacture of highly integrated devices. As a wafer for growing this epitaxial layer, a p ⁺ silicon wafer doped with boron at a high concentration is generally used.

Why p ⁺ wafer is employed in the epitaxial wafer, as the reason for the device design First, the device will not operate the parasitic transistor the floating charge is not intended that occurs when operating, a so-called latch-up phenomenon p ⁺ This can be prevented by using a wafer, and device design may be facilitated. Further, when using a capacitor having a trench structure, there is an advantage that it can be prevented when the depletion layer spread at the time of applying a voltage around the trench is p ⁺ . The wafer an epitaxial layer grown on such a p ⁺ wafer referred to as p / p ⁺ epitaxial wafer.

In general, it is known that a low resistivity wafer to which boron is added at a high concentration hardly causes epitaxial defects even when an epitaxial layer is formed on the surface. However, in recent years, it has been found that when an epitaxial layer is formed on a p ⁺ wafer doped with boron in a resistivity range of 0.008 to 0.025 Ωcm, epitaxial defects frequently occur.

The inventors investigated this cause, and found that there was a crystal region in which the oxidation-induced stacking fault exceeded 1 × 10 ² / cm ² in the p ⁺ wafer in the resistivity range of 0.008 to 0.025 Ωcm. It has been found that an epitaxial defect is generated in a region where the oxidation-induced stacking fault exists.

  Although it is conceivable to change the resistance value in order to avoid epitaxial defects, a high-speed transistor is formed by forming an epitaxial layer having a high resistance value on the surface of a low resistance value wafer of 0.008 to 0.025 Ω · cm. Therefore, the reduction of epitaxial defects is strongly demanded for silicon single crystal wafers in the resistivity range.

Further, the occurrence of the oxidation-induced stacking fault can be reduced by lowering the oxygen concentration in the wafer. However, lowering the oxygen in the wafer leads to a decrease in the amount of acid precipitates formed inside the wafer, and lG (Intrinsic Gettering). ) The ability will be reduced. In consideration of this gettering ability, the oxygen concentration in the wafer needs to be at least 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more.

When the inventors tried to manufacture a p ⁺ wafer having a resistivity range of 0.008 to 0.025 Ωcm in the oxygen concentration range, inevitably, the oxidation-induced stacking fault was 1 × 10 ² / cm ² . It has been found that there is a problem that an excessive crystal region is always included in the wafer and the above-described epitaxial defect occurs.

The present invention has solved the problems in the above-mentioned p / p ⁺ epitaxial wafer found by the inventors, has no occurrence of epitaxial defects, has excellent in-plane uniformity of oxygen precipitate density, and has an excellent lG effect. It aims at providing the manufacturing method of an epitaxial wafer.

  For the purpose of preventing the occurrence of epitaxial defects, the inventors pay attention to the relationship between the thermal history received during the growth of a silicon single crystal and the defect, and the thermal history obtained by variously changing the pulling rate of the single crystal is different. As a result of growing an epitaxial layer on the wafer and intensively examining defects, it was found that the occurrence of epitaxial defects was suppressed by rapidly cooling the temperature range from 1100 ° C. to 900 ° C. after the pulling, and the present invention was completed. did.

That is, the present invention provides a silicon single crystal having a resistivity of 0.008 to 0.025 Ω · cm and an oxygen concentration of 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or more added with boron. In the step of pulling and growing by the Czochralski method, the temperature range from 1100 ° C. to 900 ° C. after the pulling is cooled at a cooling rate of 3.0 ° C./min or more, and oxidation-induced stacking faults generated during high-temperature oxidation treatment are 1 A step of obtaining a silicon single crystal having a property of × 10 ² / cm ² or less, a step of cutting and polishing a wafer from the single crystal, and a step of growing an epitaxial layer on the main surface of the wafer were cut out from the single crystal. Then, before mirror polishing, the epitaxial wafer is subjected to a heat treatment at a temperature of 700 ° C. or higher and lower than 900 ° C. for 30 minutes to 4 hours. It is a manufacturing method of C.

According to the present invention, the pulling speed can be increased when growing a silicon single crystal, the productivity of single crystal production is not reduced, and the thermal history at the time of growth is optimized, so that the target epitaxial layer is formed after wafer formation. P / p ⁺ epitaxial with reduced number of defects, good in-plane uniformity of oxygen precipitate density and high gettering ability, and stable resistivity of 0.008 to 0.025 Ω · cm A wafer can be provided.

  The inventors conducted an experiment to change the speed at which a silicon single crystal having a diameter of 8 inches is pulled up by the Czochralski method in order to investigate the influence of the thermal history during the growth of the silicon single crystal on the occurrence of epitaxial defects. Went.

  That is, boron is added so that the resistance value becomes 0.012 Ωcm, the straight body part is grown to a length of 500 mm at a lifting speed of 1.1 mm / min, and the lifting speed is changed to 1.8 mm / min at the time of 500 mm. Then, after returning to 1.1 mm / min at 550 mm and growing it to 1000 mm as it is, tail drawing was performed to finish the pulling up.

  The single crystal grown with the above-mentioned thermal history is changed from the temperature according to the distance from the melt at the start of the change in the pulling rate, that is, from the temperature corresponding to the distance from the solid-liquid interface to the low temperature side. It was quenched in the temperature range around 100 ° C.

  A sample was cut out from a portion of these single crystals that were quenched from 1400 to 600 ° C. and treated at 850 ° C. for 2 hours, and then mirror-polished to finish, and an epitaxial layer of 5 μm was further grown. An epitaxial wafer was obtained. FIG. 1 shows the result of measuring a surface defect of 0.09 μm size or more, that is, an epitaxial defect, using a surface defect inspection apparatus (SP-I manufactured by KLA-Tencor).

As is clear from the graph showing the relationship between the change start temperature of the pulling rate in FIG. 1 and the defect density, it was found that the occurrence of epitaxial defects was suppressed by rapidly cooling the temperature range from 1100 ° C. to 900 ° C. . This is presumably because the size of the Crown-in oxygen precipitation nuclei of the p ⁺ silicon single crystal wafer was reduced by rapid cooling.

  In the present invention, the resistivity of the silicon single crystal and the epitaxial wafer is defined as 0.008 to 0.025 Ω · cm, as described above, which is necessary to obtain a high-speed, high-performance, high-density semiconductor device. This is because it is a property.

The oxygen concentration of the silicon single crystal and the epitaxial wafer is preferably in the range of 11 to 18 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979). When the oxygen concentration is less than 11 × 10 ¹⁷ atoms / cm ^3, it is not possible to ensure the amount of oxygen deposited in the wafer to obtain a sufficient gettering effect in the device heat treatment process. When the oxygen concentration exceeds 18 × 10 ¹⁷ atoms / cm ³ , oxygen precipitation becomes excessive, and there is a possibility of generating secondary defects due to oxygen precipitates in the wafer.

In the present invention, the silicon single crystal and the epitaxial wafer are characterized in that oxidation-induced stacking faults generated during high-temperature oxidation treatment have a property of 1 × 10 ² / cm ² or less, which occurs during high-temperature oxidation treatment. When the oxidation-induced stacking fault to exceed 1 × 10 ² / cm ² , the number of epitaxial defects is increased, resulting in malfunction after device fabrication, etc., so that it is 1 × 10 ² / cm ² or less. The smaller the oxidation-induced stacking fault, the better the semiconductor device.

  The method for producing a silicon single crystal according to the present invention employs a method of pulling and growing a silicon single crystal by the Czochralski method, and any known method and apparatus can be employed. In particular, in order to realize the process of cooling the temperature range from 1100 ° C. to 900 ° C. at the time of pulling at a cooling rate of 3.0 ° C./min or more, which is a feature of the present invention, a single crystal to be grown as shown in the examples. It is possible to adopt a configuration and a method such as arranging a heat shield material surrounding the heat shield, and further attaching a cooling cylinder to the heat shield material.

  In this invention, the specific cooling temperature range is 1100 ° C. to 900 ° C. based on the inventor's knowledge, and the cooling rate of 3.0 ° C./min or more is the Crown-in oxygen precipitation. This is because the size of the nucleus can be reduced and the target epitaxial defects can be reduced, and the preferable cooling rate is 3.0 ° C./min to 6.5 ° C./min. However, excessive crystal cooling increases the thermal stress at the time of single crystal growth, so that the single crystal may break during single crystal growth. Therefore, it is desirable to keep it at 6.5 ° C./min or less.

  In this invention, by the Czochralski method, boron is added so as to have a resistivity of 0.008 to 0.025 Ω · cm, the silicon single crystal is pulled up and grown, and the specific temperature range is rapidly cooled. Even when a cooling cylinder is installed on the outer periphery of the single crystal most effective for cooling, in order to ensure a cooling rate in the temperature range of 1100 ° C. to 900 ° C., 3.0 ° C./min or more, the pulling rate of the single crystal Must be set to 0.9 mm / min or more. Moreover, in order to make the above-mentioned cooling rate into 6.5 degrees C / min or less, it is necessary to suppress a pulling-up speed to 1.8 mm / min or less.

In the present invention, in order to obtain an epitaxial wafer from a silicon single crystal having a property that the oxidation-induced stacking fault generated during the high-temperature oxidation treatment obtained by the above-described method is 1 × 10 ² / cm ² or less, at least the single crystal is obtained. Further, it is necessary to go through a process of cutting and polishing the wafer and a process of growing an epitaxial layer on the main surface. There are no particular limitations on the method of cutting into the wafer, the method of polishing the main surface or edge of the wafer, and the method of epitaxial film formation, and any known method, configuration, and apparatus can be employed.

  In this invention, in manufacturing an epitaxial wafer, after cutting a wafer from a single crystal and before mirror polishing, a heat treatment is performed at a temperature of 700 ° C. or higher and lower than 900 ° C. for 30 minutes to 4 hours. This is to provide an (intrinsic gettering) effect, and promotes the growth of small bent nuclei with boron (B) as a nucleus that disappears at a high temperature in the epitaxial process, and remains without disappearing by the epitaxial growth process. It is possible to increase the density of the oxygen breakout and improve the gettering effect. The reason for applying the heat treatment before mirror polishing is to leave no scratches from the holding jig during the heat treatment.

  As a preferable heat treatment condition, a protective oxide film can be formed to prevent contamination of the wafer by performing in a mixed atmosphere of oxygen and inert gas, and the oxide film can be removed by mirror polishing in the subsequent process. Since scratches from the holding jig during heat treatment can be removed by mirror polishing, it is desirable to perform such heat treatment before mirror polishing.

  A configuration example of a silicon single crystal growth apparatus is shown in FIG. More specifically, the crucible 1 is disposed at the center position of the apparatus, and the crucible 1 is composed of a quartz container 1a and a graphite container 1b disposed on the outside thereof.

  A heater 2 is disposed concentrically on the outer periphery of the crucible 1, and a melt 3 melted by the heater is accommodated in the crucible 1. Above the crucible 1, a pulling shaft 4 is mounted so as to be able to rotate and move up and down with a seed crystal 5, a single crystal 6 can be grown from the lower end of the seed crystal 5, and the pulling shaft The heat shield material 7 is arranged so as to surround the single crystal 6 grown with the rise of 4.

Comparative Example 1
A single crystal having the diameter of 8 inches, p-type (100), oxygen concentration of 13 × 10 ¹⁷ atoms / cm ³ , 0.015 Ω · cm to 0.012 Ω · cm, using the above-described silicon single crystal growth apparatus of FIG. Was grown at a pulling rate of 1.2 mm / min. A wafer cut out from the grown silicon single crystal and subjected to mirror polishing (Example No. 1), and a wafer subjected to a heat treatment held at 850 ° C. for 1 hour after the cutting and before the mirror polishing step (Example No. 2) ) And prepared.

  An epitaxial layer was grown to a thickness of 5 μm on the two kinds of wafers using an epitaxial film forming apparatus, followed by hydrogen baking for 1 minute at 1150 ° C. under a deposition temperature of 1075 ° C. With respect to the obtained epitaxial wafer, surface defects (epitaxial defects) having a size of 0.09 μm or more were counted with a surface defect inspection apparatus (manufactured by KLA-Tencor; SP-1).

  Next, these epitaxial wafers were heat-treated at 1000 ° C. for 16 hours to cleave the wafers, selectively etched with a light etchant for 5 minutes, counted for etching pit density with an optical microscope, and silicon The density of oxygen precipitates (BMD) formed in the wafer was determined. The measurement results are shown in Table 1.

  The number of epitaxial defects in Table 1 indicates the total number of measured 25 epitaxial wafers. Example No. of the comparative example in which the cooling rate in the temperature range of 1100 ° C. to 900 ° C. is 3.0 ° C./min or less. 1 and No. 2 has a large number of epitaxial defects. No. In No. 2, no heat treatment was performed before epitaxial film formation. BMD density higher than that of 1 was obtained, but epitaxial defects occurred frequently.

Example 1
In the silicon single crystal growing apparatus shown in FIG. 2, the temperature range of 1100 ° C. to 900 ° C. of the single crystal pulled up by incorporating the cooling cylinder 8 inside the heat shield material 7 and circulating the coolant as shown in FIG. In the same manner as in Comparative Example 1, the cooling rate is 8 inches in diameter, p-type (100), silicon having an oxygen concentration of 13 × 10 ¹⁷ atoms / cm ³ and 0.015 Ωcm to 0.012 Ωcm. Single crystals were grown at various pulling speeds.

  A wafer was cut out from a silicon single crystal grown at a pulling rate of 0.9 to 1.35 mm / min and mirror-polished (No. 3 to No. 5), and after the cut and before the mirror polishing step Wafers (No. 6 to No. 8) that had been heat-treated at 850 ° C. for 1 hour were prepared.

  An epitaxial layer was grown to a thickness of 5 μm on the two kinds of wafers using an epitaxial film forming apparatus, followed by hydrogen baking for 1 minute at 1150 ° C. under a deposition temperature of 1075 ° C. With respect to the obtained epitaxial wafer, surface defects (epitaxial defects) having a size of 0.09 μm or more were counted with a surface defect inspection apparatus (manufactured by KLA-Tencor; SP-1).

  Next, these epitaxial wafers were heat-treated at 1000 ° C. for 16 hours to cleave the wafers, selectively etched with a light etchant for 5 minutes, counted for etching pit density with an optical microscope, and silicon The BMD density formed in the wafer was determined. The measurement results are shown in Table 1.

  In the examples (Examples No. 3 to No. 8) of the present invention in which the cooling rate in the temperature range of 1100 ° C. to 900 ° C. is 3.0 ° C./min or more, the cooling rate is 3.0 ° C./min or less. It can be seen that the number of epitaxial defects is lower than that of the samples (Execution Nos. 1 to 2), and the generation thereof is suppressed. In addition, the implementation No. in which heat treatment was performed before epitaxial film formation was performed. 3-No. Also in 5, the number of epitaxial defects is suppressed low.

Further, by performing epitaxial pretreatment on a wafer grown at a cooling rate of 1100 ° C. to 900 ° C. at 3.0 ° C./min or higher, B / D density effective for gettering is high and the number of epitaxial defects is small. It can be seen that p ⁺ epitaxial wafers can be manufactured.

In the embodiment of the present invention in which the thermal history is optimized in this way, a single crystal can be grown at a pulling rate of 0.9 mm / min or higher, and high quality p / p ⁺ can be obtained without reducing the productivity of single crystal production. An epitaxial wafer can be manufactured.

Example 2
Furthermore, the implementation No. The same sample wafer as the silicon wafer produced in 1 to 8 was prepared, and the degree to which oxidation-induced stacking faults occurred when each sample wafer before the epitaxial growth treatment was subjected to high-temperature oxidation treatment was investigated.

The experimental conditions were that each sample wafer was heat treated in an oxidizing atmosphere at a temperature of 1100 ° C. for 16 hours, the wafer surface was etched using a light etchant for 5 μm, and then the wafer surface was observed at multiple points with an optical microscope. The number of pits observed at each observation point (oxidation-induced stacking fault density) was counted to measure the density at each observation point. The measurement results are shown in Table 1. In the table, the oxidation stacking fault density indicates the maximum value obtained among the observed points. Further, <1 × 10 ² in the table indicates a detection lower limit value in the measurement.

As is apparent from Table 1, in the examples of the present invention (Examples Nos. 3 to 8), no crystal region in which the oxidation-induced stacking fault exceeds 1 × 10 ² / cm ² is observed in the wafer plane. On the other hand, in the comparative example (Example Nos. 1 and 2), a crystal region in which the oxidation-induced formation layer defects exceeded 1 × 10 ² pieces / cm ² was observed in the wafer surface. This means that the amount of oxidation-induced stacking faults greatly affects the amount of epitaxial defects.

According to the present invention, when a silicon single crystal is grown, the pulling speed can be increased, the productivity of single crystal production is not reduced, and the thermal history at the time of growth is optimized, so that the target after forming into a wafer can be obtained. P / p ⁺ having a reduced number of epitaxial defects, good in-plane uniformity of oxygen precipitate density and high gettering ability, and a stable resistivity of 0.008 to 0.025 Ω · cm. An epitaxial wafer can be provided. Therefore, the present invention can be widely applied to the manufacture of epitaxial wafers used as substrates for highly integrated devices.

It is a graph which shows the relationship between the epitaxial defect density at the time of changing the pulling speed of the middle process by CZ method, and the temperature at the time of a pulling speed change start. It is explanatory drawing which shows schematic structure of the growth apparatus of a silicon single crystal. It is explanatory drawing which shows the structure which incorporates a cooling means in the heat shield material of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Crucible 1a Quartz container 1b Graphite container 2 Heater 3 Melt 4 Lifting shaft 5 Seed crystal 6 Single crystal 7 Heat shield material 8 Cooling cylinder

Claims (1)

A silicon single crystal having a resistivity of 0.008 to 0.025 Ω · cm and an oxygen concentration of 11 × 10 ¹⁷ atoms / cm ³ (ASTM F-121, 1979) or higher with boron added is pulled up by the Czochralski method. In the growing step, the temperature range from 1100 ° C. to 900 ° C. after the pulling is cooled at a cooling rate of 3.0 ° C./min or more, and oxidation-induced stacking faults generated during high-temperature oxidation treatment are 1 × 10 ² / cm ^2. Obtaining a silicon single crystal having the following properties:
Cutting and polishing a wafer from the single crystal,
A process of growing an epitaxial layer on the wafer main surface;
An epitaxial wafer manufacturing method comprising performing heat treatment at a temperature of 700 ° C. or higher and lower than 900 ° C. for 30 minutes to 4 hours after cutting a wafer from a single crystal and before mirror polishing.

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