WO2022172367A1

WO2022172367A1 - Method for predicting occurrence of defect in epitaxial silicon wafer and method for manufacturing epitaxial silicon wafer

Info

Publication number: WO2022172367A1
Application number: PCT/JP2021/005014
Authority: WO
Inventors: 浩三中村; 進前田; 剛士仙田; 吉亮安部; 真吾成松
Original assignee: グローバルウェーハズ・ジャパン株式会社
Priority date: 2021-02-10
Filing date: 2021-02-10
Publication date: 2022-08-18
Also published as: KR20230124056A

Abstract

Provided is a method that is for predicting the occurrence of a defect (stacking fault (SF)) in an epitaxial silicon wafer when the phosphorus concentration is to be defined arbitrarily and crystal thermal hysteresis is present. This method for predicting the occurrence of a defect comprises: a step for calculating a cooling curve of a silicon monocrystal; a step for calculating the concentration of at least interstitial phosphorus in each temperature process from the concentration phosphorus contained as a dopant; a step for calculating the size and density of depositions of phosphorus and silicon at the time of completion of cooling, from the degree of supersaturation of interstitial phosphorus during cooling; and a defect estimation step for estimating the density of defects (stacking faults (SFs)) in a silicon wafer after epitaxial growth, from the size and density of the depositions of phosphorus and silicon.

Description

Method for predicting occurrence of defects in epitaxial silicon wafer and method for manufacturing epitaxial silicon wafer

The present invention relates to a method for predicting the occurrence of defects in an epitaxial silicon wafer and a method for manufacturing an epitaxial silicon wafer.

Epitaxial silicon wafers for power MOS transistors require substrates with low resistivity. For this reason, silicon wafers heavily doped with phosphorus (P) are used as substrates for epitaxial growth.

On the other hand, it is known that when the resistivity of the substrate is lower than 0.9 mΩcm, many stacking faults (hereinafter referred to as SF) occur in the epitaxial film. These SFs (stacking faults) can be detected by etching, can be confirmed with the naked eye or under an optical microscope, and the density can be obtained. This SF (stacking fault) causes a problem in fabricating a power MOS transistor. Therefore, various methods have been tried to suppress the occurrence of such defects.

For example, in Patent Document 1, the cause of SF (stacking fault) occurring in the epitaxial film is the cluster formed by combining phosphorus and oxygen formed in the crystal growth process of the substrate crystal, and they are the epitaxial film. It is estimated that SF (stacking fault) occurs at the interface between Then, by examining the relationship with the thermal history during cooling of the crystal, the density of SF has a correlation with the residence time of the crystal passing through the temperature range of 570 ° C ± 70 ° C (500 ° C to 640 ° C), and its residence When the time is 200 minutes or more, SF (stacking fault) in the epitaxial wafer increases. However, Patent Document 1 does not confirm the presence of clusters formed by combining phosphorus and oxygen. In addition, in Patent Document 1, the reason why the cluster formed by combining phosphorus and oxygen is assumed to be the cause of SF is that phosphorus atoms cannot diffuse in the temperature range of 570 ° C. ± 70 ° C., so there is a possibility of diffusion. This is because we speculated that the oxygen atoms clustered around the phosphorus atom.

Further, in Patent Document 2, when annealing is performed for 30 minutes in an argon atmosphere at 1200° C. before epitaxial growth, the density and phosphorus concentration of SF (stacking fault) generated after epitaxial growth, and the temperature range of 570° C.±70° C. of the crystal An empirical formula for the relationship between the residence time of the argon anneal and the epitaxial growth temperature has been proposed.

Further, in Non-Patent Document 3, a phosphorus-doped crystal of 1.0 mΩcm is subjected to additional heat treatment from 400° C. to 800° C. in steps of 25° C. for 500 hours at each step, and changes in precipitation of phosphorus are investigated. there is As a result, SiP precipitates between 500°C and 700°C, but when heated to 775°C, the SiP generated at the low-temperature step dissolves and disappears, and only SFs and dislocations are observed. there is Some of the present inventors believe that when epitaxial growth treatment at 1130° C. is applied to a crystal in which high-density SiP precipitates are present, the SiP in the bulk portion of the wafer disappears, and the SiP density that existed in the as-grown We observe that the same density of SFs (stacking faults) is present.

Japanese Patent No. 5890587 JP 2019-142733 A

As described above, methods for suppressing the occurrence of SF (stacking faults) in epitaxial films have been proposed, but as will be explained below, they are still insufficient. The following analysis was made by the present inventors.

For example, Patent Document 1 states that the cause of SFs (stacking faults) occurring in an epitaxial film is clusters formed by bonding phosphorus and oxygen formed during the crystal growth process of the substrate crystal. However, some of the present inventors have reported in Non-Patent Document 1 that in a high-concentration phosphorus-doped crystal (resistivity of 0.87 mΩcm), high-density SiP precipitates are formed in the as-grown state. It is reported by TEM observation that it exists. Here, SiP is a compound of silicon and phosphorus, and unlike the speculation in Patent Document 1, does not contain oxygen.

Further, in Patent Document 1, in an epitaxial film using a phosphorus-doped substrate having a resistivity of 0.7 mΩcm or more and 0.9 mΩcm or less, in order to reduce SF (stacking fault) to 0.1/cm ² or less, states that the residence time in the temperature range from 500° C. to 640° C. in the crystal growth process of the substrate crystal must be 200 minutes or less. However, although it is shown that the temperature range during crystal growth to be controlled is 500° C. to 640° C. when the phosphorus doping is 0.7 mΩcm or more and 0.9 mΩcm or less, if the resistivity is outside the above range The temperature range to be managed is unknown. Since the temperature range to be managed is considered to correspond to the temperature zone in which SiP precipitates are generated and grow, it is thought that it changes depending on the resistivity (phosphorus concentration). In this method, it is necessary to find the temperature range to be controlled for each resistivity by experiment, and a great number of experiments are required.

In addition, since the method described in Patent Document 2 is also an empirical formula, it can only be applied within the range of the sample conditions from which the empirical formula was derived. Note that the resistivities of the samples from which the empirical formula was derived in Patent Document 2 are 0.6725, 0.68375, and 0.7225 mΩcm, and the applicable range is very narrow. Moreover, it can be applied only when annealing is performed in an argon atmosphere at 1200° C. for 30 minutes before epitaxial growth.

In addition, in Patent Document 2, one of the mechanisms for reducing SF (stacking fault) by lowering the furnace temperature at the time of loading the wafer in the pre-annealing process is that the amount of interstitial silicon introduced into the wafer is reduced. I am mentioning. However, as shown in Non-Patent Document 2, in the phosphorus-doped crystal, most of the phosphorus atoms are present at positions substituted for the lattice positions where silicon atoms are present, but some phosphorus atoms are present between silicon lattices. . In general, the diffusion coefficient of interstitial atoms is several orders of magnitude larger than that of atoms at substitution sites. On the other hand, the method described in Patent Document 2 does not consider the influence of interstitial phosphorus.

In this way, methods for suppressing the occurrence of SF (stacking faults) in epitaxial films have been proposed, but they are not applicable to arbitrary resistivities (that is, phosphorus concentrations). In addition, the scope of application regarding the thermal history of crystals is also limited.

The present invention has been made in view of the above problems, and provides a method for predicting the occurrence of defects in an epitaxial silicon wafer and a method for manufacturing an epitaxial silicon wafer for any given phosphorus concentration and crystal thermal history. With the goal.

A method for predicting the occurrence of defects in an epitaxial silicon wafer according to the present invention, which has been made to achieve the above object, is a method for predicting the occurrence of defects in an epitaxial silicon wafer manufactured by growing an epitaxial film using a silicon single crystal doped with phosphorus as a substrate. A generation prediction method, comprising: a thermal history calculation step of calculating a cooling curve of the silicon single crystal from temperature characteristics and a pulling rate including a pulling apparatus for manufacturing the silicon single crystal; a concentration calculation step of calculating at least the concentration of interstitial phosphorus in each temperature process of the cooling curve from the concentration; A precipitate calculation step of calculating the size and density of the substance, a defect estimation step of estimating the density of defects (SF: stacking fault) in the silicon wafer after epitaxial growth from the size and density of the phosphorous and silicon precipitates; including.

In the method for predicting the occurrence of defects in the epitaxial silicon wafer having the above configuration, the precipitates of phosphorus and silicon that cause stacking faults (SFs) in the epitaxial silicon wafer are more interstitial than the phosphorus present at the substitution position. Phosphorus is considered to be the cause, and the method of predicting the occurrence of defects can be improved by calculating mainly the concentration of interstitial phosphorus.

Further, in the concentration calculation step, it is preferable to calculate not only the concentration of interstitial phosphorus but also the concentration of vacancies, interstitial silicon, and reactants between phosphorus and vacancies. This is because interstitial phosphorus undergoes various reactions with vacancies, interstitial silicon, and reactants of phosphorus and vacancies during the crystal cooling process.

Then, in the defect estimation step, it is preferable to estimate the density of defects in the silicon wafer after the epitaxial growth using a threshold value of the size of precipitates of phosphorous and silicon to be detected determined in advance experiments. This is because the size of the SF (stacking fault) to be annealed out also changes depending on the pre-baking conditions performed in the previous stage of the epitaxial growth.

For example, if the threshold size of the precipitates of phosphorus and silicon is set to 12 nm, pre-baking is performed in a hydrogen atmosphere at 1130° C. for 60 seconds, and then an epitaxial film of 3 μm is grown at 1130° C., which is suitable for epitaxial conditions. be.

Further, in the method for producing an epitaxial silicon wafer according to the present invention, the occurrence of defects is predicted, and if the density of predicted defects does not satisfy a specified level, the pulling speed is adjusted to reduce the number of predicted defects. It is preferable to manufacture a phosphorus-doped silicon single crystal under the condition that the density satisfies a specified level, and grow an epitaxial film using the silicon single crystal as a substrate. Predicting defect density prior to actual manufacturing improves yield. Furthermore, it is conceivable to adjust the pre-baking conditions performed in the previous stage of epitaxial growth.

According to the present invention, it is possible to provide a method for predicting the occurrence of defects in an epitaxial silicon wafer and a method for manufacturing an epitaxial silicon wafer for any phosphorus concentration and crystal thermal history.

FIG. 1 is a schematic diagram of an example of a single crystal pulling apparatus using the CZ method. FIG. 2 is a graph showing the resistivity at each position on the straight body of Crystal 1 and Crystal 2. In FIG. FIG. 3 is a graph showing cooling curves at respective positions on the straight body of the crystal 1. FIG. FIG. 4 is a graph showing cooling curves at respective positions on the straight body of the crystal 2. FIG. FIG. 5 is a graph showing the densities of SFs (stacking faults) after epitaxial growth at each position on the straight body of Crystal 1 and Crystal 2 when the crystals were used as substrates. FIG. 6 is a graph showing the SiP density calculated for crystal 1. FIG. FIG. 7 is a graph showing the SiP density calculated for crystal 2. FIG. FIG. 8 is a graph comparing experimental results and calculation results of the relationship between the SF (stacking fault) density of the epitaxial film in the crystal 1 and the straight body position. FIG. 9 is a graph comparing experimental results and calculation results of the relationship between the SF (stacking fault) density of the epitaxial film in the crystal 2 and the straight body position. FIG. 10 is a flow chart schematically showing the procedure of the defect occurrence prediction method.

A method for predicting the occurrence of defects in an epitaxial silicon wafer according to an embodiment of the present invention will be described below with reference to the drawings. However, the method for predicting the occurrence of defects in an epitaxial silicon wafer according to the embodiments of the present invention is not limited to the embodiments described below. The attached drawings are schematic, and the dimensions and proportions of each element may differ from the actual ones.

First, considering the results of Non-Patent Document 1 and Non-Patent Document 3 together with the results of Patent Document 1, SF (stacking fault) in an epitaxial film when using a phosphorus-doped substrate wafer of 0.9 mΩcm or less. It is presumed that generation is generated by the following process.

(1) In a phosphorus-doped crystal with a resistivity of 0.9 mΩcm or less, SiP is generated and grows during a temperature interval of 570° C.±70° C. (500° C. to 640° C.) during the cooling process of the crystal.
(2) SiP dissolves and SF remains in the crystal during pre-baking heating performed in the preceding stage of epitaxial growth.
(3) In the cooling process of crystal growth, when the residence time between the temperature intervals of 570°C ± 70°C (500°C to 640°C) is short, the size of SiP is small, so the size of SF generated is also small. SFs (stacking faults) near the surface layer are annealed out in the pre-baking process, and no SFs remain on the surface layer when epitaxial growth is started.
(4) On the other hand, when the residence time between the temperature intervals of 570° C.±70° C. (500° C. to 640° C.) is long in the cooling process during crystal growth, the size of SiP increases, resulting in SF (stacking). SFs (stacking faults) near the surface layer are not annealed out during the pre-baking process. Then, SF remaining on the surface layer when epitaxial growth is started propagates as SF into the epitaxial film.

Considering that SFs are formed in the epitaxial film on the low-resistivity substrate in such a process, it is important to predict the density of SiP precipitates that act as nuclei that propagate as SFs to the epitaxial film. Then, the relationship between the predicted SiP size distribution and the stacking fault density of the epitaxial film is obtained, and the stacking fault of the epitaxial film is estimated from the relationship.

First, a method for obtaining the relationship between the predicted SiP size distribution and the SF (stacking fault) density of the epitaxial film will be described.
(1) Calculate the cooling curve during crystal growth.
(2) Calculate the generation and growth of SiP during cooling from the phosphorus concentration and the cooling curve.
(3) Determine the size distribution of SiP after cooling.
(4) Experimentally evaluate the SF (stacking fault) density of the epitaxial film for the corresponding phosphorus concentration and cooling curve.
(5) Understanding the relationship between SiP size distribution and SF (stacking fault) in the epitaxial film.

Each of the processes (1) to (5) will be explained below.

FIG. 1 is a schematic diagram of an example of a single crystal pulling apparatus using the CZ (Czochralski) method. The pulling apparatus shown in FIG. 1 has a general structure, and a quartz crucible 3 filled with a raw material melt 2 is rotatably installed in the center of the furnace 1 . A side heater 4 for heating the quartz crucible 3 from the side circumference and a bottom heater 5 for heating the quartz crucible 3 from the bottom are installed around the quartz crucible 3 . A radiation shield 6 is provided above the quartz crucible 3 for temperature control of the raw material melt 2 in the quartz crucible 3 and the crystal 9 to be pulled up.

In the single crystal pulling apparatus using the CZ method, a seed crystal 8 held at the lower end of a wire 7 is brought into contact with the liquid surface of the raw material melt 2 in the quartz crucible 3, and while the quartz crucible 3 and the seed crystal 8 are rotated, , the wire 7 is pulled up to grow the crystal 9 .

Model the structure of the pulling machine used for crystal growth as shown in Fig. 1 with a mesh structure, enter the physical property values for each member, and enter the pulling speed corresponding to the length position of the crystal. Then, the surface temperature distribution of each member is calculated based on the amount of heat generated by the heater and the emissivity of each member. On the other hand, the internal temperature distribution of each member is calculated by solving the heat conduction equation based on the surface temperature distribution and thermal conductivity of each member. In this way, the temperature distribution inside the pulled crystal is calculated. In addition, the cooling curve of the entire crystal including the temperature distribution inside the crystal is calculated by considering the pulling speed of the crystal.

These calculation processes can be calculated using comprehensive heat transfer analysis software commonly used by the engineer. There are three types of comprehensive heat transfer analysis software, such as 1) CGSim (STR), 2) CrysMAS (Crystal Growth Laboratory of the Fraunhofer Institute of Integrated Systems and Device Technology), 3) FEMAG (FEMAG soft). can be exemplified. Note that CGSim is used in the calculation examples described below.

Next, the process of forming SiP by aggregation of phosphorus atoms during the cooling process is calculated. As shown in Non-Patent Document 2, it is believed that phosphorus atoms in silicon exist mainly at positions substituted for silicon lattice points, and partly exist at interstitial sites of silicon. The diffusion coefficient of phosphorus atoms present at substitution positions is well known, and it is known that they hardly move in the temperature range where SiP is thought to occur. On the other hand, atoms existing between lattices generally diffuse at high speed. Therefore, it is believed that it is the interstitial phosphorus, rather than the phosphorus present at the substitution sites, that forms the SiP.

Therefore, first, the reaction of phosphorus during cooling of the crystal will be explained according to Non-Patent Document 2. Here, the reaction between phosphorus atoms and point defects in silicon crystals is assumed as follows. As for the form of phosphorus in silicon, the case where it exists at a position substituting a silicon atom at a lattice point is defined as P 2 _S , and the case where it exists between silicon _lattices is defined as P 1 . In addition, V denotes atomic vacancies, and I denotes interstitial silicon.

_PS +V=PV (1)
P _S+ +I+2e ⁻ =P _i− (2)

Here, PV is the reaction product of phosphorus and vacancies, P _s+ is the positively charged phosphorus at the substitution position, e is the electron, and P _i− is the negatively charged interstitial phosphorus. Also, in the formula (1) showing the reaction with the vacancies, it is assumed that the compound of the vacancies and phosphorus is electrically neutral. In equation (2), since it is assumed that the interstitial phosphorus P _i is negatively charged, the charge change is considered. Reference was made to Non-Patent Document 2 for this assumption.

Assuming that the reaction constants in equations (1) and (2) are K _V and K _I respectively, the following equations (3) and (4) are obtained according to the law of mass action.

_CV N/C _PV =K _V (3)
CIN/ _CPi ₌ KI( _ni / _n ) ² (4)
where _CV is the concentration of vacancies, N is the concentration of phosphorus, CPV is the concentration of _PV , _CI is the concentration of interstitial silicon, _CPi is the concentration of _Pi , n is the concentration of electrons, _ni is the intrinsic electron concentration. Here, _ni is expressed by Equation (5).

n _i (cm ⁻³ )=1.568×10 ¹⁵ T ^3/2 exp[−{1.17−(4.9×10 ⁻⁴ T ² /(T+655))}/2k _B T] (5)
Here, T is absolute temperature (K) and kB is Boltzmann's constant _8.6257 ×10 ⁻⁵ (eV/K).

The relationship between the electron concentration n and the donor-type impurity concentration N is given by the following equation (6).
n=N/ ² +[ ^N2 /4+ _ni2 ] ^1/2 (6)

Here, it can be seen from equation (3) that _CPV is proportional to N. On the other hand, from equations (4) and (6), C _Pi changes as follows. From equation (6), the electron concentration n becomes n=n _i when N<<n _i , and n=N when N>>n _i . Therefore, when the phosphorus concentration is low, C _Pi is proportional to N when N<<n _i , and when the phosphorus concentration is high, N>>n _i , C _Pi is proportional to the third power of N. That is, when the phosphorus concentration N exceeds the intrinsic electron concentration, the interstitial phosphorus concentration _CPi is expected to increase sharply. This indicates that the interstitial phosphorus concentration _CPi becomes dominant at the phosphorus concentration N to be considered in the present invention.

Another reaction that occurs during crystal growth is the pair annihilation reaction between vacancies and interstitial silicon shown in Equation (7).
V+I=0 (7)

Then, the reaction rate of the pair annihilation reaction is shown by Equation (8).
dC _V /dt=dC _I /dt=-K _IV (C _V C _I -C _V ^eq C _I ^eq ) (8)
Here, C _V ^eq and C _I ^eq are the thermal equilibrium concentrations of vacancies and interstitial silicon, respectively.

Moreover, K _IV is represented by Formula (9).
K _IV =4πa _c (D _V +D _I ) exp(−ΔG/k _B T) (9)
where a _c =0.543×10 ⁻⁷ cm and D _V and D _I are the diffusion coefficients of vacancies and interstitial silicon, respectively. ΔG is a barrier for pair annihilation reactions, and since ΔG is generally assumed to be zero, it was set to zero here.

Next, changes in the concentrations of C _V , C _I , C _PV and C _Pi during the cooling process of the crystal are shown. It is assumed that V, PV, _I , and Pi change while the reactions of equations (1) and (2) always maintain a steady state of balance. That is, the equations (3) and (4) are always satisfied.

First, the relationship between _CV and _CPV will be shown. Here, since C _PV <<N, the change in the phosphorus concentration N due to the formation of PV is ignored. The sum of the densities of V and PV is defined as C _V ^T as in equation (10).
_CV ^T = _CV + _CPV (10)

Then, equation (3) becomes equation (11).
( _CVT-CPV ₎ N/ ^CPV ₌ _KV (11)

That is, if ^CVT is known, _CPV can be _obtained using equation (12).
_CPV = _CVT /( ^KV _/ N+1) (12)

Next, the relationship between the concentrations of C _I and C _Pi is obtained from equation (4). Here, since C _Pi <<N, the change in the phosphorus concentration N due to the formation of P _i is ignored. Also, the concentration ratio between the equilibrium concentration of P _i and P _S is defined as R as in equation (13).
R=C _Pi ^eq /N (13)

Now that we have shown a new parameter, R, the relationship to _KI is shown below. First, equation (4) holds true even when each component has an equilibrium concentration, so it can be written as equation (14).
C _IN /C _Pi =C _I ^eq N/C _Pi ^eq (14)

Therefore,
^CIN/CPi=CIeq _/ _R ₍ 15)

Also, from equations (13) and (14), it can be seen that the relationship between R and _KI is expressed by equation (16).
R=C _I ^eq (n/n _i ) ² /K _I (16)

The sum of the densities of I and P _i is defined as C _I ^T as in equation (17).
C _I ^T = C _I + C _Pi (17)

Then, formula (18) is obtained from formula (15).
C _Pi /N=R(C _I ^T −C _Pi )/C _I ^eq (18)

When this is expanded and rearranged, the formula (19) is obtained.
C _Pi =C _I ^T /{C _I ^eq /(NR)+1} (19)

Now, with the equations derived so far, the changes in V, _I , PV, and Pi during cooling can be calculated. Next, a specific calculation procedure is shown. Here, the concentration at the solid-liquid interface, ie, 1685K, is the initial condition. Then, at the solid-liquid interface, all concentrations are assumed to be thermal equilibrium concentrations. That is, the initial density is given by the following equation (20).

CV = _CV ^eq at _1685K
C _I =C _I ^eq at 1685K
C _PV =C _V ^eq N/K _V at 1685K
C _Pi =NR at 1685K (20)

Changes in V and I during cooling are determined by equation (8) for each temperature drop to determine changes in C _V and C _I . Then, changes in _CVT and ^CIT are determined from changes in ^Cv and _CI , and _CPV and _CPi are _determined from _equations (12) and (19). By obtaining this for each temperature lowering step, changes in concentration of V, _I , PV and Pi can be obtained.

It should be noted that each temperature-dependent parameter is set as shown in Equations (21) to (26).

C _V ^eq =6.49×10 ¹⁴ exp[−3.94{1/(k _B T)−1/(1685 k _B )}] (21)
C _I ^eq =4.84×10 ¹⁴ exp[−4.05{1/(k _B T)−1/(1685 k _B )}] (22)
D _V =4.45×10 ⁻⁵ exp[−0.3{1/(k _B T)−1/(1685 k _B )}] (23)
D _I =5.0×10 ⁻⁴ exp[−0.9{1/(k _B T)−1/(1685 k _B )}] (24)
K _V =9.61×10 ¹⁹ exp[−1.0{1/(k _B T)−1/(1685 k _B )}] (25)
K _I =3.5×10 ²⁰ exp[−1.2{1/(k _B T)−1/(1685 k _B )}] (26)
k _B here is 8.6257×10 ⁻⁵ (eV/K).

Next, a model representing the nucleation and growth process of SiP will be explained. As a nucleation rate model, the model regarding clusters of vacancies proposed in Non-Patent Document 4 is referred to and applied to SiP.

In the classical nucleation theory, nucleation is considered as a process that overcomes the energy barrier associated with cluster formation by thermal fluctuation. Here we assume that the SiP is a sphere. Assuming that the nucleus is a sphere, the change in free energy associated with the generation of a particle of radius R is given as follows.

ΔG(R)=−(4πR ³ /3Ω)f+4πR ² σ (27)
f=k _B Tln(C _Pi /C _Pi ^eq ) (28)

where Ω is the volume per molecule of SiP (4.08×10 ⁻²³ cm ³ ). Also, f is the chemical potential of phosphorus, and -f indicates the energy change of the system when one SiP is deposited. The term 4πR ² σ indicates the surface energy, where σ is the surface energy per unit area of SiP (σ=556 erg/cm ² ). Also, k _B in Equations (27) and (28) is 1.381×10 ⁻¹⁶ (erg/K).

ΔG(R) takes a maximum value with increasing radius. The radius at the maximum value is the critical radius R _cri and the maximum value of ΔG(R) is ΔG*. ΔG* represents the energy barrier associated with cluster formation.

R _Cri =2σΩ/f (29)
ΔG*=16πσ ³ Ω ² /(3f) ² (30)

The frequency of nucleation is defined as the frequency at which a nucleus with the size of R _cri is generated due to thermal fluctuations and the frequency at which another atom is added to the nucleus to overcome the peak of the maximum value and form a precipitate. be. At that time, the steady-state nucleation rate I is represented by equation (31).

I= ^βZρeq (31)
Here, β is the capture rate of the element to the critical nucleus, and Z is a factor called Zeldovich factor that corrects the ratio of the thermal equilibrium density to the steady state density. ρ ^eq is the thermal equilibrium density of the critical nucleus.

^ρeq = _ρexp (−ΔG*/kBT) (32)
where ρ is the density of silicon sites (5×10 ²² cm ⁻³ ).

β=4πR _cri D _Pi C _Pi (33)
where D _Pi is the diffusion coefficient of interstitial phosphorus.

Z=f( _12πΔG *kB T) ^−1/2 (34)

Therefore, each occurrence speed I is represented by the following formula (35).

I=(4πR _cri D _Pi C _Pi ) _Zρexp (−ΔG*/kB T) (1/sec·cm ³ ) (35)

That is, during cooling of the crystal, SiP is generated at the rate shown in formula (35). The density of SiP generated during every 30 seconds is integrated, and the growth of SiP and the absorption of interstitial phosphorus generated in each time interval are calculated until cooling is completed.

The SiP growth rate is shown in equation (36).
dR/dt=ΩD _Pi (C _Pi −C _Pi ^eq )/R (36)

With R _Cri as the initial size, the change dR of the radius at each time step was obtained by Equation (36), and the radius was obtained as R=R+dR. The absorption flux of phosphorus by SiP is shown in equation (37).

J=4πRD _Pi (C _Pi −C _Pi ^eq ) (37)

Equation (37) above represents the interstitial phosphorus absorbed by one SiP. This is integrated and added to the change in interstitial phosphorus concentration. where D _Pi is given by equation (38).

D _Pi =3×10 ⁻⁷ exp[−1.1{1/(k _B T)−1/(1685 k _B )}] (38)
Here k _B is 8.6257×10 ⁻⁵ (eV/K).

As described above, the concentrations of atomic vacancies V, interstitial silicon _I , phosphorus and vacancy reactants PV, and interstitial phosphorus Pi during the cooling process of the crystal are obtained, and generation and growth of SiP are calculated.

Next, the relationship between the SiP size distribution estimated by calculation and the SF (stacking fault) density in the epitaxial film under the corresponding experimental conditions is examined.

<Experiment>
The crystals used for the evaluation are two crystals, crystal 1 and crystal 2, and have a diameter of 200 mm. FIG. 2 is a graph showing the resistivity at each position on the straight body of Crystal 1 and Crystal 2. In FIG. As shown in FIG. 2, crystal 1 varies in resistivity from 0.9 mΩcm to 0.7 mΩcm and crystal 2 varies in resistivity from 0.75 mΩcm to 0.55 mΩcm. Crystal 1 and Crystal 2 are used to evaluate the occurrence of defects in a wide range of resistivities.

FIG. 3 is a graph showing the cooling curve at each position on the straight body of the crystal 1, and FIG. 4 is a graph showing the cooling curve at each position on the straight body of the crystal 2.

<Epitaxial condition>
The manufacturing conditions for the epitaxial film are as follows. First, as pre-baking, pre-baking is performed in a hydrogen atmosphere at 1130° C. for 60 seconds. Thereafter, an epitaxial film of 3 μm is grown at 1130° C. for epitaxial growth.

<SF: Stacking fault evaluation>
An epitaxial silicon wafer produced as described above is inspected for stacking faults. SFs (stacking faults) can be detected by etching, confirmed with the naked eye or under an optical microscope, and the density can be determined.

FIG. 5 is a graph showing the densities of SFs (stacking faults) after epitaxial growth when the crystals at each position on the straight body of Crystal 1 and Crystal 2 are used as substrates. This experimental result is compared with the SiP obtained by the calculation method described above.

6 and 7 are graphs showing SiP densities calculated by the method described above for crystal 1 and crystal 2, respectively. FIG. 6 shows the relationship between the density and the position in the straight body of SiP radii of >4, >6, >8, >10, >12, >14, and >16 nm, respectively, calculated under the manufacturing conditions of crystal 1. showing relationships. FIG. 7 shows the same calculation results under the manufacturing conditions of crystal 2. FIG.

6 and 7 show the number of SiPs per unit volume (pieces/cm ³ ), whereas the experimental results shown in FIG. pieces/cm ² ). Therefore, the two cannot be directly compared. Consider the following.

First, SiP melts in the hydrogen baking process that precedes epitaxial processing, leaving SFs, but small SFs (stacking faults) near the surface disappear. The size of the SF remaining after the SiP dissolves is determined by the size of the SiP. Therefore, the longer the time passed through 570° C.±70° C., which is considered to be the generation/growth period of SiP, the larger the size of SiP and the more SFs that do not disappear in the process of hydrogen baking. Here, it is assumed that the size of SF generated after SiP is dissolved is equal to the size of SiP.

Then, the density at which SF is partially exposed on the surface and taken over by the epitaxial film is 2rD(r), where the density of particles with a radius of r is D(r) (particles/cm ³ ). become. Also, if the radius of SiP is smaller than the threshold value R _cri , it is considered that the SF generated after the dissolution of SiP disappears due to hydrogen pake. Therefore, the number per area exposed on the surface was calculated with a radius r greater than the threshold value R _cri . The density SF(R) (particles/cm ² ) at which particles above the threshold value R appear on the surface is expressed by the following equation (39).

Here, SF(R) in Equation (39) represents SiPs with a radius R or greater, that is, the number of SFs exposed on the surface per area.

8 and 9 show the experimental results of the relationship between the SF (stacking fault) density and the straight body position of the epitaxial films in crystal 1 and crystal 2, respectively, and calculations with threshold values of 8, 10, 12, 14, and 16 nm. It compares the relationship between the SF (stacking fault) density and the straight body position. 8 and 9 that the calculated SF (stacking fault) density with a threshold of 12 nm agrees with the experimental results.

From the above results, it can be seen that the following defect generation prediction method is effective for epitaxial silicon wafers manufactured by growing an epitaxial film using silicon doped with phosphorus as a substrate. FIG. 10 is a flow chart schematically showing the procedure of the defect occurrence prediction method.

First, as a preparatory step, obtain the temperature characteristics including the pulling equipment that manufactures the silicon single crystal doped with phosphorus (Step S1). Since the lifting device has a structure as shown in FIG. 1, for example, heat transfer analysis is performed using the capabilities of the side heater 4 and the bottom heater 5, the positional relationship of the radiation shield 6, etc., and the physical property values of each member. Get information for

After that, the cooling curve of the crystal is calculated from the pulling speed for actually producing the silicon single crystal doped with phosphorus (Step S2).

On the other hand, from the concentration of phosphorus doped into the silicon single crystal, at least the concentration of interstitial phosphorus in each temperature process of the cooling curve is calculated (Step S3). As described above, the precipitates of phosphorus and silicon (SiP) that cause stacking faults (SF: stacking faults) in epitaxial silicon wafers have more interstitial phosphorus (P _i ) than phosphorus present at substitution positions. This is because it is considered to be the cause.

However, this is not limited to calculating only the concentration of interstitial phosphorus (P _i ). This is because interstitial phosphorus (P _i ) undergoes various reactions with vacancies (V), interstitial silicon (I), and reactants (PV) of phosphorus and vacancies during the crystal cooling process. Therefore, in the calculation in Step S3, not only the concentration of interstitial phosphorus but also the concentration of vacancies (V), interstitial silicon (I), and reactants (PV) between phosphorus and vacancies can be calculated. preferable.

After that, from the supersaturation of interstitial phosphorus (P _i ) during cooling of the crystal, the size and density of precipitates of phosphorus and silicon (SiP) at the completion of cooling are calculated (Step S4).

Then, the density of defects in the silicon wafer after epitaxial growth is estimated from the size and density of precipitates of phosphorus and silicon (SiP) when cooling is completed (Step S5). In addition, for this estimation, an experiment was conducted in advance on the relationship between the size and density of precipitates of phosphorus and silicon (SiP) and the density of defects in the silicon wafer after epitaxial growth, and the precipitates of phosphorus and silicon to be detected It is preferable to set a threshold for the size of (SiP). This is because the size of the SF (stacking fault) to be annealed out also changes depending on the pre-baking conditions performed in the previous stage of the epitaxial growth.

As for the epitaxial conditions, when pre-baking is performed in a hydrogen atmosphere at 1130° C. for 60 seconds and then an epitaxial film of 3 μm is grown at 1130° C., the threshold of the size of precipitates of phosphorus and silicon (SiP) is set to 12 nm. , the SF (stacking fault) density agrees with the experimental results.

The defect occurrence prediction method described above can also be implemented as an epitaxial silicon wafer manufacturing method in which an epitaxial film is grown on a silicon substrate doped with phosphorus.

That is, the occurrence of defects is predicted from the concentration of phosphorus doped in the silicon single crystal and the pulling speed of the crystal. It is conceivable to manufacture an epitaxial silicon wafer under the condition that the density of defects satisfies a specified level.

If the predicted defect density does not meet the prescribed level, it is possible to adjust the pre-baking conditions performed in the previous stage of epitaxial growth.

Although the present invention has been described above based on the embodiments, the present invention is not limited by the above embodiments.

REFERENCE SIGNS LIST 1 furnace 2 raw material melt 3 quartz crucible 4 side heater 5 bottom heater 6 radiation shield 7 wire 8 seed crystal 9 crystal

Claims

A method for predicting the occurrence of defects in an epitaxial silicon wafer manufactured by growing an epitaxial film using a silicon single crystal doped with phosphorus as a substrate, comprising:
a thermal history calculation step of calculating a cooling curve of the silicon single crystal from temperature characteristics and a pulling rate including a pulling apparatus for manufacturing the silicon single crystal;
a concentration calculation step of calculating at least the concentration of interstitial phosphorus in each temperature process of the cooling curve from the concentration of phosphorus doped in the silicon single crystal;
a precipitate calculation step of calculating the size and density of phosphorus and silicon precipitates at the completion of cooling from the interstitial phosphorus supersaturation during cooling of the silicon single crystal;
a defect estimation step of estimating the density of defects in a silicon wafer after epitaxial growth from the size and density of the precipitates of phosphorus and silicon;
A method for predicting the occurrence of defects in an epitaxial silicon wafer containing
2. The defect in the epitaxial silicon wafer according to claim 1, wherein in said concentration calculation step, not only the concentration of interstitial phosphorus but also the concentration of vacancies, interstitial silicon, and reaction products between phosphorus and vacancies are calculated. occurrence prediction method.
2. In the defect estimation step, the density of defects in the silicon wafer after epitaxial growth is estimated using a threshold value of the size of precipitates of phosphorous and silicon to be detected determined in advance experiments. 3. The method for predicting occurrence of defects in the epitaxial silicon wafer according to 2.
The method for predicting occurrence of defects in an epitaxial silicon wafer according to claim 3, wherein the threshold size of the precipitates of phosphorus and silicon is 12 nm.
The defect occurrence prediction according to any one of claims 1 to 4 is performed, and if the predicted defect density does not meet a specified level, the pulling speed is adjusted to predict the number of defects. A method for producing an epitaxial silicon wafer, comprising: producing a silicon single crystal doped with phosphorus under a condition that the density satisfies a specified level; and growing an epitaxial film using the silicon single crystal as a substrate.
The method for manufacturing an epitaxial silicon wafer according to claim 5, further comprising adjusting the pre-baking conditions performed in the pre-stage of epitaxial growth.