JPH01298726A - Manufacture of semiconductor wafer and semiconductor device using the semiconductor wafer - Google Patents

Abstract

PURPOSE:To obtain a wafer having no defective region of high quality and defective nucleus growth region by annealing the wafer made of high oxygen concentration silicon single crystal grown at a low temperature by a Czochralski method, and then forming a silicon epitaxial layer on its surface. CONSTITUTION:After the surface of a wafer is lapped, it is annealed at a low temperature, for example, 700 deg.C in a nitrogen atmosphere for 3 hours to form a defective nucleus in a whole interior. Then, after the surface of the wafer 1 is mirror-fihished, a P-type silicon epitaxial layer 2 is formed on the surface of the wafer by a CVD method. A thin insulating film 3 is formed by a thermally oxidizing method on its main surface, an Si3N4 film 4 covering the surface is etched to allow the film 4 to remain only on an active region, and a channel stopper region 5 is then formed from the surface of the layer 2. Then, the wafer 1 is oxidized with steam to form a field insulating film 6. In case of the steam oxidation, oxygen among lattice is precipitated in the defective nucleus in the wafer 1, and inner defects to become a gettering source such as SiO2 precipitate, laminated layer defects are grown.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer manufacturing technique and a semiconductor device using the semiconductor wafer.

[Conventional technology]

Intrinsic gettering is a method that uses oxygen precipitation defects that occur inside a semiconductor wafer (hereinafter referred to as a wafer) to collect contaminant impurities in areas other than the device active region and remove their negative effects.
BACKGROUND ART Gettering (hereinafter referred to as IG) technology has become an essential technology for improving the characteristics and yield of integrated circuits formed on wafers.

The above IG process is described in, for example, Japanese Patent Application Laid-Open No. 55-96641.
As described in Japanese Patent Publication No. 56-80139, (1) high-temperature annealing (approximately 1050 to 1200°C) to form a defect-free region (denuded zone) near the surface of the wafer; ■Low temperature annealing (approximately 60
(0 to 800°C), (2) Medium temperature annealing (around 1000°C) to concentrate micro defects inside the wafer around the defect cores to form a high-density defect region. - A process performed in the order of medium temperature (Japanese Patent Application Laid-Open No. 56-80139) and a process performed in the order of low temperature-high temperature-medium temperature (Japanese Patent Application Laid-Open No. 55-96641) are adopted.

In addition, the above IG may be performed in advance at a stage before introducing the process, or may be performed using a heat treatment step during the process, but in either case, crystal growth using the Czochralski method (CZ method) is performed. Sometimes the concentration of oxygen doped is, for example, 9. OX 10" ~ 1.I
It is usual to use a silicon single crystal wafer with a high oxygen concentration of about 10'' atoms/cd (Japan Electronics Industry Promotion Association conversion factor, hereinafter the same).

[Problem to be solved by the invention]

According to studies by the present inventors, conventional IC technology using high oxygen concentration silicon single crystal wafers has the following problems.

First, in the IG process, in which annealing is performed in the order of high temperature, low temperature, and medium temperature, defect nuclei are unlikely to occur because high temperature annealing is performed to form a defect-free area on the wafer surface, and then low temperature annealing is performed to form internal defect nuclei. This has the disadvantage of requiring long-term low-temperature annealing.

In recent years, processes have become increasingly low-temperature-oriented, so if high-temperature annealing is performed during the process, the annealing time is insufficient, and internal defects may rise to the surface of the wafer during the subsequent medium-temperature process. There is a risk that this may occur.

On the other hand, in the IG process where annealing is performed in the order of low temperature - high temperature - medium temperature, low temperature annealing is performed to form internal defect nuclei, and then high temperature annealing is performed to form defect-free regions.
Although it has the advantage of shortening low-temperature annealing time,
There is a drawback that micro defects tend to remain in the defect-free region, that is, in the element active region.

Furthermore, if high temperature annealing is performed during the process, there is a risk that internal defects will rise to the surface of the wafer during the subsequent medium temperature process for the reasons described above.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a method for manufacturing a silicon single crystal wafer having a high-quality defect-free area and a semiconductor device using the wafer. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, this is a method in which a wafer made of high oxygen concentration silicon single crystal grown by the Czochralski method is subjected to low-temperature annealing treatment, and then a silicon epitaxial layer is formed on the surface of the wafer.

[Effect]

The interstitial oxygen concentration in the silicon epitaxial layer is about an order of magnitude lower than the interstitial oxygen concentration in the silicon single crystal obtained by the Czochralski method, so even if medium temperature treatment of about 1000°C is performed, micro defects will not occur in the epitaxial layer. It will never occur.

In other words, since this epitaxial moisture can be used as a defect-free area, a wafer with a high-quality defect-free area can be obtained even if high-temperature annealing for the purpose of forming a defect-free area is omitted or the high-temperature annealing time is short. .

In addition, high oxygen concentration silicon single crystal wafers that have been annealed at a low temperature of about 600 to 800°C are then subjected to medium temperature annealing, which causes oxygen to precipitate into internal defect nuclei and cause the defect nuclei to grow. It has a gettering effect.

Therefore, for wafers on which an epitaxial layer is formed on the surface after low-temperature annealing, high-temperature annealing for the purpose of forming defect-free regions can be omitted.
Since growth of internal defects is facilitated, low-temperature annealing for defect nucleation can be done in a short time.

〔Example〕

FIGS. 1(a) to 1(6) are cross-sectional views of essential parts of a semiconductor wafer showing the manufacturing process of a semiconductor device using a semiconductor wafer according to an embodiment of the present invention.

First, by the Czochralski method, for example, a silicon single crystal ingot with an initial interstitial oxygen concentration = 10XlO'' atoms/crl (Japan Electronics Industry Promotion Association conversion coefficient) and a resistivity = approximately 100 cm is pulled, and this is (100
) to create wafers.

Next, after lapping the surface of the wafer, for example,
Low-temperature annealing is performed for 3 hours in a nitrogen atmosphere at 00° C. to form defect nuclei throughout the interior.

Next, after performing polishing to give the surface of the wafer a mirror finish, a p-type silicon epitaxial layer with a film thickness of approximately 10 μm and a resistivity of approximately 10 Ω・am, for example, is formed on the surface of the wafer using the CVD method. The layer is used as a device active region to form the desired integrated circuit on its surface.

First, as shown in FIG. 1(a), a thin insulating film 3 is formed by thermal oxidation on the main surface of an epitaxial layer 2 formed on the surface of a wafer 1, and 5isN4 is deposited on the surface by CVD. Etching the membrane 4 and adding 5is only to the active area
N<After leaving the film 4, from the surface of the epitaxial layer 20,
For example, boron (B) ions are implanted to form the channel stopper region 5, and then the wafer 1 is
A field insulating film 6 is formed by steam oxidation at .degree. C. for 5 hours.

During the steam oxidation, interstitial oxygen precipitates at defect nuclei inside the wafer 1, and internal defects that become gettering sources such as SiO, precipitates, and stacking faults grow.

Next, after removing the active region insulating film 3 and the Sl*Ns film 4 to form a first gate insulating film 7, a first conductive layer made of polysilicon, for example, is deposited on the surface of the wafer 1. is patterned to form a capacitor electrode 8, and then
After removing the first gate insulating film 7, the wafer 1 is thermally oxidized to form a second gate insulating film 9 in the transistor formation region and an insulating film 10 on the surface of the capacitor electrode 80 (see FIG. 1). b)).

Next, a second conductive layer consisting of two layers of, for example, polysilicon and tungsten silicide (WSi) adhered to the surface of the wafer 1 is patterned to form a second gate insulating film 9.
After forming a gate electrode 11 on the surface of the wafer 1, n-type impurity ions such as arsenic (As) are implanted into the surface of the wafer 1 to form source/drain regions 12 in a self-aligned manner on both sides of the gate electrode 11. For example, phosphosilicate glass (PSG) or boron phosphosilicate glass (B
An interlayer insulating film 13 made of PSG) is deposited (FIG. 1(C)).

Next, after forming a contact hole 14 in the upper region of the source/drain region 12, the Al film deposited on the surface of the wafer 1 is patterned to form an AI! After forming the wiring 15, the surface of the wafer 1 is coated with a passivation film 1.
6, and then holes are formed at predetermined locations to form electrode pads 17, thereby forming an MO3O3 memory element (FIG. 1 (6)).

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the above embodiment, low-temperature annealing was performed after the roughing process, but the present invention is not limited to this. For example, low-temperature annealing may be performed after a mirror finishing process by polishing and before introducing a wafer process.

Furthermore, the present invention can be applied not only to MO3 type semiconductor devices but also to various semiconductor devices using a wafer made of silicon single crystal, such as bipolar type semiconductor devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, a wafer made of high oxygen concentration silicon single crystal grown by the Czochralski method is subjected to low-temperature annealing treatment, and then a silicon epitaxial layer is formed on the surface, resulting in high-quality defect-free areas and defect nucleus growth. Since a wafer having a region is obtained, the reliability of an integrated circuit formed on this wafer and a semiconductor device using the same is improved.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are sectional views of essential parts of a semiconductor wafer, showing the manufacturing process of a semiconductor device using a semiconductor wafer according to an embodiment of the present invention. 1... Silicon single crystal wafer, 2... Epitaxial layer, 3.10... Insulating film, 4... 513N4 film,
5... Channel stopper region, 6... Field insulating film, 7... First gate insulating film, 8... Capacitor electrode, 9... Second gate insulating film, 11... Gate electrode, 12... Source/drain region, 13... Interlayer insulating film, 14... Contact hole, 15... Al
Wiring, 16... Passivation film, 17... Electrode pad. Fig. 1 1, Silicon Sosagina Rishihe 2 engineering and 09 Kinteru layer

Claims (1)

[Claims] 1. A semiconductor wafer made of high oxygen concentration silicon single crystal grown by the Czochralski method is subjected to low-temperature annealing treatment, and then a silicon epitaxial layer is formed on the surface of the semiconductor wafer. A method for manufacturing a semiconductor wafer. 2. A semiconductor device in which a predetermined integrated circuit is formed on a semiconductor wafer obtained by the manufacturing method according to claim 1.