JPS59978B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing bipolar semiconductor integrated circuits, and particularly to ICs such as planar diodes and transistors in which a mask used for impurity diffusion is also used as a passivation film. This provides the most suitable manufacturing method for this application.

Conventionally, SiO2 is used as an impurity diffusion mask when manufacturing this type of semiconductor device, and this 10SiO2 film is left as is on the substrate surface as a surface passivation film.

However, when looking at the characteristics of the device manufactured using this method,
A type of memory effect occurs due to the electric charge present in SiO2, which tends to cause a drop in breakdown voltage.Also, stability against humidity is not good enough for 5 minutes, and changes in leakage current are observed when tested under humid conditions, reducing reliability. It's bad. However, it also has the disadvantage of being susceptible to deterioration if there are fluctuations in electrical bias or temperature. The 20 applicants have filed a patent application No. 49-36175 (Japanese Patent Publication No. 53-25) to develop a semiconductor device with such defects corrected.
No. 52).

According to this, a polycrystalline silicon layer containing oxygen is formed on a semiconductor substrate. This polycrystalline silicon layer (hereinafter simply referred to as poly-Si layer) has a lower resistance than SiO2, so when used as a passivation film, it eliminates the memory effect like SiO2, improving the breakdown voltage and increasing the resistance on the semiconductor substrate surface. It is possible to prevent the reversal phenomenon and reduce leakage current. Furthermore, the present applicant has already proposed 30 patent application No. 123765/1983.
According to JP-A No. 51-49686, a poly-Si layer containing, for example, nitrogen, which has better moisture resistance than SiO2, is formed as a second stabilizing layer on a poly-Si layer containing oxygen. I have to. This makes it possible to particularly improve the moisture resistance. To manufacture a transistor as an example of such a semiconductor device, paste and emitter diffusion are performed using a SiO2 film formed on the surface of a semiconductor substrate as a mask, and then, after removing this SiO2 film, a poly-Si layer containing oxygen is grown by vapor phase growth. The stabilizing layer is then partially etched away to form openings for electrode attachment.

However, this method has the disadvantage of complicating the process, especially when applied to IC manufacturing. The present invention was invented to correct the above-mentioned defects and to provide the features of the above-mentioned Japanese Patent Application No. 49-36175. For example, a semiconductor layer (for example, an N-type epitaxial layer) for providing a transistor, a resistor, etc.) is formed on a semiconductor substrate (for example, a P-type silicon substrate), and the layer reaches from the surface of the semiconductor layer to the semiconductor substrate +. forming an isolation diffusion region (for example, a P-type isolation diffusion region) in the semiconductor layer; and depositing an oxygen-containing polycrystalline silicon layer (poly-Si layer) on the surface of the semiconductor layer;
forming a base region in the isolation region by performing impurity diffusion using the polycrystalline silicon layer as a mask in the isolation region of the semiconductor layer separated by the isolation diffusion region; At the time of formation, an emitter region is formed in the base region by diffusing impurities into the base region using the oxide film formed on the base region as a mask, and these impurity diffusions are performed. The method of manufacturing a semiconductor integrated circuit is characterized in that the polycrystalline silicon layer and the oxide film are left as they are afterwards.

By this method, the manufacturing process of bipolar ICs is extremely simplified, and bipolar ICs with high reliability and good characteristics can be manufactured. Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 show a first embodiment in which the present invention is applied to a bipolar IC.

First, as shown in Figure 1A, 3~5Ω? 111 crystal P
The surface of the mold silicon substrate 1 is thermally oxidized at 1130°C for 30 minutes, and openings 3 and 4 are formed in the thermally oxidized SiO2 layer 2 with a thickness of about 36007C by etching, and N-type silicon is formed through these openings. Impurities (e.g. Sb) are
8=25Ω/mouth, X. =2.0μ to form N+ type semiconductor regions 5 and 6j, respectively.

Next, as shown in FIG. 1B, the SiO layer 2 on the substrate 1 is removed by etching, and then the surface of the substrate 1 is coated with 4 to 7 Ωα.
An N-type epitaxial layer 7 is grown to a thickness of about 10 μm.

Next, as shown in FIG. 1C, an oxygen-containing poly-Si layer 8 is formed on the surface of the N-type epitaxial layer 7 to a thickness of 0.5 μm to 2.0 μm (for example, about 1.0 μm) using an apparatus to be described later. Make it grow.

Although the surface of this poly-Si layer is oxidized in the diffusion process described later, the entire poly-Si layer is not oxidized and the original poly-Si layer remains on the substrate 1 side.
It is desirable that at least 0.1μ (1000λ) remain. In addition, the thickness of the poly-Si layer 8 is set to 2.0 mm in order to prevent the electrode from breaking when forming the electrode in the final process.
It is preferably less than μ. Further, as will be described later, the poly-Si layer 8 has an excellent passivation effect due to the oxygen content, and the oxygen content is preferably 2 to 45 at %, more preferably 15 to 35 at %. Next, as shown in Figure +1D, N-type semiconductor regions 5,
A predetermined portion of the poly-Si layer 8 existing between the openings 910 and 6 is removed by plasma etching or etching with hot phosphoric acid.
Through these openings, a P-type impurity (for example, B) is diffused in the thickness direction at 1240° C. for 150 minutes into the substrate 1, thereby forming p + type isolation diffusion regions 12.
, 13, 14 are formed.

These separate diffusion regions may be integrally connected to each other, each with ρ8=10Ω/port. At the same time as this separation and diffusion, the surface of the poly-Si layer 8 is thinly oxidized to contain SiO2.
2, SiO2 also grows in the openings 9, 10, and 15, so that the poly-Si layer 8 including the substrate 1 is covered with a thin SiO2 layer 11. Also, by separation diffusion, the N+ type semiconductor regions 5 and 6 under the N type epitaxial layer 7 are
The impurities inside diffuse into the low concentration epitaxial layer 7,
Each time N+ type buried regions 16 and 17 are formed between N type epitaxial layer 7 and substrate 1. Then the 1st E
As shown in the figure, predetermined portions of the SiO2 layer 11 and the poly-Si layer 8 on the N-type semiconductor regions 18 and 19 that have been separated and formed by the above-described separation and diffusion are removed by etching to form openings 20 and 2.
form 1. For this etching, the same etching solution can be used for both the SiO2 layer 11 and the poly-Si layer 8. Then, a P-type impurity (for example, B) is diffused at 1100° C. for 100 minutes through the openings 20 and 21, so that the N-type semiconductor region 18, which will become the collector region on the left side, is filled with P-type impurities.
A + type base region 22 and a p + type resistance region 23 are formed in the N type semiconductor region 19 on the right side. These base region 22 and resistance region 23 are each ρ8=250Ω/mouth, Xj
=1.8μ. Due to this diffusion, SiO2 layers 24 and 25 which are continuous to the SiO2 layer 11 grow in the openings 20 and 21, respectively. Next, as shown in FIG. 1F, the SiO2 layer 2
4 and the poly-Si layer 8 and SiO2 on the N-type semiconductor region 18.
Predetermined portions of the layer 11 are etched away to form openings 26 and 2.
7, and conduct N-type impurities (for example, P
) for 35 minutes at 1000°C.

As a result, an N+ type emitter region 28 is formed below the opening 26.
N+ type semiconductor regions 29 for extracting collector electrodes are formed under the openings 27, respectively. Then, as shown in Figure 1G,
The thin SiO2 layer 30 formed during the base diffusion described above,
Predetermined portions of 31 and SiO2 layers 24 and 25 are removed by etching, and emitter electrode 32, base electrode 33, collector electrode 34, and resistor electrodes 35 and 36 are deposited.

As described above, it is possible to manufacture an IC having, for example, an NPN type bipolar transistor and a resistor in each of the N type semiconductor regions 18 and 19 formed by separating the N type epitaxial layer 7.

According to this embodiment, impurity diffusion is performed in each of the N-type semiconductor regions 18 and 19 separated by the isolation diffusion regions 12, 13, and 14 using the poly-Si layer 8 deposited on the surface of the epitaxial layer 7 as a mask. Particularly, the N-type semiconductor region 1
Resistance regions 23 are formed in each of the regions 9 and the poly-Si layer 8 is left as is after impurity diffusion. Therefore, when each diffusion region is formed using SiO2 as a mask and then the poly-Si layer is deposited Compared to this, the number of man-hours is reduced and the manufacturing process can be significantly simplified.

During base diffusion (Fig. 1E), the poly-Si layer 8 acts as a stopper for P-type impurities, and during emitter diffusion (Fig. 1F), the poly-Si layer 8 acts as a stopper for the SiO2 on the surface of the poly-SSi layer 8.
The layer 11 and the SiO2 layer 24 in the opening 20 act as a stopper for N-type impurities. The reason why the poly-Si layer 8 acts as a diffusion mask in this way is that this poly-Si layer can be grown at a low temperature of about 650° C. and its diffusion coefficient becomes small.

That is, the poly-Si layer 8 is formed by the apparatus shown in FIG.
, 39, 40, and 41 are connected, and among these, monosilane (SiH4) is supplied from a gas source 38, nitrogen oxide such as dinitrogen monoxide (N2O) is supplied from a gas source 39, and nitrogen as a carrier gas is supplied from a gas source 41 to the furnace 37. send them to each. Note that the gas source 40 contains ammonia (NH,), which is not used in this embodiment. In operation, the substrate 1 is placed in the furnace 37, and the temperature of the furnace 37 is set to about 65°C using a heater.
It is held at 0° C., which is the decomposition temperature when using SiH4 as the silicon source. When SiH4 and N2O are fed together with the carrier gas from gas sources 38 and 39, they are thermally decomposed to grow poly-Si containing a predetermined amount of oxygen. In this case, the flow rate ratio of SiH4 and N2O may be appropriately selected, but when the flow rate ratio expressed as N2O/SiH4 is approximately %, the oxygen content in the poly-Si layer 8 will be approximately 15 at%. If NO, NO2, etc. are used as an oxygen supply source in addition to N2O, the amount of oxygen Q can be easily controlled. Although the diffusion coefficient of impurity atoms in poly-Si, which does not contain oxygen, is almost the same as that in single-crystal silicon, if even a small amount of oxygen enters, the diffusion coefficient decreases rapidly, making it extremely advantageous as a diffusion mask.

For comparison, poly-Si was subjected to thermal decomposition of SiCl4 (850°C
It is unsuitable to form the film with a large diffusion coefficient because the diffusion coefficient is large. In addition, in this practical example, the separation diffusion regions 12, 13
. Deterioration of the poly-Si layer 8 can be avoided.

Furthermore, since the surface of the poly-Si layer 8 becomes the SiO2 layer 11 during diffusion, interconnections can also be passed through the surface of this SiO2 layer. Furthermore, since the poly-Si layer 8 covers the reverse bias junction between the base region 22 and the collector region 18 and the lightly doped N-type semiconductor regions 18 and 19, the surface passivation effect is very excellent.

That is, when a SiO2 film is used as a passivation film as in the conventional method, a kind of memory effect occurs due to the charges existing in the SiO2, and a channel is formed on the semiconductor regions 18 and 19 side. The electric charge is fixed due to polarization in the resin, and as a result, the withstand voltage at the bonding surface is likely to drop, and the effects of external electric fields and temperature are likely to occur.
However, since the poly-Si layer 8 has a lower resistance than SiO2, the above-mentioned phenomenon does not occur, the withstand voltage is improved, and inversion is prevented, so that it is advantageous for use at a high power supply voltage. Furthermore, since it contains an appropriate amount of oxygen, it has a higher resistance than pure polycrystalline silicon, so no charge transfer occurs through the poly-Si layer 8, and reverse leakage current is extremely reduced.
On the other hand, since the junction between the emitter region 28 and the base region 22 is covered with the SiO2 layer 24, there is no fear that the HFE will be lowered compared to the case where it is covered with oxygen-containing poly-Si. Further, the coefficients of thermal expansion of the poly-Si layer 8 and the epitaxial layer 7 are similar, eliminating poor adhesion due to thermal strain, and combining the above-mentioned factors, the passipation effect is extremely good.

Note that the oxygen content in the poly-Si layer 8 is 2 to 45 at(f).
However, if the amount of oxygen is too small, a leakage current in the opposite direction may occur, and if it is too large, the effect is almost the same as that of SlO2.

Note that this poly-Si preferably has fine crystals, with a grain size of 1000 Å or less (actually 100 to 200 λ).
If this particle size is too large, charges will be trapped and accumulated in the layer, causing a memory phenomenon, and it will be insufficient to obtain a sufficient stabilizing effect. Note that the thickness T1 of the poly-Si layer 8 is 0.1μ=
<T1 is preferably 2.0μ; if it is thinner than 0.1μ, the reverse current characteristics after heat treatment are likely to deteriorate;
．． If it is thicker than 0μ, the problem of breakage of the electrode tends to occur when extending the electrode on the upper surface.

Next, a second embodiment in which the present invention is applied to a high voltage LECIC will be described with reference to FIG. First, as shown in Figure 3A, P
A first N-type epitaxial layer 4 is formed on a type silicon substrate 41.
A SiO2 layer 40 is formed on the surface of this epitaxial layer by thermal oxidation, and P-type impurities are diffused at a high concentration through openings 42, 43, 44, and 45 provided in this SiO2 layer. The N-type epitaxial layer 47 reaches the substrate 41 and is connected to several N-type semiconductor regions 48, 49,
p+ type isolation diffusion regions 51, 5 for isolation into 50, respectively.
2, 53, 54 are formed.

At this time, as described in the first embodiment, the impurities in the N+ type semiconductor region previously formed in the substrate 41 diffuse into the epitaxial layer 47, and the N+ Mold buried regions 55, 56, and 57 are formed, and an SiO2 layer continuous to the SiO2 layer 40 is grown in each opening 42-45. Next, as shown in FIG. 3B, a predetermined portion of the SiO2 layer 40 on the left N-type semiconductor region 48 is etched away to form an opening 46, and a P-type impurity (for example, B) is diffused through this opening to form a p+-type A semiconductor region 58 is formed.

Next, as shown in FIG. 3C, the SiO2 layer 40 on the epitaxial layer 47 is removed by etching, and a second N-type epitaxial layer 6 is formed on the exposed surface of the epitaxial layer 47.
Grow 7.

Next, as shown in FIG. 3D, an N-type epithelial layer 6 is formed.
A SiO2 layer 59 is formed on the surface of the semiconductor substrate 7 by thermal oxidation, and this SiO2 layer is etched to leave a portion corresponding to the emitter of an LEC transistor, which will be described later, and remove the rest.

Next, as shown in FIG. 3E, a poly-Si layer 68 containing a predetermined amount of oxygen is grown to a predetermined thickness on the surface of the epitaxial layer 67 in the same manner as described in the first embodiment.

Next, as shown in FIG. 3F, predetermined portions of the poly-Si layer 68 are etched away to form openings 60, 6162, 63,
64 and 65, and P-type impurity (
For example, B) is diffused until it reaches the epitaxial layer 47.

As a result, the diffusion regions from the openings 60, 63, 64, 65 extend to the upper part of the p+ type isolation diffusion regions 51, 52, 53, 54, and together they form the epitaxial layer 67.
P+ type isolation diffusion region 71 reaching from the surface to the substrate 41
, 72, 73, and 74 are formed, respectively. Also, the opening 61,
The diffusion region from 62 reaches the p + type semiconductor region 58 and becomes one, and the impurity in the p + type semiconductor region 58 also diffuses into the epitaxial layer 67. A lightly doped N1 type semiconductor region, ie, an emitter region 78, is formed surrounded by a p+ type semiconductor region, ie, a base region 82, which is included in the concentration. Further, the N1 type epitaxial layer 67 is formed by the N1 type semiconductor regions 88, 89, 9 by the isolation diffusion regions 71 to 74.
0 respectively. Simultaneously with the above-described separation and diffusion, the surface of the poly-Si layer 68 is oxidized and changed to the SlO2 layer 81, and SiO2 subsequently grows in the openings 60-65. Also, the SiO remaining on the epitaxial layer 67
The surface of the poly-Si layer existing on the second layer 59 is also oxidized, so that the poly-Si layer 75 is just buried by the SlO 2 layer 81 and the SiO 2 layer 59 continuous thereto. Next, as shown in FIG. 3G, the portion of the SiO2 layer 81 existing in the opening 62, the poly-Si layer 68 on the N-type semiconductor region 8990, and the portion of the SiO2 layer 81 are selectively etched using the same etching solution. Remove opening 76
, 77, 79 are formed, and a P-type impurity (for example, B) is diffused through these openings.

As a result, a p+ type semiconductor region 80 with a higher concentration for taking out the base electrode is formed on the upper right side of the base region 82, and a p+ type base region 92 and a p+ type resistance region 93 are formed in the N1 type semiconductor region 8990. At the same time, SiO2 layers 83, 84, and 85, which are connected to the SlO2 layer 81, grow in the openings 76, 77, and 79, respectively. Then the 3rd H
As shown in the figure, the SlO2 layer 81 on the emitter region 78,
59 and the poly-Si layer 75, the SiO2 layer 81 on the N-type semiconductor region 88 on the right side of the base region 82, that is, the collector region 88, the poly-Si layer 68, and the SiO2 on the base region 92.
layer 84, N-type semiconductor region 89 to the right of base region 92;
That is, the SiO2 layer 81 and poly S1 on the collector region 89
Layer 68 is selectively etched away to form openings 86 and 8, respectively.
7, 91, and 94 are formed, respectively.

Then, N type impurities (for example, Sb) are diffused through these openings to form an N+ type emitter region 98, an N+ type semiconductor region 99 for extracting the collector electrode, and an N+ type 1 emitter region 108.
, an N+ type semiconductor region 109 for extracting the collector electrode is formed, respectively. Next, as shown in FIG. 31, the SlO2 layers 95, 96, 97, 98 grown during the emitter diffusion described above are grown.
and the SlO2 layers 83, 84, 85 are selectively etched away, and emitter electrodes 102, 1 are formed in these removed portions.
12, base electrodes 103, 113, collector electrode 104
, 114, and resistor electrodes 105 and 106 are applied, respectively.

As described above, an NPN type LEC transistor having a low concentration emitter region on the left side of the epitaxial growth layer 67 is formed, and a normal NPN type transistor is formed in the middle thereof.
Resistors are respectively formed on the right side thereof.

Also in this embodiment, the separation diffusion regions 71, 72, 73,
By diffusing impurities into each of the N1 type semiconductor regions 8889 and 90 separated by 74 using the poly-Si layer 67 deposited on the surface of the epitaxial layer 67 as a mask, the N1 type semiconductor region 88 is has a base region 82 in it, a base region 92 in the N-type semiconductor region 89, and a base region 92 in the N-type semiconductor region 89;
Resistance regions 93 are formed in each of the type 1 semiconductor regions 90,
Since the poly-Si layer 67 is left as is after this impurity diffusion, the manufacturing process can be significantly simplified as in the first embodiment.

Also, NPN type LEC transistor and normal NPN
It is extremely advantageous in this sense as well, since it is possible to simultaneously form two type transistors. Further, the reverse bias junctions and low concentration regions of the base regions 82, 92 and collector regions 88, 89 are covered with a poly-Si layer 68, and the emitter regions 98, 108, the base regions 82, 89,
Since the respective junctions with 92 are covered with a SiO2 layer, the passivation effect is excellent and effective for high breakdown voltage 1C, and there is no decrease in HFE. Next, the present invention will be applied to a high voltage L
A third embodiment applied to ECIC will be described with reference to FIG.

This embodiment differs from the second embodiment in the formation process of the isolation diffusion region of the second epitaxial layer, and common parts are given common reference numerals and explanations will be omitted.

That is, as shown in FIG. 4A, a second N-type epitaxial layer 67 is first formed by the process shown in FIG. 3C in the second embodiment, and then thermal oxidation is applied to the surface of this epitaxial layer. Thus, a SiO2 layer 119 is formed, and this SiO2 layer 119 is formed.
Opening 1 formed by etching a predetermined portion of the O2 layer
By diffusing P type impurities (for example, B) through 20, 121, 122, 123, 124, 125, p+ type isolation diffusion regions 71, 72, similar to those in the first embodiment are formed.
73, 74 and a p+ type base region 82 are formed.

Next, as shown in FIG. 4B, the SiO2 layer 119 is etched, leaving the SiO2 layer 119 only in the portion that will become the LEC transistor.

Next, as shown in FIG. 4C, a poly-Si layer 68 containing a predetermined amount of oxygen is grown in a vapor phase on the surface of the epitaxial layer 67, and then, as shown in FIG. 4D, a predetermined portion of the poly-Si layer 68 is removed by etching. The opening 126,1 formed by
27, 128 to diffuse a P type impurity (for example, B) to form a highly doped p+ type semiconductor region 80 in the base region 82.
A p+ type base region 92 is formed in the collector region 83, and a p+ type resistance region 93 is further formed in the N1 type semiconductor region 90.

Note that during this diffusion, the surface of the poly-Si layer 68 is oxidized and becomes Si.
It changes into an O2 layer 81. Then, as shown in FIG. 4E, S
The iO2 layers 81, 59 and the poly-Si layer 68 are etched and removed, and an N-type impurity (for example, P) is diffused from the removed portions to form N+-type emitter regions 98, 108, an N+-type semiconductor region 99 for extracting the collector electrode, 109 are formed respectively. And the SiO2 layer 9596,9 grown during diffusion
7, 98 and the SlO2 layers 83, 84, 85 are selectively etched away, respectively, and the previously described electrodes are deposited. According to this embodiment, the poly-Si layer 68 is not used as a mask when forming the isolation diffusion regions 71 and 74.
The heat generated during this diffusion does not have an adverse effect on the poly-Si.

Although the present invention has been described above based on examples, it will be understood that the present invention is not limited to these examples and can be further modified based on the technical idea thereof.

For example, to prevent the poly-Si layers 8, 68 from being completely oxidized by the diffusion process, a three-layer structure of poly-Si layers may be deposited before the diffusion.

That is, a poly-Si layer with a thickness of 5,000 yen containing oxygen is formed as a first layer in direct contact with the epitaxial layers 7 and 67, and a poly-Si layer with a thickness of 10 yen thick containing nitrogen is formed on this poly-Si layer as a second layer.
A poly-Si layer having a thickness of 1000 A0 and containing oxygen is formed as a third layer on this poly-Si layer. In this case, even if the entire top poly-Si layer is oxidized, there is no problem because the intermediate nitrogen-containing poly-Si layer is difficult to oxidize, and the presence of this intermediate layer can particularly improve moisture resistance. Proven by processing tests. To form this nitrogen-containing poly-Si layer, the supply of N2O from the gas source 39 shown in FIG.
is approximately 100/30. This nitrogen content is 10at%
The above is preferable; if the amount of nitrogen is too small, discharge is likely to occur between the electrodes through the surface of the poly layer, and the poly layer becomes similar to pure poly Si, resulting in poor moisture resistance. It is good for large amounts of nitrogen, and can be used until the proportion is almost Si3N4. In the above embodiment, the outer surface of the poly-Si layer is covered with an oxide film (SiO2), so when electrodes and external leads are provided on this layer, stability and reliability are improved, especially for high voltage resistance. can be achieved.

As described above, the present invention includes the following steps in manufacturing a bipolar IC:
A base region is formed in the isolation region by performing impurity diffusion using the oxygen-containing polycrystalline silicon layer as a mask in the isolation region separated by the isolation diffusion region, and after this impurity diffusion, the polycrystalline silicon layer is Since the silicon layer is left as is, the number of silicon layers is reduced compared to the case where the base region is formed using an oxide film as a mask, and then the oxide film is removed and the polycrystalline silicon layer is deposited. In addition, the manufacturing process can be significantly simplified, and the reverse bias junction between the base region and the collector region can be covered with the polycrystalline silicon layer, which has an extremely good surface passivation effect, thus making the semiconductor highly reliable. Integrated circuits can be manufactured.

Further, when forming the base region, an emitter region is formed in the base region by diffusing impurities into the base region using the oxide film formed on the base region as a mask, and after this impurity diffusion, the oxide film is Since the junction between the emitter region and the base region is left as is, it is possible to cover the junction between the emitter region and the base region with an oxide film, which prevents the HFE from decreasing compared to the case where it is covered with a polycrystalline silicon layer containing oxygen. be able to.

[Brief explanation of drawings]

The drawings show embodiments of the present invention, and include Figures 1A to 1A.
FIG. 1G is a sectional view showing step by step the manufacturing method according to the first embodiment in which the present invention is applied to a bibolar IC, FIG. 2 is a schematic diagram of an apparatus used for vapor phase growth of poly-Si, and FIGS. 3A to 3
Figure 1 is a cross-sectional view showing the manufacturing method according to the second embodiment in which the present invention is applied to a LECIC, and Figures 4A to 4E are sectional views showing the manufacturing method according to the third embodiment in which the present invention is applied to a high voltage LECIC. FIG. 3 is a cross-sectional view showing the method in the order of steps. In addition, in the symbols used in the drawings, 7 and 47 are N
type epitaxial layer, 8, 68, 75 are poly-Si layers, 1
1, 81 are SiO2 layers, 12, 13, 14, 51, 52
, 53, 54, 71, 72, 7374 are P+ type isolation diffusion regions, 22, 82, 92 are base regions, 23, 93 are resistance regions, 28, 78, 98, 108 are emitter regions, 6
7 is an N-type epitaxial layer.

Claims (1)

[Claims] 1. In manufacturing a bipolar type semiconductor integrated circuit, there is a step of forming a semiconductor layer on a semiconductor substrate for providing a plurality of semiconductor elements, and a step of forming an isolation diffusion region extending from the surface of the semiconductor layer to the semiconductor substrate. depositing an oxygen-containing polycrystalline silicon layer on the surface of the semiconductor layer; forming a base region in the isolation region by diffusing impurities using a silicon layer as a mask; and diffusing impurities into the base region using an oxide film formed on the base region at the time of forming the base region as a mask. forming an emitter region in the base region by performing diffusion, and the polycrystalline silicon layer and the oxide film are left as they are after the impurity diffusion. A method for manufacturing semiconductor integrated circuits.