JPS59186366A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59186366A JPS59186366A JP6014383A JP6014383A JPS59186366A JP S59186366 A JPS59186366 A JP S59186366A JP 6014383 A JP6014383 A JP 6014383A JP 6014383 A JP6014383 A JP 6014383A JP S59186366 A JPS59186366 A JP S59186366A
- Authority
- JP
- Japan
- Prior art keywords
- base
- film
- region
- type
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000009826 distribution Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 66
- 241000238557 Decapoda Species 0.000 description 30
- 238000009792 diffusion process Methods 0.000 description 9
- 238000000605 extraction Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012528 membrane Substances 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路（以下ＬＳＩという）特に高
速度はＬＳＩとその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor integrated circuits (hereinafter referred to as LSIs), particularly high-speed LSIs, and methods of manufacturing the same.
従来例の構成とその問題点
半導体装置は最近ますます高速化され、従来からの拡散
によって形成されるベーヌ厚与は０３ミクロンを切ろう
としている。しかし、より高速に動作させるためには、
（１）ベース層の厚みを０．１ミクロノ以−１置でする
。（２）ベース層の引き高し電極ノＭ−（抗７＞： 低
い。（３）エミッタ、ベース、コレクタ各層の不純物か
で＾度よく制御できる。の三条性を満ノ」杏する必要が
ある。Conventional Structures and Problems Semiconductor devices have recently become faster and faster, and the Beine thickness formed by conventional diffusion is about to fall below 0.3 microns. However, to make it work faster,
(1) The thickness of the base layer is 0.1 micron or less. (2) The height of the base layer electrode M- (resistance 7>) is low. (3) It can be well controlled by impurities in the emitter, base, and collector layers. be.
第１図にこうしたことを考慮した従来の縦型バイポーラ
トランジスクの断面１１４造を示した。ｎ１１Ｊ Ｓ
ｉ （シリコン）基板１の上に基板と同一型の不純物を
Ｊｉ’ｊつエピタキシャル成長したエビ膜３を形成し、
そのエビ膜３の不用な部分を酸化して酸化膜２を形成す
る。このエビ膜３と酸化膜２の」二にさらに不純物の異
なるエビ膜４を形成する１、エビ膜４は、形成した下地
が単結晶であるときにのみエピタキシャル成長し、下地
がガラス層や多結晶の場合には成畏した膜は多結晶とな
る。ベース層として用いるエビ膜４と同時に形成した多
結晶膜（ポリシリコン）６をベース電極取り出し７部分
を除いて酸化し、酸化膜５を形成する３３以上の）ＩＩ
ｌ′１ａの上にさらにエビ膜を形成し、エミッタ了とべ
一ヌ電極取出し部８を形成し、他の部分は酸化膜９とす
る。エミッタγにはｎ型のイオンが注入され、ベース層
４との間に接合を作る。寸だ、電極取出し部８にはＰ５
のイオンを注入する。Figure 1 shows a 114-section cross-section of a conventional vertical bipolar transistor with these considerations in mind. n11JS
Forming a shrimp film 3 on a (silicon) substrate 1 by epitaxially growing impurities of the same type as the substrate,
An oxide film 2 is formed by oxidizing unnecessary parts of the shrimp film 3. A shrimp film 4 with different impurities is formed on top of the shrimp film 3 and the oxide film 2.The shrimp film 4 grows epitaxially only when the base formed is a single crystal, and the base is a glass layer or polycrystalline. In this case, the resulting film becomes polycrystalline. The polycrystalline film (polysilicon) 6 formed at the same time as the shrimp film 4 used as a base layer is oxidized except for the base electrode extraction 7 part to form an oxide film 5 (33 or more) II
A shrimp film is further formed on l'1a, and an electrode extraction portion 8 is formed between the emitter and the base, and an oxide film 9 is formed on the other portions. N-type ions are implanted into the emitter γ to form a junction with the base layer 4. P5 on the electrode extraction part 8.
ions are implanted.
このようにして形成した半導体装置の製造方法は、従来
から用いられているＣｖＤ＋熱放散、熱酸化等の高温度
による処理を伴っているため、高温（９５０〜１２５０
℃）Ｋ達するたび毎に、各層の不純物濃度が拡散を起こ
して再分布し、（３）にあげた各層の不純物濃度を精度
よく制御できないため、ｌ−ランシスタ特性が不安定と
なシ、寸た、ベース層の厚みを０．１ミクロン以下にす
ることが困難であった。また、ベース層の引き出し電極
がベース層の厚みと等しい構造であるため、べ一ヌ層の
厚みが薄くなるとべ一ヌの延長部分のポリシリコンロの
抵抗が高くなシ高速動作ができなかった。The method for manufacturing semiconductor devices formed in this manner involves high-temperature treatments such as conventionally used CvD + heat dissipation and thermal oxidation.
°C) Every time K is reached, the impurity concentration in each layer causes diffusion and redistribution, and as the impurity concentration in each layer mentioned in (3) cannot be precisely controlled, the l-run transistor characteristics become unstable. In addition, it was difficult to reduce the thickness of the base layer to 0.1 micron or less. In addition, since the lead electrode of the base layer has a structure that is equal to the thickness of the base layer, when the thickness of the base layer becomes thinner, the resistance of the polysilicon layer in the extension part of the base increases, making high-speed operation impossible. .
発明の目的
本発明はこのような従来からの問題点に鑑み、ベースの
取９出し電極の構造を改善すること、おＥびベース層の
不純分布を改善することによって高速でかつ安定性のよ
い半導体装置を提供することを目的としている。Purpose of the Invention In view of these conventional problems, the present invention provides a high-speed and stable method by improving the structure of the lead electrode of the base and improving the impurity distribution of the E and base layer. The purpose is to provide semiconductor devices.
発明の構成
本発明はコレクタのエビ層をたとえば２層とし、このう
ちベースに近接したエビ層の一部分をベース引き出し′
上極の補助として利用して引き出し電体部分の抵抗を］
：げるとともに、ベース形成にたとえは低温膜形成法を
応用することによって、不純物か円分布しない工程を採
用し、高速で安定性のよいｌ′４ Ｋ ％ ｔｉ召を提
供するものである。Structure of the Invention In the present invention, the collector has two shrimp layers, for example, and a part of the shrimp layer near the base is pulled out from the base.
Use it as an auxiliary for the upper electrode to reduce the resistance of the lead-out electrical part]
In addition, by applying a low-temperature film formation method to the base formation, a process that does not have a circular distribution of impurities is adopted, and a high-speed and stable l'4 K% ti conversion is provided.
実施例の説明
第２１”’ｌは、本発明の第１の実施例の半導体装置の
断面図を示し／ｃｏｎ型８１型板１基板１１基板と同一
・の不純物を持つｎ型単結晶コレクタ領域となるエビ膜
１３と１６、異種のＰ型不純物を持ち単結晶べ〜ス領域
を形成するエビ膜１８、ｎ型の高イ純物濃度をもち単結
晶エミッタ領域を形成する」エビ膜２０を各・ン順４に
形成し、エビ膜１５と同時に形成した多結晶Ｓｉ膜１７
とベースのエビ膜１８と同［１７Ｊに形成した多結晶Ｓ
ｉ膜１９０２層の多結晶Ｓｉ膜をベースの取り出し電極
とする。べ−ヌの取り出し電極はさらにエミッタを形成
するエビ膜２ｏと同時に形成した多結晶Ｓｉ膜２２によ
ってベースを外部回路と接続する構造である。DESCRIPTION OF THE EMBODIMENTS No. 21'''l shows a cross-sectional view of a semiconductor device according to the first embodiment of the present invention /con type 81 type plate 1 substrate 11 n type single crystal collector region having the same impurity as the substrate shrimp films 13 and 16, which have different types of P-type impurities and form a single-crystal base region, and shrimp film 20, which has a high n-type impurity concentration and forms a single-crystal emitter region. Polycrystalline Si film 17 formed simultaneously with shrimp film 15
and the polycrystalline S formed on the base shrimp membrane 18 [17J]
The polycrystalline Si film of the i-film 1902 layer is used as a base extraction electrode. The extraction electrode of the bene has a structure in which the base is further connected to an external circuit by a polycrystalline Si film 22 formed at the same time as the shrimp film 2o forming the emitter.
第４図に、第１の実施例のトランシヌタを実現するだめ
の製造工程を示した。工程順に説明する。FIG. 4 shows the manufacturing process for realizing the transinuta of the first embodiment. The steps will be explained in order.
第４図ａではＳｉ基板１１上にＳｉＯ２膜１２全１２し
、一部分をエツチングした後ＳｉＯ２膜１２の膜厚とほ
ぼ等しい膜厚のエピタキシャル成長したエビ膜１３を形
成する。エビ膜１３中の不純物は、基板にドープされて
いる不純物と同一型（この例ではｎ型）のものである。In FIG. 4a, the entire SiO2 film 12 is deposited on the Si substrate 11, and after a portion is etched, an epitaxially grown shrimp film 13 having a thickness substantially equal to that of the SiO2 film 12 is formed. The impurities in the shrimp film 13 are of the same type as the impurities doped into the substrate (in this example, n-type).
第４図すの工程では、エビ膜１３に隣接しだＳｉＯ２膜
１２全１２、Ｐ型不純物を而し、不純物拡散源となる酸
化膜１４を適当な形状に加工し、つづいてエビ膜１５を
形成する。エビ膜１５は全面を覆うように形成し、酸化
膜１４に隣接した部分とエビ膜１３上の単結晶膜部分で
あるエビ膜１５０部分を除いて酸化し、酸化膜１６を形
成する。酸化膜１６を形成する際、ウェハは高温に加熱
され、不純物拡散源の酸化膜１４から不純物が多結晶Ｓ
１膜１７に拡散し、 コレクタと異る型のベース電極引
出しの不純層（この場合はＰ型）が得られる（第４図ｂ
）。In the step shown in FIG. 4, the whole SiO2 film 12 adjacent to the shrimp film 13 and the oxide film 14 that contains P-type impurities and serves as an impurity diffusion source are processed into an appropriate shape, and then the shrimp film 15 is formed. Form. The shrimp film 15 is formed to cover the entire surface, and is oxidized except for the portion adjacent to the oxide film 14 and the shrimp film 150 portion, which is a single crystal film portion on the shrimp film 13, to form an oxide film 16. When forming the oxide film 16, the wafer is heated to a high temperature, and impurities are removed from the oxide film 14, which is an impurity diffusion source, into polycrystalline S.
1 film 17, and an impurity layer (in this case P type) for leading out the base electrode of a type different from that of the collector is obtained (Fig. 4b).
).
次に、エビ膜１３．１５からなるコレクタの上に不純物
の型の異なるＰ型のＳｉエピ膜１８を光ＣＶＤ法や分子
線エビクキシーすなわちＭｏ１ｅｃｕｌａｒ Ｂｅａｍ
Ｅｐｉｔａｘｙ （Ｍ Ｂ Ｅ）等の方法音用いて
形成する。このときのエピタキシャル成Ｊ是１’ｒｌｉ
’１度は３００〜７００°Ｃ程度の低温であシ、不純物
の分布状、四はエピタキシャルＳ１膜成長時に変化しな
いのでエビ膜１８の膜厚を１０００Å以下としてもｐ
４（υの膜厚が維持される。このとき、多結晶Ｓ１膜１
７．酸化１１Ｆ１６上には多結晶Ｓ１膜が形成さｉ−す
る。このエビ膜１８と取出し電（「υ〕となる多結晶５
ｊｌｌｐ１９０部分を残してエツチングし、さらに、仝
而に光ＣｖＤやＭＢＥ等の低温膜形成、ノＪ″法を用い
でＳｉエピ膜２０および多結晶Ｓ１膜２４を形成する。Next, a P-type Si epitaxial film 18 with different impurity types is deposited on the collector consisting of the shrimp film 13, 15 using a photo-CVD method or a molecular beam
It is formed using a method such as Epitaxy (MBE). The epitaxial formation J at this time is 1'rli
'1 degree is a low temperature of about 300 to 700 degrees Celsius, and the distribution of impurities does not change during the growth of the epitaxial S1 film, so even if the thickness of the shrimp film 18 is less than 1000 Å, the p
The film thickness of 4(υ is maintained. At this time, the polycrystalline S1 film 1
7. A polycrystalline S1 film is formed on the oxidized 11F16. This shrimp membrane 18 and the polycrystalline 5 which becomes the extraction voltage ("υ")
Then, a Si epitaxial film 20 and a polycrystalline S1 film 24 are formed using low-temperature film formation such as optical CvD or MBE, or a J'' method.
エビ膜２０は、コレクタと１７１１しｎ型の不純物を高
濃度に含むエミツタとなる膜であり、多結晶Ｓｉ膜１９
上で接合を形成するので、エビ膜２５を除いた部分の多
結晶Ｓ１膜２４上をイオン注入（ｉ／ｉ）によってＰ型
に変化させる。The shrimp film 20 is a film that serves as a collector and an emitter containing a high concentration of n-type impurities, and the polycrystalline Si film 19
Since a junction is formed above, the portion of the polycrystalline S1 film 24 excluding the shrimp film 25 is changed to P type by ion implantation (i/i).
２５はレシヌトであシ、エビ膜２０をイオン注入から保
護している。（第４図Ｃ）
さらに、レジスＩ・２６を塗布し電極２４とエビ膜２０
を除いた部分をエツチングして除去する。Reference numeral 25 is resin, which protects the shrimp membrane 20 from ion implantation. (Fig. 4C) Furthermore, resist I-26 is applied to the electrode 24 and shrimp membrane 20.
Remove the remaining part by etching.
（第４図ｄ） レジスタ２５．２６を除去Ｌ、プラズマｃＶＤ。(Figure 4d) Remove resistor 25.26 L, plasma cVD.
光ＣＶ Ｄ、 Ｍｏ１ｅｃｕｌａｒ Ｂｅａｍ Ｄｅ
ｐｏｓｉｔｉｏｎ等の低温薄膜形成方法によって８１０
２膜２１を形成し、必要な電極部をエツチング除去して
、第２図に示す半導体装置が形成される。Optical CV D, Molecular Beam De
810 by a low temperature thin film forming method such as position
A semiconductor device shown in FIG. 2 is formed by forming two films 21 and removing necessary electrode portions by etching.
第３図は、本発明による第２の実施例の半導体装置であ
り、第１の実施例との相異点（・」、第４しく１ａの工
程後、第１の実施例では不純物拡散源の酸化膜１４を形
成して不純物を多結晶５１１７に拡１１りするのに列し
て、第２の実施例では、不純物拡１１々源２３を酸化膜
１２中にイオン注入又は拡散によって設け、不純物を多
結晶Ｓｉ １γ中に拡散する。FIG. 3 shows a semiconductor device according to a second embodiment of the present invention, which differs from the first embodiment (・). In addition to forming the oxide film 14 and diffusing impurities into the polycrystal 5117, in the second embodiment, an impurity diffusion source 23 is provided in the oxide film 12 by ion implantation or diffusion. Impurities are diffused into polycrystalline Si 1γ.
この例では、第２図と第３図との比較より明らかなよう
に、酸化膜１４が取り除け、断差がなくなるため、ベー
ス層１８とベースからの引き出し電］゛１ｖとなるＳ１
膜１９との間に断線による不良かなくなることである。In this example, as is clear from the comparison between FIG. 2 and FIG.
This means that there will be no defects due to disconnection between the film 19 and the film 19.
発明の効果
以」二のように、本発明はベースの引き出し電極１１１
（分に接してベースと同じ型の半導体領域を設け、カッ
、ベース、エミツタおよび酸化膜の形成を光ＣＶＤやＭ
ＢＨなどの低湿膜形成法により行なうので、ベース中の
不純物分布は、エビ膜形成時にドープさ）１だ不純物分
布を保ち、極めて薄いべ一ヌを持ちかつベース引き出し
抵抗の小さい、高速１９動作の＋−，ｉＪ’能な１−ラ
ンシヌタを実現し、かつ、たとえは酸化膜の一部分に不
純物拡散源を設けることにより、平坦な構造の１−ラン
ジスタが実現でき、歩留りの高い素子を提供できる。Effects of the Invention As described in ``2'', the present invention provides the extraction electrode 111 of the base.
(A semiconductor region of the same type as the base is provided in contact with the base, and the formation of the base, emitter, and oxide film is performed using photo-CVD or M
Since this is done using a low-humidity film formation method such as BH, the impurity distribution in the base is maintained at the same level as the impurity distribution (doped during the formation of the shrimp film), and has an extremely thin base and low base extraction resistance. +-, iJ', and by providing an impurity diffusion source in a portion of the oxide film, it is possible to realize a 1-ran transistor with a flat structure and provide a device with a high yield.
第１図は従来例の１−ランシスタの描造断面Ｉン１、第
２図、第３図は本発明の第１．第２の実施例の１−ラン
シスクの断面図、第４図（ａ）〜に）は第１の実施例の
トランジスタの製造工程断面図である。
１１・・・・・８１基板、１３．ｉ５ ・ コレクタ
領域となるエビ膜、１８・・・ベース領域、１４不純物
拡散源酸化膜、１７．１９ ベース引き出し電極多
結晶膜、２３・・・・・不純物拡散源。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
１
第３図FIG. 1 shows a drawn cross-section of a conventional 1-run transistor, and FIGS. The 1-Ransis sectional view of the second embodiment (FIGS. 4(a) to 4) is a sectional view of the manufacturing process of the transistor of the first embodiment. 11...81 board, 13. i5 - shrimp film serving as collector region, 18... base region, 14 impurity diffusion source oxide film, 17.19 base extraction electrode polycrystalline film, 23... impurity diffusion source. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 1 Figure 3
Claims (4)
もに、前記ベースから引き出しだ前記ベースと同一・導
′１シ型の第１の半導体領域と、この第１の半導体領域
の少くとも一方の主面上に前記ベースと同一導電型の第
２の半導体領域とを有し、ｎ１１記第１および第２の半
導体領域を前記ベースの′１（ヱ（が引出し領域として
なる半導体装；査。(1) A collector, a base, and an eminog are stacked, and a first semiconductor region of the same conductive type as the base is drawn out from the base, and at least one main semiconductor region of the first semiconductor region is formed. A semiconductor device having a second semiconductor region of the same conductivity type as the base on a surface, and the first and second semiconductor regions n11 being the lead-out regions of the base.
第１の非単結晶半導体領域を形成し、前記コレクタ領域
上に他方の導電型の単結晶ベース領域を、前記第１の非
単結晶半導体領域上に前記ベース領域に接して他力の導
電型の第２の非単結晶半導体領域を形成する工程と、前
記ベース領域」二に一方導電型のエミノグ領域を形成す
る工程とをイ〕し、前記第１．第２の非単結晶半導体領
域をベース電極引出し領域とすることを特徴とする半導
体装置の製造方法。(2) forming a collector region of one conductivity type and a first non-single-crystal semiconductor region of the other conductivity type, and forming a single-crystal base region of the other conductivity type on the collector region; forming a second non-single-crystalline semiconductor region of a different conductivity type on the single-crystal semiconductor region in contact with the base region; and forming an eminog region of one conductivity type in the base region. B] and the above-mentioned 1. A method for manufacturing a semiconductor device, characterized in that a second non-single crystal semiconductor region is used as a base electrode lead-out region.
物源上に形成することを特徴とする特許請求の範囲第１
項に記載の半導体装置の製造方法。(3) The first non-single crystal semiconductor region is formed on an impurity source of the other conductivity type.
A method for manufacturing a semiconductor device according to paragraph 1.
成方法にて行うことを特徴とする特許請求の範囲第３項
に記載の半導体温度の別命方法、っ（５）低温薄膜形成
方法が、光ＧＶＤ法又は分子線エピタキシー法よりなる
ことを特徴とする特許請求の範囲第４項に記載の半導体
装置の製造方法。(4) A method for forming a semiconductor temperature according to claim 3, characterized in that the base region is formed by a low-temperature thin film forming method at 700'C or less; (5) a low-temperature thin film forming method; 5. The method of manufacturing a semiconductor device according to claim 4, wherein the method is a photoGVD method or a molecular beam epitaxy method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6014383A JPS59186366A (en) | 1983-04-06 | 1983-04-06 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6014383A JPS59186366A (en) | 1983-04-06 | 1983-04-06 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59186366A true JPS59186366A (en) | 1984-10-23 |
Family
ID=13133623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6014383A Pending JPS59186366A (en) | 1983-04-06 | 1983-04-06 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59186366A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63208272A (en) * | 1987-02-24 | 1988-08-29 | Nec Corp | Manufacture of semiconductor element |
| JPS63239982A (en) * | 1987-03-27 | 1988-10-05 | Fujitsu Ltd | Manufacture of bipolar semiconductor device |
-
1983
- 1983-04-06 JP JP6014383A patent/JPS59186366A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63208272A (en) * | 1987-02-24 | 1988-08-29 | Nec Corp | Manufacture of semiconductor element |
| JPS63239982A (en) * | 1987-03-27 | 1988-10-05 | Fujitsu Ltd | Manufacture of bipolar semiconductor device |
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