JPS5828731B2 - All silicon materials available. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of making a thin layer of silicon and a method of making a thin layer of silicon on a substrate material, and more particularly to an insulating substrate such as a polycrystalline substrate. Alternatively, it relates to a method of forming such a thin layer of silicon on an insulating substrate, such as a semiconductor covered with an oxide film.

It has long been known that it is desirable to create a thin layer of silicon on a dielectric substrate to improve electrical isolation between electrical components on the substrate and for other desirable reasons.

In the prior art, this has been accomplished using the well-known silicon-on-sapphire process, which involves depositing silicon on a sapphire substrate.

This type of device suffers from deterioration in quality due to the difference in crystal structure between silicon and sapphire.

Furthermore, this method was expensive because the sapphire substrate was expensive.

The above is also accomplished in conventional technology by growing a thin epitaxial silicon layer on a single-crystal silicon substrate, then forming oxide and polycrystalline silicon on the epitaxial layer, and then polishing and removing the original substrate. You can also do it by doing the following: 1. =.

The problem with this method is that it is difficult to obtain a clean, damage-free surface of the thin silicon layer after the polishing operation because of the polishing damage.

In accordance with the present invention, a method is provided for creating a thin layer of silicon on a dielectric or insulating substrate, and the resulting silicon layer has superior quality properties than silicon-on-sapphire. Furthermore, the surface of the final silicon layer is relatively undamaged and can be readily manipulated to form semiconductor devices.

Briefly, the above is accomplished by depositing a thin n- epitaxial layer on a p+ substrate according to a first embodiment.

Next, silicon oxide is deposited on the n layer, and then polycrystalline silicon is grown on this oxide layer.

The p++ layer is then removed using an etchant that etches only the p10 layer and stops at the junction between the p+1 layer and the n layer.

In this way, a semiconductor device can be fabricated in one layer using known fabrication methods, and another silicon oxide layer can be formed on the next layer or on other layers deposited on top of the previous fabrication process. can be formed.

Holes are drilled in this silicon oxide such that a subsequent directionally dependent etch (ODE) can be used to etch down to the junction between the n-layer and the underlying silicon dioxide.

Additional silicon oxide in the newly etched areas serves as electrical insulation.

According to a second embodiment of the invention, a thin n-epitaxial layer is deposited on a P10 substrate with a (110) crystal orientation.

Next, silicon oxide is formed on this epitaxial layer, and an opening is formed in the oxide layer, the size of which is etched to a position slightly above the junction of the n1 layer and the p+10 layer by the following direction-dependent etching. is now available.

Another layer of silicon oxide is then formed within the etched layer, and polycrystalline silicon is formed over the entire silicon oxide layer.

Next, the p110 region is removed using an etchant that etches only the p+10 layer and stops etching at the junction between it and the n layer.

In this way, the n-regions are electrically isolated from other n-regions by silicon oxide dielectric insulation.

Semiconductor devices can then be fabricated in the n-region according to standard known methods.

Therefore, it is an object of the present invention to use two adjacent layers of different conductivity types, where one has a low resistivity and the other has a high resistivity above a preselected value. The object is to obtain an etching method that proceeds and stops in a high resistivity region.

Another object of the invention is to use a matrix material of low resistivity and deposit thereon a layer of opposite conductivity type and with a resistivity greater than a preselected value to form a compensated intrinsic boundary layer. It is also an object to provide a method for forming thin layers of silicon on a dielectric substrate in which a diffusion potential or an electric field is created, each of which increases the steepness of the etch stop.

After forming an oxide layer and polycrystalline silicon on top of the high resistivity layer,
The original substrate is removed by a concentration-dependent etchant.

Yet another object of the invention is that one layer is of one conductivity type and the other is of the opposite conductivity type and has a higher resistivity than the first layer, the resistivity being greater than a preselected value. The purpose of the present invention is to stop etching at a junction position between two semiconductor layers such as the one shown in FIG.

The above objects and other objects of the invention will become readily apparent to those skilled in the art upon consideration of the following preferred embodiments.

The following examples are given by way of example only and are not intended to limit the invention.

Referring to FIG. 1A, a p+10 substrate 1 serving as a base material has an n~ region 3 epitaxially attached thereon.

It should be noted that although the preferred embodiment deals only with the case of p+10 and n single layer, the present invention is equally effective for the case where the P region is epitaxially grown on the n10 region for the first time. I'll keep it.

It is further noted that layer 3 need not be applied by chemical vapor deposition (it may be formed by any well-known method).

p10 area 1 preferably has a thickness of 250μ and 300μ from the door.
m, but the thickness does not have to be this.

Preferably, this thickness is as thin as possible to minimize the amount of silicon to be etched in the following etching step.

Region 1 is preferably 0.010 ohm -Cm or less, preferably 0.005 to 0.007 ohm -cr
The resistivity is in the range n.

For example, the epitaxial layer 3 is approximately 2.5 microns thick and has a resistivity of at least 0.1 ohm-cm.

The resistivity of region 3 is at least an order of magnitude greater than that of region 1.

The resistivity of region 3 cannot be of any value since it needs to act as an etch stop, as discussed in detail below.

That is, region 3 is approximately 1.5 X if it is P-type.
1 o19/, the impurity concentration must be below,
In addition, if it is an n-type, the impurity concentration must be approximately 7×10 18 /i or less.

Next, as shown in FIG. 1B, a silicon dioxide layer 5 is formed on the layer 3, and on this silicon dioxide layer 5 a polycrystalline layer 7 is formed as shown in FIG. 1C. .

Region 1 is then etched away using an etchant preferably consisting of 1 part by weight of hydrofluoric acid, 3 parts by weight of nitric acid, and 8 to 12 parts by weight of acetic acid.

Region 1 is completely removed by this etchant.

This etch action automatically stops when the junction between regions 1 and 3 is reached.

Another method is to extract region 1 from the junction of regions 1 and 3 by approximately 75
The method is to remove by mechanical polishing or other methods down to a micrometer, and then remove the remaining portion of region 1 using the above-mentioned etching solution.

Polishing must be stopped approximately 75 μm from the junction of regions 1 and 3.

It means that polishing is approximately 25μm to 75μm from the polishing area.
This is because it will cause damage to the previous area as well.

The etched structure is shown in the ilD diagram.

If you do this, there are several directions in which you can proceed.

As can be seen from FIG. 1D, a semiconductor device 9 fabricated on the surface is shown.

It is created by conventional masking and diffusion steps, both of which are necessary to form transistors, and other types of devices may also be formed in this manner.

The semiconductor device is then electrically isolated by forming a silicon dioxide layer or other suitable layer 11 on the layer 30 surface.

A hole is then formed in layer 11, which is in the thickness of layer 3 by a directionally-dependent etch to form a groove 13 that reaches the junction of layers 3 and 5, whereby the first
As shown in Figure E, adjacent semiconductor devices formed in layer 3 are separated.

Another silicon dioxide layer 15 is then formed in groove 13 to provide additional isolation between the electrical components as shown in FIG. 1F.

The appropriate electrodes are then attached using standard processing steps to complete the device.

As is clear from the structure shown in Figure 1D, groove 13
may be formed prior to the formation of the semiconductor device 9.

After the formation of the oxide, the oxide layer 11 is removed and the oxide is deposited into the groove formed by the directionally dependent etch, followed by the formation of the semiconductor device.

Furthermore, the substrate 1 may have essentially any crystal axis direction.

For example, when using a directionally dependent etch, region 1 is
In order to obtain the rectangular grooves 13, it is sufficient to have (ioo) crystal orientation.

Rectangular grooves are formed using the (110) crystal orientation.

Now referring to FIGS. 2A to 2D, the second embodiment of the present invention
Examples are shown.

According to the second embodiment, the base material P10 substrate 21 is (1
00) crystal axis direction, and an epitaxial n layer 23 is formed thereon.

A silicon dioxide layer 25 is then formed over layer 23.

A hole is then drilled in layer 25, which is the thickness of layer 23, such that the following directionally dependent etch will stop at or slightly above the junction of layers 21 and 23.

If the etching stops just above the bond, a small amount of layer 23 must be polished or otherwise removed in a subsequent step to the point where the etching stops.

Groove 2 is created by direction-dependent etching as shown in Figure 2B.
7 is formed.

On the upper surface of the structure of FIG. 2B and into groove 27, No. 2C
Another silicon dioxide layer 29 is formed as shown.

A polycrystalline silicon layer 31 is then formed over layer 29, again as shown in FIG. 2C.

Layer 29 serves for electrical isolation in the same manner as described with respect to the embodiment of FIG.

Region 21 is then removed using the same etchant described with respect to the embodiment of FIG. 1 in a similar manner.

This provides a plurality of electrically isolated regions in layer 23 as shown in FIG. 2D.

A semiconductor device such as a transistor having an emitter region 33 and a base region 35 is shown in FIG. 2D.
It can be formed using normal masking and mounting processes.

Such processes are well known to those skilled in the art and will not be described in detail here.

The first step in obtaining a completed usable semiconductor device is
It is clear that electrodes must be routed to each region of the semiconductor device formed in both the embodiments of FIG. 2 and FIG.

Although the invention has been described with respect to specific preferred embodiments,
Various variations and modifications will be readily apparent to those skilled in the art.

Accordingly, the scope of the claims should be interpreted as broadly as possible in light of the prior art to include all such modifications and variations.

[Brief explanation of the drawing]

Figures 1A-1F illustrate a series of steps for forming a thin layer of silicon on a dielectric substrate, with subsequent steps for forming electrical devices therein, in accordance with a first embodiment of the present invention; There is. Figures 2A-2D illustrate a second method of forming a thin layer of silicon on a dielectric substrate along with steps for forming semiconductor devices on or in the substrate. (Reference number), 1...P+10 board, 3...
...N region, 5...Silicon dioxide layer, 7...
...Polycrystalline layer, 9-°---semiconductor device, 1
1... Silicon dioxide layer, 13... Groove, 15... Silicon oxide layer, 21...
・P+10 substrate, 23...n- region, 25...
...Silicon dioxide layer, 27... Groove, 29
. . . Silicon dioxide layer, 31 . . . Polycrystalline silicon layer, 33 . . . Emitter region, 35.
...Base area.

Claims (1)

[Scope of Claims] 1. A method of forming a thin silicon layer on an insulating substrate, comprising: (a) a first layer of one conductivity type and a first layer of the opposite conductivity type;
(b) a first oxide layer on said second layer; (C) forming a polycrystalline silicon layer on the first oxide layer; (d) forming the first layer with 1 part by weight of (e) removing the first layer by automatically stopping the etching at the bonding position of the first and second layers during etching with an etching solution containing from 1 to 12 parts by weight; performing a semiconductor processing step on the exposed surface of the method.