JPS5833702B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a composite semiconductor device comprising complementary transistors;
In particular, the present invention relates to a method for manufacturing a semiconductor substrate suitable for obtaining a high-voltage composite semiconductor device.

Conventionally, a PN junction isolation structure and a dielectric isolation structure have been proposed as element isolation structures in this type of semiconductor substrate.

In a PN junction isolation structure, for example, when an NPN transistor is formed, the breakdown voltage is mainly determined by the avalanche of the depletion layer between the base and the collector.

This is because the thickness of the high resistivity collector side region (referred to as the collector pocket) into which the depletion layer can extend is limited.

To increase pressure resistance, make the collector pocket larger.
That is, it is sufficient to increase the thickness of the epitaxial growth layer, but this requires high-temperature and long-term heat treatment to form the P+ diffusion layer for isolation.

Since the buried layer is lifted by this heat treatment, the collector pocket becomes smaller.

Due to the balance between the two, it is known that the breakdown voltage of a semiconductor element using PN junction isolation is about 120V at most.

Therefore, when a higher breakdown voltage is required, a dielectric isolation structure is adopted.

In the dielectric isolation structure, for example, as shown in FIG. 1, N-type and P-type head regions 2 are formed on a polycrystalline silicon substrate 1, and these N-type and P-type head regions 2 are separated from each other by an insulating film 3. It has a similar structure.

In the dielectric isolation structure, unlike PN junction isolation, the collector
The thickness of the pocket can be increased.

Therefore, in order to obtain the desired breakdown voltage, it is only necessary to set the lower limit of the resistivity of the collector pocket and the lower limit of the depth (thickness) of the dielectrically isolated island so that the depletion layer can be extended. .

However, depending on the conventional manufacturing method of this type of substrate, the conditions for setting the above-mentioned withstand voltage cannot be satisfied, such as the fact that the depth of the dielectrically isolated island can be sufficiently large, and that the concentration distribution of this island is small. Therefore, the desired design breakdown voltage could not be obtained.

For example, one of the manufacturing methods for the semiconductor substrate shown in FIG.
This is a well-known EPIC technology, in which a semiconductor region 2 having either N-type or P-type conductivity is formed, and the desired region 2 is made P-type or N-type by impurity introduction technology such as ion implantation. There is a method of making a semiconductor substrate.

However, in this manufacturing method, the impurities to be introduced have a distribution in the depth direction, and when trying to obtain a region 2 with a higher resistivity, the accuracy of impurity control is low.
thickness and resistivity are limited.

Therefore, it has been difficult to increase the breakdown voltage of semiconductor elements that require high resistivity.

Furthermore, in order to improve the above-mentioned drawbacks, a manufacturing method shown in FIG. 2 has been proposed.

That is, as shown in FIG. 2A, a depression 5 is formed in a part of the upper surface of the semiconductor substrate 4, and then, as shown in FIG. 2B, a silicon layer 6 having a conductivity type opposite to that of the semiconductor substrate 4 is formed. Epitaxial growth is performed on the substrate 4.

At this time, it is also possible to provide a compensation diffusion layer 7 on the silicon layer 6 if necessary.

Next, as shown in FIG. 2C, a silicon region 8 is formed on the semiconductor substrate 4 by removing unnecessary silicon layer 6 by polishing or the like.

Next, as shown in the second diagram, portions of the semiconductor substrate 4 and silicon region 8 having different conductivity types are separated by a groove 9, and a plurality of N-type and P-type silicon regions 9 and 11 are formed.

The next step is to manufacture the semiconductor body using the well-known EPIC technology.

However, the above manufacturing method has the following two drawbacks.

That is, in the process shown in FIG. 2A, the depressions 5 are not processed uniformly and defects are generated during the epitaxial growth of the silicon layer 6, so that a significant deterioration of the device characteristics is unavoidable.

Furthermore, since the compensation diffusion layer I is cut out by the groove 9,
Since the compensating diffusion layer 7 is not formed around the silicon region 10, the good characteristics of the device are not fully exhibited.

In order to solve these drawbacks, the present applicant has already applied for a method for manufacturing a semiconductor device shown in FIG.
45063).

That is, in a P-type semiconductor substrate 53 made of, for example, Si and having principal surfaces 51 and 52 (however, 52 is not shown) facing each other as shown in FIG. As shown in FIG. 3B, a mask layer 6 made of, for example, 5i3N4, which can extend to cover areas other than the local area 60.
form 1.

Next, an N-type epitaxial growth layer 62 that can be continuously extended is formed on the mask layer 61 and the region 60 as shown in FIG. 3C.

In this case, a portion 63 of the layer 62 above the region 60 can be obtained from a single crystal, but a portion 64 above the mask layer 61 cannot be obtained from a single crystal.

Next, on the portion 63 of the layer 62, for example, 5i is applied as shown in the third diagram.
A mask layer 65 made of 0.02 is applied, and the layer 62 is etched using this as a mask to form a semiconductor layer 66 in the area below the mask layer 65 on the area 60 of the portion 63, as shown in FIG. 3E. Leave as and remove others.

In this case, a groove 68 is formed in the substrate 53 from the main surface 51 side.

Next, the mask layer 65 is removed from above the layer 66, and then an N+ type semiconductor region 69 is formed on the outer surface side of the layer 66 and on the trench 68 side by, for example, a diffusion process of an N type impurity.

Introducing this N+ impurity does not require a photoetching step, and is a so-called self-lining, forming a collector compensation layer that is indispensable for improving the characteristics of the transistor.

Next, for example, by thermal oxidation treatment, the area 6 is removed as shown in FIG. 3G.
An insulating layer 70 is formed on the outer surface of 9.

Next, the mask layer 61 is removed from the main surface 57 as shown in FIG. An extendable P-type epitaxial growth layer 72 is formed.

Unlike the conventional method described in FIG. 2, the epitaxial growth 73 on which semiconductor elements are to be formed in the future is performed on a uniform processed surface 11, and a good crystal layer can be obtained.

In this case, a portion 73 of the layer 72 above the region 71 can be obtained from a good single crystal, but a portion 74 above the insulating layer 70 cannot be obtained from a single crystal.

Next, on the portion 73 of the layer 72, as shown in FIG.
A mask layer 75 made of i02 is formed, and then the mask layer 75 is
By performing an etching process on the layer 72 and the substrate 53 using as a mask, as shown in FIG. , a structure in which a semiconductor layer 80 in a region other than the above-mentioned insulating layer 70 of the layer 72 is laminated on the semiconductor layer 79 in the region under the insulating layer 75 in the region other than the region under the substrate 530 layer 66. semiconductor layer 8 having
form 1.

In this case, the insulating layer 70 acts as a mask layer.

Next, the mask layer 75 is removed from above the layer 81, and then, as shown in FIG. A P+ type semiconductor layer 82 is formed by the impurity diffusion process.

This compensation layer is also formed of a self-line like the N+ layer 69 described above.

Next, for example, by thermal oxidation treatment, the layer 82 is formed as shown in FIG. 3M.
An insulating layer 83 is formed on the outer surface of.

Next, a continuously extending polycrystalline semiconductor layer 84 is formed on the insulating layers 70 and 83 as shown in FIG. 3N.

Next, by polishing and etching the main surface 52 side of the substrate 53, as shown in FIG. A main complement 85 is formed by cutting along the extending surface.

Next, as shown in FIG. 3P, N-type regions 58 and 59 are formed in layers 78 and 81, respectively, by a diffusion process of N-type impurities, for example.

Next, P-type regions 91 and 92 are formed locally from the main surface 85 in the layer 77 of the layer 18 and the region 59 of the layer 81, respectively, as shown in FIG. At the same time, a P-type region 93 is formed in layer 79 of layer 81 to be connected to layer 82 .

Next, for example, an N-type region 94 is formed in the region 91 as shown in FIG.
An N-type region 95 connected to region 59 is formed in layer 79 of No. 1.

Next, as shown in FIG.
8, 99, 100 and 101, thus obtaining the desired composite semiconductor device.

In FIG. 3R, 102 is an insulating layer.

According to the configuration of the composite semiconductor device shown in FIG. 3M obtained by such a manufacturing method, the layers 78 and 81 form the insulating layer 70 on both sides of the main surfaces 103 and 104 other than the main surfaces 103 and 104 on the main surface 85 side. and 83 in a polycrystalline layer 84 common to them, and thus layers 66 and 77 of layer 78, regions 91,
and 94 as a collector, a base, and an emitter region, a vertical NPN transistor Q1, and a layer 810 and a layer 80.
, a vertical PNP transistor Q2 having regions 59 and 92 as collector, base and emitter regions, respectively, and these transistors Q1 and Q2 are connected to the insulating layer 7.
In this case, as is clear from the above, the transistors Q1 . The semiconductor layers 77 and 79 on which transistors Q1 and Q2 are formed have good crystallinity, and sufficient compensation diffusion layers can be provided in the collector regions of transistors Q1 and Q2, respectively, so that both transistors Q1 and Q2 can be used for current amplification. It has six major features that allow it to easily realize excellent electrical characteristics such as a high rate of conductivity.

Furthermore, since the semiconductor layers 77 and 79 on which the transistors Q1 and Q2 are formed are both formed by epitaxial growth, the resistivity can be increased, and the breakdown voltage of the device can also be increased.

However, in the above-described manufacturing method, sufficient consideration was not given to the mask layer 61, so there was a drawback that the number of non-defective products per wafer was extremely small.

When the cause of this problem was investigated, it became clear that the following points were the cause of this defect.

1) Since there is no layer between the mask layer 61 and the P-type Si substrate 53 to relieve stress between them, defects may occur around the local opening region 60, and sometimes the semiconductor layer 66 And the crystallinity of the semiconductor layer 78 was impaired.

2) In the step shown in FIG. 3E, mask layer 61 is wetted directly with an anisotropic etching solution.

At this time, the etching resistance of the mask layer 61 against anisotropic etching liquid (KOH, alcohol) is not sufficient,
When observed over a wide area, pinhole-like defects occur, and the main surface 51 of the Si substrate is oxidized through these pinholes, which impairs the crystallinity near the pinholes when growing the single crystal semiconductor layer 73. Ta.

Therefore, when manufacturing a semiconductor device using this manufacturing method,
It was possible to obtain relatively good products for SSI class chips with a chip size of about 1 width, but it was difficult to obtain good products for LSI class chips with a chip size of about 5 widths or more.

The present invention proposes a novel method for manufacturing a semiconductor substrate free from the above-mentioned drawbacks, using a three-layer structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated as the mask layer. An example of the method for manufacturing a semiconductor substrate according to the present invention will be explained in detail with reference to FIG.

Opposing main surfaces 5 as shown in FIG. 4A obtained in advance
1 and 52 (however, 52 is not shown), for example, N-type impurity concentration 1.5×1015/cr#7: (10
0) within a silicon semiconductor substrate 53 having a main surface 5.
From the first side, as shown in Figure 4B, for example, the size is 300μ.
An extended mask layer 61 is formed to cover areas other than a plurality of m-square local regions 60.

The mask layer 61 includes a silicon nitride film and has a thickness of 50 mm.
It has a three-layer structure in which a silicon oxide film of 0 people, a silicon nitride film of 1500 people, and a silicon oxide film with a thickness of 5000 Å are sequentially laminated.

Next, as shown in FIG.
1 epitaxial growth layer 62 is formed to a thickness of 50 μm.

The thickness of this epitaxial growth layer 62 is selected so as to obtain the desired base-emitter junction breakdown voltage of the transistor formed therein, but it is possible to increase the thickness by using the epitaxial growth method. It is.

In this case, the portion 63 of the layer 62 above the region 60 can of course be made of single crystal, but the portion 64 above the mask layer 61 cannot be made of single crystal.

Further, although the boundary region 100 between the portions 63 and 64 has the same crystal axis as the portion 63, the crystallinity is poor.

The boundary surface 101 between the ff63 and the boundary area 100 is (
111) coincides with the surface.

Next, a mask layer 65 made of a silicon oxide film is applied on the portion 63 of the layer 62 as shown in the fourth diagram, and using this as a mask, the layer 62 is subjected to an anisotropic etching process using, for example, a mixture of KOH and alcohol. Then, as shown in FIG. 4E, the area below the mask layer 65 on the area 60 of the portion 63 is left as a semiconductor layer 66, and the rest is removed.

In this case, if mask layer 65 is formed to cover at least all of portion 63, boundary region 100 is etched anisotropically, leaving only portion 63 defined by region 60.

At this time, the side surface of the semiconductor layer 66 is about 54 mm with respect to the main surface 51.
Make a °.

Furthermore, if the mask layer 65 is formed so as to cover only part of the portion 63, a groove will be formed on the substrate 53 at the boundary between the region 60 and the mask layer 61; The shape is almost the same as in the above case.

In this way, in this step, the mask layer 61 and the mask layer 65 do not need to be precisely aligned.

Next, in order to completely remove only the mask layer 65, the uppermost layer 66 is removed using, for example, dilute hydrofluoric acid or an etching solution containing hydrofluoric acid.At this time, the uppermost silicon oxide film of the mask layer 61 may also be removed. ), then an N+ type semiconductor region 69 having an impurity concentration of 1×10 20 /d and a thickness of 1 μm is formed on the outer box side and the trench 68 side in the layer 66 by diffusion treatment of N type impurities.

This semiconductor region 69 has a thickness of 15 mm by subsequent heat treatment.
It is on the order of μm.

Introducing this N+ impurity does not require a photoetching step, and is a so-called self-lining, forming a collector compensation layer that is indispensable for improving the characteristics of the transistor.

Next, an insulating layer 70 made of a silicon oxide film having a thickness of 08 μm is formed on the outer surface of the region 69 as shown in FIG. 4G by ordinary thermal oxidation treatment at 1050° C.

Next, by utilizing the difference in etching rate between the mask layer 61 having a silicon nitride film formed as a surface layer and the insulating layer 70 made of a silicon oxide film and the difference in thickness of the silicon oxide film, for example, thermal rinsing at 160°C is performed. By etching the entire surface with an acid solution, the mask layer 6 is etched as shown in FIG.
Only the silicon nitride film and silicon oxide film of No. 1 are completely and selectively removed from the main surface 51.

What should be noted here is that the silicon nitride film of the mask layer 61 and the insulating layer 70 have different compositions, so etching solutions with different etching rates can be used, and the thickness of the silicon oxide film of the mask layer 61 Since it is sufficiently thinner than the silicon oxide film of the insulating layer 70, no photolithography process is required.

Applying a photolithography process to a thick film such as the semiconductor layer 66 is difficult in terms of yield, and this process in the present invention is also useful in terms of yield.

Next, a P-type epitaxial growth layer 72 with an impurity concentration of 7×10 14 /C 71t is continuously extended over the region 71 from which the insulating layer 10 and the mask layer 61 of the main surface 51 have been removed, as shown in FIG. Form approximately 70 μm.

Unlike the conventional method described in FIG. 2, the layer 73 on which the semiconductor element is to be formed is epitaxially grown on the uniform processed surface 71, and a good crystal layer can be obtained.

In this case, the portion 14 above the insulating layer γ0 cannot be made of single crystal.

Next, on the portion 73 of the layer 72, as shown in FIG.
A mask layer 75 made of a silicon oxide film with a size of 300 μm square is formed in a part of the region where the semiconductor layer 66 is not provided, and then covered with the mask layer 15 of the layer 72 using the mask layer 15 as a mask. Uncovered area and substrate 53
As shown in FIG. 4K, the layer 66 is laminated on the semiconductor layer 77 in the region below the layer 66 of the substrate 53. A semiconductor layer 80 in a region other than above the insulating layer 70 of the layer 72 is laminated on the semiconductor layer 79 in the region under the insulating layer 75 in the region other than the region under the layer 66 of the substrate 53. A semiconductor layer 81 having a structure is formed.

In this case, the insulating layer 70 functions as a mask layer, and by this etching process, the semiconductor layer 81 is processed and a groove for separation is formed at the same time.

Next, by utilizing the difference in thickness between the insulating layers 70 and 75, the mask layer 75 is removed from above the layer 81 by etching the entire surface without going through a photolithography process.

Next, as shown in the fourth diagram, a P+ type impurity concentration I x 1 is applied to the regions of the layer 78 that are not covered by the insulating layer 70 and to the outer surfaces of the layer 81 as shown in the fourth diagram.
020/crL A semiconductor layer 82 having a thickness of about 1 μm is formed.

The thickness of this semiconductor layer 82 will be approximately 12 μm in later steps.

This compensation layer is also formed of a self-line like the N+ layer 69 described above.

Next, an insulating layer 83 is formed on the outer surface of layer 82 as shown in FIG. 4M by thermal oxidation treatment at 1050° C. or the like.

Next, as shown in FIG. 4N, a polycrystalline silicon semiconductor layer 84 having a thickness of 200 μm and 8 degrees is formed on the insulating layers 70 and 83 in a continuous manner.

Next, by polishing and etching the main surface 52 side of the substrate 53, the layer 77 of the semiconductor layer 78 and the layer 79 of the semiconductor layer 81 are removed as shown in FIG.
6. A main surface 85 is formed by cutting the semiconductor layer 810 and the insulating layer 83 along a plane extending parallel to the main surface 51.

Thus, the N-type epitaxial growth layer γ8 and the P-type epitaxial growth layer 81 have the compensating diffusion layers 69 and 82 on their side and bottom surfaces, respectively, and the layers 78 and 81 have the compensation diffusion layers 69 and 82 on their side and bottom surfaces, respectively, through the insulating layers 70 and 83. A semiconductor substrate having a structure supported by a polycrystalline layer 84 is obtained.

According to the present invention described above, since the semiconductor layers 66 and 80 are formed by epitaxial growth, they have extremely high crystallinity, can be made sufficiently thick, and have high resistivity. .

Furthermore, since the mask layer 61 has a three-layer structure, the semiconductor layer 61
6.78 is obtained as a good quality one, and the main surface 51 of the Si substrate is prevented from being oxidized through the pinhole.
A high quality semiconductor substrate can be obtained.

A method of manufacturing a composite semiconductor device using the above-mentioned semiconductor substrate will be explained using a PNP I-transistor and an NPN transistor as examples.

First, as shown in FIG. 5A, N-type regions 58 and 59 are formed in layers 78 and 81, respectively, by a diffusion process of N-type impurities.

Next, as shown in FIG. 5A, P-type regions 91 and 92 are formed locally from the main surface 85 in the layer 77 of the layer 78 and in the region 59 of the layer 81, respectively, by a P-type impurity diffusion process. At the same time, a P-type region 93 connected to the layer 82 is formed in the layer 79 of the layer 81 .

Note that the above-mentioned N-type and P-type diffusion treatments may be performed first for the P-type and then for the N-type, depending on conditions such as the type and concentration of impurities and the temperature required for the diffusion treatment.

Next, as shown in FIG. 5B, an N-type region 94 is formed in the region 91 by a diffusion process of N-type impurities, and the layer 8
An N-type region 95 connected to region 59 is formed in layer 79 of No. 1.

Next, as shown in FIG.
．． 98, 99, 100 and 101 are attached, thus obtaining the target composite semiconductor device.

In addition, 102 in FIG. 5C is an insulating layer.

According to the configuration of the composite semiconductor device shown in FIG. 5C, the layer 78
A vertical NPN transistor Q1 has layers 66 and 77, regions 91 and 94 as collector, base and emitter regions, respectively, and layer 80, regions 59 and 92 of layer 81 as collector, base and emitter regions, respectively. Vertical P
The transistors Q1 and Q2 are separated from each other by insulating layers 70 and 83.

In this case, as is clear from the above, the transistor QL
Since the semiconductor layers 66 and 80 on which transistors Q1 and Q2 are formed have good crystallinity, and sufficient compensation diffusion layers can be provided in the collector regions of transistors Q1 and Q2, both transistors Q1 and Q2 can be used for current amplification. It has the characteristics of a dog that can easily realize excellent electrical characteristics such as a dog's rate.

Furthermore, since the semiconductor layers 66 and 80 on which the transistors Q1 and Q2 are formed are both formed by epitaxial growth, it is clear that the resistivity can be increased and the breakdown voltage of the device can also be increased.

This will be illustrated in an experimental example.

FIG. 6A shows the voltage/current characteristics of the transistor Q1, and the manufacturing conditions are as follows.

The depth of the semiconductor layer 78 is 50 μm, and the planar size is 30 μm.
0 μm x 300 μm; Emitter depth is 7 μm 1 Impurity concentration is 1 x 20 /crtl: Base depth is 11
μm, the impurity concentration is 2×1019/77j, and the impurity concentration of the collector pocket 78 is 5×10”/CIL.
FIG. 6B shows the voltage/current characteristics of the transistor Q2, and the manufacturing conditions are as follows.

The semiconductor substrate 53 used has a P-type impurity concentration of 1.5×1
015/d, the depth of the semiconductor layer 81 is 70 μm, the planar size is 300×300 μm; the depth of the emitter 92 is 8
μm1 impurity concentration is 2 x 1019/(cap; base 5
9 has a depth of 11 μm and an impurity concentration of 8×1018/d;
The impurity concentration of the collector pocket is 7X10"/cIL. As is clear from the characteristic diagram in FIG.
The transistor has an extremely high breakdown voltage of 350 to 380V.

As described above, according to the method for manufacturing a semiconductor substrate of the present invention, the semiconductor layer constituting the island has extremely high crystallinity, its depth can be sufficiently increased, and its resistivity is high. This is extremely useful for increasing the voltage resistance of semiconductor devices.

Further, in the present invention, since the mask layer 61 has a three-layer structure, a semiconductor substrate of good quality can be obtained, which has the advantage that LSIs having a chip size of about 5 mm or more can be obtained with a high yield rate.

The above description merely shows an example of the method for manufacturing a composite semiconductor device according to the present invention.
It is also possible to read "N type" and "N+ type", and "N type" and "N+ type" to be read as "P type" and "P+ type".

Further, in the step of FIG. 4F, an N+ type semiconductor layer 69 is formed in the semiconductor layers 66 and 67 from the surface side, and in the step of FIG. Instead of forming the polycrystalline N7 type semiconductor layer 82 on the outer surfaces of the semiconductor layers b6 and 61, a polycrystalline P+ type semiconductor layer is formed on the outer surface of the semiconductor layer 81. A step of forming a semiconductor layer is taken, and therefore the semiconductor layer 69 described above is
In this case, 82 and 82 may be replaced with N+ type and P+ type semiconductor layers, and various other modifications may be made without departing from the spirit of the invention of the vehicle.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor substrate with a dielectric separation structure, FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor substrate, and FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor substrate proposed by the applicant. Figures 4 and 4 are cross-sectional views showing sequential steps in an example of the method for manufacturing a semiconductor substrate according to the present invention, and Figure 5 shows a method for manufacturing a composite semiconductor device using the semiconductor substrate according to the present invention. A cross-sectional view of FIG. 6 is a diagram showing the characteristics of a transistor using a semiconductor substrate according to the present invention. 51.52... Main surface of semiconductor substrate, 53...
... Semiconductor substrate, 61 ... Mask layer, 62
, 72...Epitaxial growth layer, 69, 82
...High impurity concentration semiconductor layer, 65, 70
, γ5,83...Insulating layer, 66, γ7,7B,
79, 80, 81... semiconductor layer, 58, 59.
9? , 92, 94, 95... semiconductor region.

Claims (1)

[Claims] 1. A silicon oxide film, a silicon nitride film, and an oxide film extending over a first main surface of a silicon semiconductor substrate having first and second main surfaces to cover areas other than the first local area. forming a mask layer formed by successively stacking silicon films; forming a first insulating layer made of a silicon oxide film on the first local region on the first epitaxial growth layer; using the first epitaxial layer as a mask, leaving a portion of the first epitaxial layer above the first local region as a first semiconductor layer and removing the other portion; and after removing the first insulating layer. , a fourth semiconductor layer having a higher impurity concentration than the semiconductor layer of the bundle 1 is formed on the outer surface of the first semiconductor layer.
forming a second insulating layer on the outer surface of the second semiconductor layer; Using an etching solution or etching gas that has a high etching rate for the silicon nitride film, the entire first main surface is etched, and the mask layer is removed while the second insulating layer remains. after that, forming a second epitaxial growth layer having a second conductivity type that extends continuously over the second insulating layer and the region of the first main surface where the mask layer has been removed; forming a third insulating layer made of a silicon oxide film on the second epitaxial growth layer in a part of the region where the first semiconductor layer is not provided; a step of leaving a portion of the second epitaxial growth layer on the second local region other than the second semiconductor layer as a third semiconductor layer and removing the other portion; and removing the third insulating layer. After that, a second semiconductor layer having a higher impurity concentration than the third semiconductor layer is formed on the outer surface of the third semiconductor layer.
forming a fourth insulating layer on the outer surface of the fourth semiconductor layer; and forming a fourth insulating layer on the second and fourth insulating layers. forming a continuously extended polycrystalline semiconductor layer, and extending the first semiconductor layer, the third semiconductor layer, and the fourth insulating layer across parallel to the first main surface; 1. A method for manufacturing a semiconductor substrate, comprising the step of forming a third main surface in a manner obtained by cutting along the length.