JPS5825245A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To achieve good electric separation of elements and high integration by a method wherein a semiconductor layer is grown on a semiconductor substrate and an island region is provided in the layer while an insulation film for separation is formed not only in both side ends of this region but also in the bottom. CONSTITUTION:A p<+> type layer 13 is formed on the outer layer of a p type Si substrate 11 by diffusion, and an n type layer 14 having required resistivity is provided on the layer 13 by epitaxial growth, then a p<+> type region 15 reaching the layer 13 is formed at the endmost portions of the layer 14 by diffusion, so that the layer 14 is separated as an islanded region 12. Next, the substrate 11 is dipped in hydrofluoric acid liquid and receives anode formation processing to convert only the layer 13 and the region 15 into porosity Si layer 13' and 15'. Afterward these layers are converted into SiO2 layers 6 and 6' by heat treatment to electrically separate the region 12 not only at its both sides but also at the base by the layers 6 and 6'. After this a p<+> type source region 2 and a drain region 3 are formed on the region 12 by diffusion, and a polycrystalline Si gate 5 is provided on the region 12 which is between the regions 2 and 3 via a gate SiO2 film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having an insulating film isolation structure and a method for manufacturing the same.

Electrical isolation methods between elements employed in semiconductor integrated circuits (hereinafter referred to as ICs) are broadly classified into (IIPN junction isolation method) and (2) insulating film isolation method.

Of these, the latter insulating film separation method has many advantages over the former, and therefore tends to be widely used in the future.

This insulation film separation method is called LOOO8 (Local 0xi).
It is generally known as a dation (+f 5 ilicon) structure, and has an insulating film isolation structure as shown in FIG. The figure shows the case of MO8IO, where 1 is an n-type region, 2.3 is a pair of p-type regions that are selectively formed in the n-type region 1 and is to become a source region and a drain region, and 4 is a pair of p-type regions. 5 is a polycrystalline silicon film formed on the gate insulating film 4; 7 is a glass film covering the polycrystalline silicon 5 and the insulating film 6, and 8 and 9 are provided in the pair of p-type regions 2 and 3, respectively. a source electrode and a gate electrode.

By the way, in MO8IO with the above structure, the n-type region 1
The end of the PN junction 10 between the pair of p-type regions 2.3 and 2.3 is separated by the insulating film 6, but the other parts are P-type.
Electrical isolation is not complete because the line of N junction 10 remains as it is.

Therefore, a PN junction capacitance exists in the source region 2 and the drain/region 3, and a parasitic capacitance also exists due to the wiring formed on the insulating film 6 or the glass film T, which reduces the operating speed of the circuit. Defects arise. Another disadvantage is that the circuit configuration is complicated in order to prevent the influence of these capacitances.

The present invention has been made in response to the above problems, and it is possible to eliminate the conventional drawbacks by interposing an insulating film not only at the side ends of the semiconductor island region where semiconductor circuit elements are to be formed, but also at the bottom thereof. It is an object of the present invention to provide a semiconductor integrated circuit configured as described above and a method for manufacturing the same.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view showing a semiconductor integrated circuit according to an embodiment of the present invention, in which the same parts as in FIG. An insulating film 6' separating the other semiconductor layers into a plurality of island regions 12 is a second insulating film formed at the bottom of the island region 12 so as to be continuous with the insulating film 6.

The island region 12 has, for example, a p-type source region 2, a drain region 3, and a polycrystalline silicon gate 5.
A FET is formed.

The semiconductor integrated circuit having the above structure is manufactured by the manufacturing method shown in FIG.

Hereinafter, the manufacturing method will be explained step by step with reference to FIG.

Step (a): As shown in FIG. 3 (al), a p-type layer 13 with a high impurity concentration is formed by diffusing boron on the surface of a p-type silicon substrate 11, and a desired resistivity is formed on the surface of this 94 layer 13. .

A thick n-type layer 14 is formed by epitaxial growth.

Step (b): As shown in FIG. 3(b), a second high impurity concentration p medium type region is formed by diffusing poron into the n type layer 14 by a well-known selective diffusion method to reach the p 10 type layer 13. form 15. As a result, the n-type layer 14 is separated into a plurality of island regions 12 by the p-medium region 15.

Step (C): As shown in FIG. 3(C), the semiconductor substrate is immersed in, for example, a hydrofluoric acid (HF) solution and anodized, thereby forming the p-type layer 13 and the region 15.
An anodizing current is applied only to the silicon wafers to convert those portions into porous silicon 13' and 15'.

Step (d): As shown in FIG. 3(d), the semiconductor substrate is thermally oxidized to transform the porous silicon portions 13' and 15' into silicon oxide films 6 and 6'. In this thermal oxidation treatment, the porous silicon portion has the property of being oxidized faster than other single crystal silicon portions, so the silicon oxide films 6 and 6' can be formed in a short time. Therefore, the plurality of island regions 12 are electrically isolated from each other by the insulating films 6 and 6'.

Step (e): As shown in FIG. 3(e), for example, a normal MO
By forming a MOSFET having a p-type source region 2, a drain region 3, and a polycrystalline silicon gate 5 in the island region 12 using the S process, the M of the structure shown in FIG.
O8IO is obtained.

In the structure of the semiconductor integrated circuit according to the embodiment of the present invention,
Not only the side ends but also the bottom of the island region 12 where circuit elements such as MOSFETs are to be formed are insulated from other regions by the insulating film 6'.
0 does not exist. Therefore, the PN junction capacitance in the source region and drain region can be significantly reduced. Furthermore, since the insulating film is formed thick and the wiring is formed on it, parasitic capacitance can also be reduced.

As described above, according to the present invention, since the insulating film is interposed not only at the side edges of the semiconductor island region where the semiconductor circuit element is to be formed but also at the bottom thereof, various undesirable capacitances are generated. This makes it possible to keep the amount of noise to a minimum, thereby improving the operating speed of the circuit.

Furthermore, since the degree of electrical isolation between elements is improved, the circuit configuration can also be simplified.

Furthermore, since it is possible to reduce the area of the island region or the insulating film region, higher integration can be achieved. Furthermore, as the degree of integration increases, circuit elements having various characteristics can be formed on a common semiconductor substrate, making it possible to manufacture a wide variety of ICs.

Although the present embodiment has been described using an example in which MO8IO is manufactured, the present invention is not limited to this and can be similarly applied to the case where bipolar ICs are manufactured.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing a conventional example, Figures 2 and 3 (a
) to (el are all cross-sectional views showing examples of the present invention. 2... Source region, 3... Drain region, 5...
Polycrystalline silicon gate, 6, 6'...insulating film, 12...
- Island area. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. An insulating film that is selectively formed on the surface of the semiconductor substrate and separates the other surface of the semiconductor substrate into a plurality of island regions;
and a second insulating film formed at the bottom of the island region so as to be continuous with the insulating film. 2. The semiconductor integrated circuit according to claim 1, wherein a MOSFET is formed in the island region. 3. (A) A semiconductor substrate having a first conductivity type semiconductor layer with a higher impurity concentration on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer on the first conductivity type semiconductor layer with a higher impurity concentration. A process of forming a semiconductor layer. (B) forming a first conductivity type semiconductor region with a high impurity concentration that selectively reaches the first conductivity type semiconductor layer with a high impurity concentration in the second conductivity type semiconductor layer; A process of separating a type semiconductor layer into multiple island regions. (0) A step of making only the high impurity concentration first conductivity type semiconductor layer and the second high impurity concentration first conductivity type semiconductor region porous by anodizing the semiconductor substrate. (D) A step of converting the porous first conductivity type semiconductor region and semiconductor layer into an insulating film. (l) A method for manufacturing a semiconductor integrated circuit, comprising the step of forming a desired semiconductor circuit element in the island region. 4. Forming the second conductive type semiconductor layer in the step (6) above by an epitaxial growth method. A method for manufacturing a semiconductor integrated circuit according to claim 3, characterized in that: