JPS6154256B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an ultrahigh-speed logic integrated circuit device.

A conventional method for manufacturing this type of device is as shown in FIG. FIGS. 1a to 1g are cross-sectional views showing a conventional manufacturing method in the order of steps. Figure 1a
Relatively low impurity concentration (10 ¹⁴ cm ^-3 ) as shown in
On the surface of the semiconductor substrate 1 made of p-type silicon,
The opening 2a is opened so that the selected surface area is exposed.
An insulating film 2, such as an oxide film (SiO ₂ ) having a
An n ⁺ buried region 3 is formed. Note that region 4 in FIG. 4B is a p + channel cut region provided in a region other than the n ⁺ buried region in the surface region of p type semiconductor substrate 1, and is formed by, for example, ion implantation ^technology . Next, as shown in FIG. 3c, silicon is epitaxially grown on the entire surface of the semiconductor substrate 1 including the selected surface region and the insulating film 2, and a single crystal semiconductor region 5a is formed in the selected surface region. Further, a polycrystalline semiconductor region 5b is formed on the insulating film 2. Next, as shown in FIG. 4D, a resist 6 is applied to the surfaces of the single crystal semiconductor region 5a and the polycrystalline semiconductor region 5b, and then the polycrystalline semiconductor region 5b is partially removed. Next, as shown in FIG. 5e, p-type impurities such as boron are diffused into one of the polycrystalline semiconductor regions 5b and the single-crystalline semiconductor region 5a using the oxide film 8a as a mask to form external base regions 7b and internal regions, respectively. A base region 7a is formed. In this case, since the diffusion rate of impurities in the polycrystalline semiconductor region is faster than that in the single-crystalline semiconductor region, one polycrystalline region 5b is entirely converted into the p-type base region 7b, as shown in FIG. 1e. The single crystal semiconductor region 5a is partially converted into a p-type base region 7a. Next, as shown in FIG. 1f, the other polycrystalline semiconductor region 5 is formed using the oxide film 8b as a mask.
arsenic (As) is simultaneously diffused into the internal base region 7a and the n ⁺ type polycrystalline collector region 9b.
and an n ⁺ type emitter region 10. Note that 9a is diffused into the single crystal semiconductor region 5a.
n ⁺ collector area. Next, as shown in ^FIG .
1b to the p-type external base region 7b.
1c, and a collector electrode 11a is formed in the n ⁺ collector region 9b, respectively.

The semiconductor device manufactured in this way has a single crystal region 5a simultaneously formed on the p-type substrate 1 by vapor phase growth.
and a polycrystalline region 5b, both regions 5a and 5b are provided.
In order to provide a collector region 5a, a base region 7a, and an emitter region 10 in a single crystal semiconductor region by utilizing the difference in diffusion speed in
Selected surface area i.e. n ⁺ buried area 3
By making the area of the collector base junction smaller than that of existing devices, the area of the collector base junction can be made smaller, so the base collector capacitance can be made smaller. Therefore, since the thickness of the polycrystalline semiconductor regions 9b and 7b is large, there is a drawback that wiring defects due to steps are likely to occur in the portions 12a and 12c shown in FIG. 1g.

The present invention provides a manufacturing method for reducing the level difference in wiring in this type of ultra-high-speed logic integrated circuit device. FIG. 2 is a sectional view of a main part showing a manufacturing method according to an embodiment of the present invention in order of steps. As shown in FIG. 2a, a semiconductor substrate 1 made of p-type silicon with a relatively low impurity concentration (10 ¹⁴ cm ^-3 )
An insulating film 2 such as an oxide film (SiO ₂ ) having an opening 2a is formed on the surface of the substrate so that a selected surface region 1a is exposed, and then, as shown in FIG. 2a, an n-type impurity such as arsenic (As) is diffused to form an n ⁺ buried region 3. In addition, p ⁺ region 4 in Fig. 2b is p
This is a p ⁺ channel cut region provided in a region other than the n ⁺ buried region 3 in the surface region of the shaped semiconductor substrate 1 . Next, as shown in FIG. 2c, when n-type silicon is epitaxially grown on the entire surface of the semiconductor substrate 1 including the selected surface region 1a and the insulating film 2, the selected surface region 1a
A single crystal n-type semiconductor region 5a is formed on the insulating film 2, and a polycrystalline semiconductor region 5b is formed on the insulating film 2. When an impurity such as boron is diffused over the entire surface of the semiconductor substrate 1 as shown in FIG. 2c in which the single crystal semiconductor region 5a and the polycrystalline semiconductor region 5b are formed, Since the diffusion coefficient of the polycrystalline semiconductor region 5b is larger, as shown in FIG. An impurity introduced region 51b is formed which is thicker than the impurity introduced region 51a.

Then, when heat treatment is performed in an oxidizing atmosphere containing hydrogen, impurity introduced regions 51a and 51b and an oxidized region 52 shown in FIG. 2e are formed thereon with a thickness of about 4:6. Next, when the surface of the semiconductor substrate 1 on which the oxidized region 52 is formed is etched in a hydrofluoric acid atmosphere, there is a large difference in etching rate between the oxidized region 52 and the polycrystalline semiconductor region 5b, so that there is a gap between the surfaces of the regions 5a and 5b. The formation of steps is prevented, and the polycrystalline semiconductor region 5b is
However, a semiconductor substrate as shown in FIG. 2f, in which the difference in level between the surface and the insulating film 2 is small, can be obtained.

Next, as shown in FIG. 2g, after removing unnecessary parts of the polycrystalline semiconductor region 5b, a part of the surface of the single crystal n-type epitaxial region 5a is left and is continuous with one polycrystalline semiconductor region. When the p-type impurity is diffused in the single crystal n-type epitaxial region 5a, the single crystal n-type epitaxial region 5a has the p-type region 7a, and one polycrystalline semiconductor region has the entire p-type impurity. Polycrystalline region 7b is formed. In addition,
Reference numeral 8 in FIG. 2g indicates these p-type regions 7a,
These are a mask oxide film when forming 7b and an oxide film formed during heat treatment. Next, as shown in FIG. 2h, using the oxide film 8 as a mask, an n ⁺ type single crystal region 10 is formed in the p type region 7a within the single crystal region.
Further, an n ⁺ polycrystalline region 9b is diffused and formed in the other polycrystalline region. Next ^, as shown in FIG ^.
a, 11b, and 11c are provided.

In this way, the n-type epitaxial region 5a
is an internal collector region, the n ⁺ polycrystalline semiconductor region 9b continuous to this n-type epitaxial region 5a is an external collector region, the p-type single crystal region 7a is an internal base region, and the p-type semiconductor region continuous to this p-type single crystal region 7a is An npn transistor is formed in which the polycrystalline region 7b is used as an external base region and the n ⁺ type single crystal region 10 is used as an emitter region, and the base electrode 11c and collector electrode 11a extend on the insulating film 2 and are connected to other elements or regions. (none of which are shown). In this case, the difference in level between the surfaces of the polycrystalline regions 7b and 9b and the surface of the insulating film 2 is as shown in FIG.
As shown in de and f, the size of the collector electrode 11a and the base electrode 11c is reduced by the amount that an impurity introduced region is formed and removed by oxidation.
Even if it extends over the insulating film 2, disconnection at the stepped portion can be prevented. Note that when performing multilayer wiring in which an insulating film is provided on the collector electrode 11a, emitter electrode 11b, and base electrode 11c, and other electrodes are further provided on top of the insulating film, the effect of the above-mentioned level difference is particularly large. So,
This method is effective.

Although this invention has described an example in which the impurity-introduced region and the oxidized region are provided in both the single-crystal semiconductor region and the polycrystalline semiconductor region, essentially the impurity-introduced region is provided only in the polycrystalline semiconductor region in which the external region is formed. The object is achieved by providing an oxidized region and removing this oxidized region.

As explained above, this invention provides an impurity-introduced region in a polycrystalline semiconductor region formed on an insulating film, oxidizes the surface of the region to form an oxidized region, removes the oxidized region, and removes the remaining polycrystalline semiconductor region. The base region and collector region are formed in the crystalline semiconductor region, and electrodes are provided that connect to the surfaces of the polycrystalline base region and collector region and extend on the insulating film, resulting in reliability with extremely little disconnection due to electrode steps. It is possible to manufacture semiconductor devices with high performance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional method for manufacturing a semiconductor device in order of steps, and FIG. 2 is a sectional view showing a method of manufacturing a conventional semiconductor device in order of steps. In the figure, 1 is a semiconductor substrate, 1a is a surface region, 2 is an insulating film, 2a is an opening, 5a is a single crystal semiconductor region, 5b is a polycrystalline semiconductor region, 51a and 51b are impurity introduced regions, and 52 is an oxidized region , 11a, 11
b and 11c are electrodes. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A step of forming an insulating film having an opening on the surface of the semiconductor substrate so that a selected surface region of the semiconductor substrate is exposed, a step of forming an insulating film having an opening on the surface region and the insulating film, which is the same as that of the semiconductor substrate. A step of forming a single crystal semiconductor region in the surface region and a polycrystalline semiconductor region on the insulating film by growing a material, and introducing impurities from at least the surface of the polycrystalline semiconductor region to form the polycrystalline semiconductor region. a step of forming an impurity-introduced region thinner than the thickness of the impurity-introduced region, a step of oxidizing at least the impurity-introduced region to form an oxidized region, a step of removing the oxidized region, and after this step, a step of forming an impurity-introduced region on the polycrystalline semiconductor region and the insulating film. A method of manufacturing a semiconductor device, including a step of forming an existing electrode. 2. Claim 1, characterized in that impurities are introduced from each surface of the single crystal semiconductor region and the polycrystalline semiconductor region to form impurity introduced regions in each surface layer of the single crystal semiconductor region and the polycrystalline semiconductor region. A method for manufacturing a semiconductor device according to section 1.