JPS59215741A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to obtain an interelement isolating region having a flat surface and moreover formed fine by a method wherein interelement isolating grooves are formed, and an insulating material is buried in the grooves thereof. CONSTITUTION:An n<+> type buried layer 3 is formed on a p type Si substrate 1, and an n type epitaxial layer 4 is grown thereon. After an Si film 5 is grown on the surface, the parts to act as the active regions of elements are covered with a photo resist 9. Then the film 5, the layer 4 and the layer 3 are etched using the resist 9 as a mask to form interelement isolating grooves 18. Then p<+> type channel cut regions 19 are formed. Then the resist 9 is removed, and after an Si oxide film 5a is formed on the surface, an insulating film 20 is deposited. Then a solution type insulator 21 is applied. The surface is flattened completely in such a way. After then, the film 21 is calcined to be converted into an Si oxide film by performing heat treatment. Then the flattened film 20 and the Si oxide film obtained by calcining the film 21 are etched. Thus the interelement isolating region of structure buried with the Si oxide films in the grooves 18 is completed. Accordingly, a bird beak and a level difference are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to the formation of isolation regions between elements of a semiconductor integrated circuit.

[Prior art]

Currently, as an element isolation method for semiconductor integrated circuits, the oxide film isolation method, in which elements are separated by a thermal oxide film, has replaced the conventional pn junction isolation method, and is now used in high-speed, high-density silicon integrated circuits. It has been widely used.

The manufacturing process of oxide film isolated transistors for high-speed, high-density bipolar LSIs formed using this oxide film separation method is explained below.
1(A) to (r,>) First, as shown in FIG. 1(4), one main layer of a p-type silicon substrate fi An oxide film (2) is formed on the surface, and then a part of the oxide film (2) is removed by photolithography and etching to form a hole, as shown in FIG. 1CB). part to n
Antimony (SB) or arsenic (As), which is to become a shaped buried layer (3), is ion-implanted to form an ion-implanted layer (3). Next, as shown in FIG. 1(0), oxidation and drive diffusion of the implanted ions are performed to form an oxide film (2a) and an n+ type buried layer (3a). Thereafter, as shown in FIG. 1(D), the oxide film (2a) is removed and an n-type epitaxial layer (4) having a relatively low impurity concentration (~10 cxn) is grown. At this time, vertical autodoping occurs, and the n+ type buried layer becomes 9 as shown in (3b), and the n- type layer (4) located above it has a slightly thinner effective thickness than that in other regions. Become. Next, Figure 1 (
As shown in FIG. 1, an underlying oxide film (5) and an oxidation-resistant insulating film (6) are formed, and a semiconductor region that is to become an element such as a transistor or wiring, that is, an n+ type buried layer (in FIG. 1) is formed.
3b) The underlying oxide film (5) and the oxidation-resistant insulating film and film (6) are removed from the parts other than the upper part. After that, Figure 1C
As shown in F), the n-type epitaxial layer (4) is etched using the underlying oxide film (5) and the oxidation-resistant insulating film (6) as a mask, and boron (B) is ion-implanted to form a p-type layer.
Form a +-shaped channel cut region (7). Next, as shown in FIG. 1(), selective oxidation is performed to form an insulating oxide film (8), and the oxidation-resistant insulating film (6) and underlying oxide film (5) are removed. Next, as shown in FIG. 1 (I), the area other than the base region is covered with a resist (9), and boron (B) ions are implanted to form a p+ type active base region (lO).Similarly, as shown in FIG. ) to extend the p++ type inactive base region (11) to a p+ type resist film (9a).
It is also possible to form the active region with a higher concentration than +101. After that, as shown in Figure 1 (, r),
(9a) is removed, the semiconductor surface is covered with an oxide film (8a) by OVD method, and in this state, drive diffusion is performed on these p+ type active base regions [101] and p++ type inactive base regions (101).Next, , as shown in Figure 1 (2), remove the oxide film at the base, emitter, and collector contact areas, cover only the area that will become the base contact with resist (12+), and remove As from the other oxide film removed areas.
was ion-implanted to form n+ type emitter regions (131 and n
A +-shaped collector region θ Shu is formed at the same time. Next, the resist θ powder is removed, and after ion implantation, As is annealed.

As shown in FIG. 1 (L), the base electrode 05 and the emitter electrode (
IQ), Collector! T! A bipolar transistor is formed by forming iθno.

In a bipolar transistor with a conventional insulation film isolation structure as described above, transistors or other elements are isolated by an n+ type buried layer (3b), a p+ type channel cut region (7), and an insulation film isolation (8b). , p-n
Compared to isolation, base-collector junction capacitance (cT
C) and collector/substrate, plate junction capacitance (0, s) M distortion can be reduced to 1/2 or less, 5/6 or less.

Ja Upper (7) As mentioned above, in a transistor with an oxide film isolation structure, the area of the transistor itself can be reduced.

However, as shown in FIG. 2, the element isolation oxide film (8b) invades the transistor region over the width W, creating a so-called bird's beak, and the edge of the oxide film has a cylindrical shape H (7b) called a bird's head. ) W difference occurs, electrode wiring,
Particularly when wiring multiple N electrodes, failures such as 5-wire disconnections are avoided.

Furthermore, since the formation of the isolation oxide film requires thermal oxidation at high temperatures and for a long time, crystal defects in the semiconductor occur and the impurity distribution in the buried collector is redistributed, resulting in the base-collector junction capacitance it (0,.

), which had drawbacks such as an increase in

[Summary of the invention]

The present invention has been made in view of the above points, and instead of forming an inter-element isolation oxide film by selective oxidation, it is possible to form an inter-element isolation groove and fill this flit with an insulating material. The present invention provides a method for manufacturing a semiconductor integrated circuit device that has low internal stress, has a flat surface, and can form fine isolation regions.

[Embodiments of the invention]

FIGS. 3(A) to 3(1) are cross-sectional views showing the state of one embodiment of the present invention at the royal process stage. Figure 3 ω
Relatively low impurity concentration (~10”cm-3) as shown in
sb+ or As'' on the entire surface of the p-type silicon substrate +11
ion implantation to form a diffusion layer (3
) to form. Next, as shown in FIG. 3(B), an n-type epitaxial layer (4) with a relatively low impurity concentration (~10151015a) is grown.
After growing a thin silicon oxide film (5) on the surface as shown in FIG. 3, a photoresist (9) is applied using photolithography to cover the area that will become the active region of the device.

Next, as shown in FIG. 3(D), the silicon oxide film fb+, the n-type epitaxial layer (4), and the n+-type buried layer (3) are etched using the photoresist (9) as a mask to isolate the elements. Form the end of the groove. At this time, in order to suppress the lateral inward expansion of etching 9, it is preferable to use reactive ion etching to form the groove (18) anisotropically with substantially vertical sidewall surfaces.

Next, as shown in FIG.
A p+ type channel cut region (19) is formed by ion implantation. With these ions, unlike in the case of conventional oxide film separation, the effect of sucking out impurities accompanying the formation of a thick silicon oxide film is almost negligible, so the ion implantation force can be made considerably smaller than in the conventional method. Next, as shown in No. 31), the photoresist (9) is removed,
After growing a thin silicon oxide film (5a) on the surface,
Deposit an insulating film, such as a silicon oxide film. It is preferable that the thickness of the insulating film (e) is approximately the same as the depth of the end of the trench for isolation between elements. For depositing the insulating HA (go), a method of depositing a silicon oxide film or a phosphorus glass film using the CVD method, which has excellent step coverage, can be used. Alternatively, it is also possible to deposit the silicon oxide film using an RF sputtering method with a substrate bias applied, which can make the shape of the stepped portion tapered. Next, as shown in Figure 3 (()),
Sieve liquid? An insulating material (2ρ, such as organo-silanol dissolved in an organic solvent, etc., is spin-coated. In this way,
The step part of the isolation groove between elements (+insulating film formed along the barrel) is filled with organo-silanol (2+), and the surface becomes completely flat.After this, heat treatment is performed,
The organic solvent is evaporated and the organo-silanol is baked to convert it into a silicon oxide film. Next, Figure 3 (I()
As shown in FIG. 3, the planarized silicon oxide film and the silicon oxide film obtained by firing the organo-silanol (21) are etched. During this etching, by using plasma etching or reactive ion etching, silicon oxide M (20) and organo-7
It is possible to make the etching speed equal to that of the silicon oxide film formed from ranol silicate and the U4-shaped silicon oxide film, and it is possible to etch until the silicon oxide film on the active region is completely removed while maintaining a flat surface shape. It is possible. In this way, an element isolation region having a structure in which a silicon oxide groove is buried in the element isolation groove (18) is finally completed.

After forming the insulating film 4, the base (ILII) and emitter (13 ),
Form collector contact (+4) and base electrode α5
), emitter electrode OL collector 'i! 81! (By forming lη, the formation of isolated transistors for element isolation is completed.

FIG. 4 is an enlarged cross-sectional view showing the inter-element isolation region and the vicinity of the rod in the semiconductor integrated circuit device obtained in this manner.
Since the element isolation groove (+19) filled with 20) is formed, the so-called bird's beak, which is the digging in of the silicon oxide film for element isolation, which was a drawback of the conventional oxide film isolation method, is eliminated. There is no narrowing of the width of the active region, and there is no step in the oxide film called bird's head, resulting in a completely flat surface, which is a huge advantage for miniaturization of devices. Since there is no thick oxide film, internal stress is small and leakage current can be kept low.In addition, the n
Since the depth of the inter-element isolation groove 019 can be increased to such an extent that the +-type layer (3) does not come into contact with the anti-inversion layer (I9), the junction capacitance C28 between the collector and the substrate can be reduced. This makes it possible to significantly improve the performance of devices.

In the above embodiments, a bipolar type integrated circuit was explained as an example, but even in the case of an MO8 type integrated circuit, the element isolation method according to the present invention can be adopted instead of the conventional oxide film isolation method. It goes without saying that you can do it.

〔Effect of the invention〕

As described above, according to the present invention, a vortex for separating elements is formed, an insulating film is deposited on the vortex, an insulating film is applied in the form of a bath liquid, the surface is flattened, and then the insulating film is deposited. By etching, it is possible to form grooves for isolation between elements filled with a film, so that a flat surface and a fine isolation region between elements can be obtained. It has a big effect.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing the state at each main process step to explain the manufacturing method of a bilayer integrated circuit device using the conventional oxide film separation method, and Figure 2 shows the oxide film in this conventional example. FIG. 3 is a cross-sectional view showing an enlarged separation method structure, FIG. 3 is a cross-sectional view showing the main process stages of an embodiment of the present invention, and FIG. FIG. 3 is an enlarged T-plane view showing the inter-element isolation structure in FIG. In the figure, (1) is a p-type silicon substrate (semiconductor substrate of l conductivity type), (31 is an 8-hole embedded semiconductor layer (semiconductor layer of second conductivity type), (18) is a groove for isolation between elements, ( 19) is a p+ (first conductivity) type channel cut region, (21) is an insulating film, and (21) is a solution-like insulator. In addition, the same reference numerals in the figure indicate the same or Buddhist parts. Agent: Oiwa Masuo Figure 1 Figure 1r4 Figure 1 Figure 2 J4 7 l 34 314 Figure 3 2θ ty Procedural amendment (voluntary) 1. Indication of the case Patent application No. 58-92758 3,
Relationship with the case of the person making the amendment Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent 5 Specification subject to amendment Column 6 of the Detailed Description of the Invention, Description of Contents of the Amendment, is amended as follows.

Claims (1)

[Scope of Claims] a first step of etching a portion to be an element isolation region other than the element formation region from the surface on the semiconductor layer side to form an element isolation groove reaching the semiconductor substrate beyond the pn junction; a second step of forming an insulating film with a thickness corresponding to the depth of the element isolation groove on the surface of the semiconductor substrate including the inside of the element isolation groove; a third step of applying a solution-like insulating material to fill the area and firing it; and a fourth step of etching the insulating film after the third step to a depth corresponding to the thickness of the flat part. (2) The semiconductor according to claim 1, characterized in that a silicon oxide group is formed by a CVD method as an insulating film in the second step. A method for manufacturing an integrated circuit device. (3) A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that a phosphorus glass film is formed by a CVD method as an insulating film in the second step.C4 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a silicon oxide film is formed as the insulating film in the second step by a sputtering method. (5) Use organo-silanol dissolved in an organic solvent as a solution-like insulating material in the third step! A method for manufacturing a semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the semiconductor integrated circuit device has a f-characteristic. (6) Any one of items 1 to 5 of the scope of the patent request, characterized in that impurity ions of the first conductivity type are implanted into the semiconductor substrate at the bottom of the element isolation groove as a channel cut region. A method of manufacturing the semiconductor integrated circuit device described above.