JP2002158304A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease stably sheet resistance value of a polycrystalline silicon resistor without depending on a pattern and length of the resistor, in a semiconductor integrated circuit device wherein the polycrystalline silicon resistor is formed on a LOCOS oxide film of a Bi-CMOS transistor. SOLUTION: In this semiconductor integrated circuit device, a silicon nitride film 51 on the polycrystalline silicon resistor 33 formed on the LOCOS oxide film 41 is eliminated wholly. When hydrogen annealing is performed from a BPSG film 52 deposited on elements, hydrogen enters the resistor 33 uniformly since the silicon nitride film 51 for shielding hydrogen does not exist. As a result, sheet resistance value of the resistor 33 is decreased uniformly without depending on the pattern and the length of the resistor 33 and can be stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a LOC formed for separating elements in a Bi-CMOS transistor.
The present invention relates to a semiconductor integrated circuit device that suppresses variations in a resistor by forming a resistor made of polycrystalline silicon on an OS oxide film and removing a silicon nitride film on the polycrystalline silicon resistor, and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Generally, an IC generates a voltage for detecting a current, and has a built-in resistor for generating the voltage. On the other hand, as a resistor, there are a diffusion resistor using a diffusion region and a polysilicon resistor.

The polysilicon resistor has the following advantages as compared with a diffusion resistor using a diffusion region. First
The diffusion resistor is formed in the island region surrounded by the isolation region. However, the polysilicon resistor can be arranged at an arbitrary position on the insulating layer and can be formed in an empty space. It has the advantage of being able to shrink.
Second, since the polysilicon resistor is formed on the insulating layer and can be formed without using the isolation region, there is an advantage that the parasitic capacitance due to the PN junction is suppressed and the influence of the parasitic capacitance on the circuit can be avoided. With the recent increase in the degree of integration, these two merits are regarded as important, and polysilicon resistors are receiving attention in ICs.

FIG. 13 is a cross-sectional view of a semiconductor integrated circuit using a polysilicon resistor. Here, an N-channel MOS transistor 1 and an NPN are shown from the left.
1 shows a transistor 2 and a polycrystalline silicon resistor 3.

In this semiconductor integrated circuit device, an N ⁻ type epitaxial layer 5 is laminated on a P ⁻ type semiconductor substrate 4. The epitaxial layer 5 has a first island region 7 and a second island region 8 separated by a P ⁺ type isolation region 6.
Are formed.

The first island region 7 has an N-channel MO.
The S transistor 1 has NPN in the second island region 8.
A transistor 2 is formed.

The P ⁺ -type isolation region 6 includes a P ⁺ -type isolation region 9 that diffuses vertically from the surface of the P ⁻ -type semiconductor substrate 4 and a P ⁺ -type isolation region 10 that diffuses from the surface of the epitaxial layer. It is formed by connecting people. Also,
Since the LOCOS oxide film 11 is formed on the P ⁺ type isolation region 6, isolation between elements is further achieved.

The resistor 3 made of silicon is formed on the LOCOS oxide film 11. On the resistor 3, a high-temperature thermal CVD oxide film 12, a silicon nitride film 13, and a BPSG film 14 are formed in the same manner as on the first island region 7 and the second island region 8.

An electrode is formed through a contact hole 15 to electrically connect the respective elements. FIG. 13 shows a state before the electrode is formed for explanation of a manufacturing method described below. It is a figure.

In the method of manufacturing the semiconductor integrated circuit device, first, a P ⁻ type semiconductor substrate 4 is prepared, and
An N ⁻ -type epitaxial layer 5 is laminated thereon. Then, the first and second portions separated by the P ⁺ type separation region 6 are formed.
In the island regions 7 and 8, an N-channel MOS transistor 1 and an NPN transistor 2 are formed. Also, L
Polycrystalline silicon resistor 3 is formed on OCOS oxide film 11.

On the other hand, a high-temperature thermal CVD oxide film 12, a silicon nitride film 13 and a BPSG
The films 14 are sequentially stacked. After forming a contact hole 15 for electrically connecting the elements 1, 2, and 3, the interface state of the N-channel MOS transistor 1 is adjusted through the contact hole 15. Specifically, hydrogen annealing has been performed through the contact hole 15 with the silicon nitride film 13 laid all over the surface.

[0012]

As described above, in the conventional method of manufacturing a Bi-CMOS transistor type semiconductor integrated circuit device, contact holes are prevented in order to prevent the interface state in the N-channel MOS transistor 1 from rising. After formation of 15, a hydrogen anneal is required.

However, since the silicon nitride film 13 formed on the N-channel MOS transistor 1, the NPN transistor 2, and the polycrystalline silicon resistor 3 blocks hydrogen, the hydrogen annealing step is performed in the contact hole 15
Done through. Therefore, hydrogen enters not only inside N channel MOS transistor 1 but also inside NPN transistor 2 and polycrystalline silicon resistor 3.

In particular, the polycrystalline silicon resistor 3 has a characteristic that the sheet resistance value is reduced due to hydrogen entering into the resistor 3. As a result, the sheet resistance value of the resistor 3 differs between a portion having a contact hole and a portion having no contact hole due to a difference in the amount of mixed hydrogen. That is, the sheet resistance value is largely influenced by the pattern shape of the resistor 3, the length of the resistor 3, and the like, and there is a problem that the sheet resistance value is not stable.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. In a semiconductor integrated circuit device according to the present invention, a semiconductor substrate of one conductivity type is laminated on a surface of the substrate. A reverse conductivity type epitaxial layer, a one conductivity type isolation region penetrating the epitaxial layer to form first and second island regions, and a LOCOS for isolating the first and second island regions from one another. An oxide film, a MOS transistor formed in the first island region, a bipolar transistor formed in the second island region, and the LOC
A polycrystalline silicon resistor formed on an OS oxide film, wherein an oxidation resistant film is formed on the MOS transistor formed in the first island region and the bipolar transistor formed in the second island region. The silicon nitride film formed on the polycrystalline silicon resistor is removed.

Preferably, in the semiconductor integrated circuit device according to the present invention, since the silicon nitride film is not formed on the polycrystalline silicon resistor, hydrogen in the hydrogen annealing step is applied to the entire resistor regardless of the contact hole. to go into. Therefore, the sheet resistance value of the resistor can be reduced uniformly without depending on the pattern shape, length, etc. of the resistor, and the sheet resistance value of the resistor can be stably obtained. It is characterized in that

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of preparing a semiconductor substrate of one conductivity type and a step of laminating an epitaxial layer of the opposite conductivity type on the substrate. Forming a reverse conductivity type isolation region penetrating the epitaxial layer, separating the first and second island regions, and forming the first and second islands by the reverse conductivity type isolation region penetrating the epitaxial layer. Forming an LOCOS oxide film for isolating the first island region and the second island region from each other, and forming the LOCOS oxide film.
Forming a polycrystalline silicon resistor on the OS oxide film; and forming a high temperature thermal CVD oxide film uniformly on the first island region, the second island region and the polycrystalline silicon resistor, Forming a silicon nitride film uniformly on the high-temperature thermal CVD oxide film, removing the silicon nitride film on the polycrystalline silicon resistor, forming the first island region, the second Forming an insulating film uniformly on the island region and the polycrystalline silicon resistor, forming a contact hole in the insulating film, and annealing hydrogen from above the insulating film. .

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, preferably, the silicon nitride film on the polycrystalline silicon resistor is removed. Since hydrogen enters the entire resistor without depending on the resistance, the sheet resistance value of the resistor can be made uniform and the quality of a product can be improved.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor integrated circuit device incorporating an N-channel MOS transistor 31, an NPN transistor 32 and a polycrystalline silicon resistor 33.

On a P ^- type single crystal silicon substrate 34,
An epitaxial layer 38 having a low concentration epi (ρ = 1.25 Ω · cm) and a thickness of 3.50 μm is formed. An N channel MOS is formed in the substrate 34 and the epitaxial layer 38 by a P ⁺ type isolation region 53 completely penetrating both.
First island region 54 forming transistor 31 and NP
The second island region 55 forming the N transistor 32 is electrically separated and formed.

The isolation region 53 is composed of a first isolation region 37 diffused vertically from the surface of the substrate 34 and a second isolation region 39 diffused from the surface of the epitaxial layer 38. The layer 38 is separated into islands. On the P ⁺ -type isolation region 53, the LO
By forming the COS oxide film 41, isolation between elements is further achieved. On the LOCOS oxide film 41, a polycrystalline silicon resistor 33 is formed.

Then, an N-channel MOS transistor 31, an NPN transistor 32 and a polycrystalline silicon resistor 33 are formed, and a high-temperature thermal CVD oxide film (HTO film) 50 A silicon nitride film 51 is formed. Then, the silicon nitride film 51 formed on the polycrystalline silicon resistor 33 is formed.
Has been removed by a known photolithography technique. Further, a BPSG (Boron Phospho Silicon) is formed on the entire surface of the silicon nitride film 51 as an insulating film.
(Cate Glass) film 52 is formed. A contact hole 56 is formed for electrically connecting the respective elements 31, 32, 33, and an electrode 57 is formed here.

The high-temperature thermal CVD oxide film 50 has a thickness of about 0.04 to 0.06 μm, the silicon nitride film 51 has a thickness of about 0.025 to 0.035 μm, and the BPSG film 52 has a thickness of about 0.9 to 0.035 μm. It is formed by deposition of about 1.0 μm.

As described above, in the semiconductor integrated circuit device of the present invention, after the silicon nitride film 51 on the polycrystalline silicon resistor 33 is removed, the BPSG film 5 is formed as an insulating film on the entire surface.
2 are formed. Therefore, hydrogen from the hydrogen annealing step for preventing the interface state of the N-channel MOS transistor 31 from rising is penetrated into the entire resistor 33 through the BPSG film 52. As a result, the sheet resistance value of the resistor 33 can be reduced uniformly without being influenced by the pattern shape, the length, and the like of the resistor 33, and a stable value can be obtained.

In FIG. 1, the polycrystalline silicon resistor 33 is shown.
Although the structure in which only the upper silicon nitride film 51 is removed has been described, as shown in FIG.
A structure in which the silicon nitride film 51 on the second and polycrystalline silicon resistors 33 is removed may be used.

In the NPN transistor 32, hydrogen by hydrogen annealing enters the inside of the device. This hydrogen electrically activates impurities in a thermally non-equilibrium state by ion implantation.
The linearity of is improved. At this time, since the size of the NPN transistor 32 is smaller than that of the resistor 33 and is formed in a fixed shape, the amount of hydrogen entering through the contact hole 56 is sufficient. Therefore, there is no particular problem even if the silicon nitride film 51 is formed on the NPN transistor 32 as shown in FIG.

However, as in the structure shown in FIG.
With the structure in which the silicon nitride film 51 on the N transistor 32 is removed, the characteristics of the NPN transistor 32 are not disturbed by the thermal stress of the silicon nitride film 51, and hydrogen is uniformly introduced over the entire surface. A structure in which the annealing step functions more effectively is obtained.

Next, a method of manufacturing the semiconductor integrated circuit device of the present invention shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 3, a P ⁻ -type single-crystal silicon substrate 34 is prepared, the surface of the substrate 34 is thermally oxidized to form an oxide film, and an oxide film corresponding to the buried layer 35 is formed. Photo-etched to make a selective mask. Then, arsenic (A) forming an N ⁺ type buried layer 35 on the surface of the substrate 34 is formed.
s).

Next, as shown in FIG.⁺Type embedding
Layer 36 and P⁺Forming a first isolation region 37 of the mold;
Then, ion implantation is performed. In FIG. 3, as a selection mask
After removing all the used oxide film, a known photolithography is performed.
P by technology⁺Mold buried layer 36 and P⁺The first of the mold
In which an opening is provided in a portion where the isolation region 37 is formed.
Photoresist (not shown) as a selection mask
You. Then, a P-type impurity such as boron (B) is
Energy 160 keV, introduction amount 1.0 × 10 ¹⁴/ C
m^TwoIon implantation. Then remove the photoresist
I do.

Next, as shown in FIG. 5, after removing the oxide film entirely, the substrate 34 is placed on a susceptor of an epitaxial growth apparatus,
C. and a SiH ₂ Cl ₂ gas and a H ₂ gas introduced into the reaction tube to obtain a low-concentration epi (ρ =
An epitaxial layer 38 having a thickness of 1.25 Ω · cm and a thickness of 3.50 μm is grown. Then, the surface of the epitaxial layer 38 to form an oxide film by thermally oxidizing, opening the portion forming the second isolation region 39, P ⁺ -type well region 40 of P ⁺ type by a known photolithography technique Is formed as a selection mask using a photoresist (not shown) provided with. Then, a P-type impurity, for example, boron (B) is ion energy of 40 keV, and an introduction amount of 3.0 × 10 ¹³ / cm.
Perform ion implantation in step ² . After that, the photoresist is removed. At this time, the N ⁺ type buried layer 35, the P ⁺ type buried layer 36, and the P ⁺ type first isolation region 37 are simultaneously diffused.

Next, as shown in FIG. 6, to diffuse the second isolation region 39, P ⁺ -type well region 40 of the ion implanted P ⁺ -type 5, first and second separation The regions 37 and 39 are connected to form a P ⁺ type separation region 53. Further, the P ⁺ -type well region 40 of the N-channel MOS transistor 31 formed in the first island region 54
And the P ⁺ type buried layer 36 are connected.

Then, a heat treatment is applied to the entire substrate 34 while forming an oxide film by steam oxidation at about 1000 ° C.
By forming the LOCOS oxide film 41 on the P ⁺ -type isolation region 53, isolation between elements is further achieved. here,
LOCOS oxide film 41 is formed to a thickness of about 0.7 to 0.8 μm.

Next, as shown in FIG. 7, amorphous silicon 49 is deposited on the entire surface of the device, and a P-type impurity, for example, boron fluoride (BF) is ion-energized at 60 keV and the introduced amount is 3.0 × 10 3 from the surface. Ion implantation is performed at ¹⁴ / cm ² . The resistance of the polycrystalline silicon resistor 33 is determined by the boron fluoride (BF). Then, a silicon oxide film (not shown) is deposited on the amorphous silicon 49 to a thickness of about 0.01 μm, diffused at 850 ° C. for about 1 hour, and the silicon oxide film is entirely removed.

Thereafter, the resistor 33 is formed on the LOCOS oxide film 41 by selectively removing the photoresist (not shown) as a mask by a known photolithography technique.

Next, as shown in FIG.
In FIG. 4, a silicon oxide film 47 is deposited as a gate of the N-channel MOS transistor 31 by about 0.02 μm, and a polycrystalline silicon 48 is deposited by about 0.4 μm. Then, by using the polycrystalline silicon 48 and the LOCOS oxide film 41 as a mask, an N ⁺ type impurity, for example, phosphorus (P), for example, phosphorus (P) is ion energy 40 ke in the N ⁺ type diffusion regions 42 and 43 of the N channel MOS transistor 31.
V ions are implanted at a dose of 1.75 × 10 ¹³ / cm ² . As a result, the N-channel MOS transistor 31 is completed.

Next, as shown in FIG.
5, the collector leading region of the NPN transistor 32 is set to N ⁺
The NPN transistor 32 is completed by forming the emitter region by the N ⁺ type diffusion region 46 and the base region by the P type diffusion region 44 by the type diffusion region 45. Here, using a photoresist (not shown) as a mask by a known photolithography technique, the N ⁺ -type diffusion regions 45 and 46 are formed by introducing an N-type impurity, for example, arsenic (As) with an ion energy of 100 keV and a dose of 5 0.0 × 10 ¹⁵ /
It is formed by ion implantation of cm ² . P-type diffusion region 4
4 is formed, for example, by ion implantation of boron fluoride (BF) with an ion energy of 60 keV and an introduction amount of 5.0 × 10 ¹⁴ / cm ² .

Next, as shown in FIG. 10, after an N-channel MOS transistor 31, an NPN transistor 32 and a polycrystalline silicon resistor 33 are formed, these elements are placed, for example, at 790 ° C. for about 2 hours. The high temperature thermal CVD oxide film 50 is formed to a thickness of 0.04 to
It is deposited by about 0.06 μm. On the high-temperature thermal CVD oxide film 50, for example, a silicon nitride film 51 having a thickness of 0.0
Deposition is performed on the order of 25 to 0.035 μm.

Next, as shown in FIG. 11, the silicon nitride film 51 formed on the polycrystalline silicon resistor 33 is removed by a known photolithography technique using a photoresist (not shown) as a mask. You. After the photoresist is removed, BPSG (Boron Phospho Si) is formed as an insulating film on the entire surface of these devices.
(Limit Glass) film 52 has a thickness of 0.9-1.
It is formed by deposition of about 0 μm.

Next, as shown in FIG.
The SG film 52 is heat-treated at 800 to 1000 ° C. for about 15 minutes to flatten the film surface. Thereafter, a contact hole is formed to electrically connect the respective elements. Then, hydrogen annealing is performed using the contact hole or the like, for example, at 420 ° C. for about one hour.

At this time, in the step of performing hydrogen annealing, since the silicon nitride film 51 on the polycrystalline silicon resistor 33 has been entirely removed in the previous step, hydrogen is supplied to the entire resistor 33 regardless of the presence or absence of the contact hole. Enter evenly.
Therefore, hydrogen enters uniformly without depending on the pattern shape of the resistor 33 and the length of the resistor 33, and the sheet resistance of the resistor 33 is stabilized, thereby improving the quality of the product. is there.

[0043]

According to the present invention, in a semiconductor integrated circuit device, a BPSG film is formed as an insulating film over the entire surface after a silicon nitride film on a polycrystalline silicon resistor formed on a LOCOS oxide film is removed. ing. Therefore, hydrogen from the hydrogen annealing process for preventing the interface level of the N-channel MOS transistor from rising is uniformly penetrated into the entire resistor through the BPSG film. As a result, the sheet resistance value of the resistor can be reduced uniformly without being affected by the pattern shape and length of the resistor, and a stable value can be obtained.

According to the present invention, in the method of manufacturing a semiconductor integrated circuit device, in the step of performing hydrogen annealing, since the silicon nitride film on the polycrystalline silicon resistor has been entirely removed in the previous step, the presence or absence of the contact hole Regardless of the hydrogen, the hydrogen enters the entire resistor uniformly. As a result, the hydrogen is not uniformly introduced into the resistor than the resistor pattern or the resistor length, so that hydrogen enters the resistor uniformly, and the sheet quality of the resistor is stabilized, thereby improving the product quality. It is a process.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 2 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 4 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 6 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 7 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 8 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 9 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 10 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 11 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 12 is a sectional view illustrating the method for manufacturing the semiconductor integrated circuit device of the present invention.

FIG. 13 is a cross-sectional view illustrating a conventional semiconductor device.

Continued on front page F term (reference) 5F038 AR07 AR09 EZ14 EZ16 EZ17 EZ20 5F048 AA00 AC05 AC10 BA07 BA12 BB05 BE03 BF00 BG12 BH01 CA03 CA07 DA00 5F082 AA11 AA21 BA02 BA04 BC01 BC09 BC15 DA10 EA32 EA36 EA45

Claims (6)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of a reverse conductivity type laminated on a surface of the substrate, and a semiconductor substrate of one conductivity type penetrating the epitaxial layer to form first and second island regions. An isolation region, and a LOCO for isolating the first and second island regions from each other.
An S oxide film; a MOS transistor formed in the first island region; a bipolar transistor formed in the second island region; and a polycrystalline silicon resistor formed on the LOCOS oxide film. An oxidation resistant film is formed on the MOS transistor formed in the first island region and the bipolar transistor formed in the second island region, and the silicon nitride film on the polycrystalline silicon resistor is removed. And a semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein an oxidation-resistant film on said bipolar transistor formed in said second island region has been removed. 3. The semiconductor integrated circuit device according to claim 1, wherein said oxidation resistant film is a silicon nitride film. A step of preparing a semiconductor substrate of one conductivity type; a step of laminating an epitaxial layer of a reverse conductivity type on the substrate; and a first and a second isolation region penetrating the epitaxial layer. Forming a second island region, forming a LOCOS oxide film for isolating the first island region and the second island region from each other, and forming a polycrystalline silicon resistor on the LOCOS oxide film Forming a high-temperature thermal CVD oxide film on the first island region, the second island region, and the polycrystalline silicon resistor, and forming an oxidation-resistant film on the high-temperature thermal CVD oxide film Removing the oxidation-resistant film on the polycrystalline silicon resistor; forming an insulating film on the first island region, the second island region, and the polycrystalline silicon resistor; Work to form contact holes in the film And a step of performing hydrogen annealing on the insulating film. 5. The method according to claim 4, wherein the oxidation-resistant film is a silicon nitride film. 6. The insulating film is made of BPSG (Boron).
5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the method is made of Phospho Silicate Glass.