JPH0579184B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an integrated circuit, and more particularly to a method of manufacturing a polycrystalline silicon resistive element.

[Conventional technology]

Conventionally, this type of manufacturing method has included a step of growing a polycrystalline silicon film, a step of introducing impurities to determine the resistance value, a step of patterning the polycrystalline silicon film into a predetermined shape, and a step of growing an interlayer insulating film. The method consisted of the steps of forming contact holes in the interlayer insulating film for drawing out the wiring, growing and patterning the wiring metal, and growing a surface protection film.

[Problem that the invention seeks to solve]

In the conventional integrated circuit manufacturing method described above,
As the surface protection film, an SiN film produced by plasma CVD method (hereinafter referred to as plasma deposited SiN film) is used. This is due to the excellent moisture resistance, alkali ion blocking effect, and mechanical strength of the plasma deposited SiN film. However, since plasma deposited SiN films contain 10 to 40 atomic percent (a/o) hydrogen, it is known that this hydrogen diffuses into the polycrystalline silicon film. Since this hydrogen passivates the dangling bonds of silicon in the polycrystalline silicon film, the conductivity increases and the resistance value becomes lower than the designed value.

One way to solve this problem is to cover the polycrystalline silicon resistance element with a Si ₃ N ₄ film formed by low-pressure CVD, and block the diffused hydrogen with the dense Si ₃ N ₄ film. There is something that says.
However, this method also has the disadvantage that the growth and patterning of the Si ₃ N ₄ film and its patterning process are lengthy. Also, although the blocking effect is effective, it has the drawback that it is not perfect.

[Means for solving problems]

In the method for manufacturing an integrated circuit according to the present invention, after forming a polycrystalline silicon film, a silicon nitride film is formed by a plasma CVD method and heat treatment is performed, or the polycrystalline silicon film is exposed to a plasma atmosphere containing hydrogen to diffuse hydrogen. This process includes a step of saturating the dangling bonds of silicon in the silicon, and a step of introducing a predetermined impurity to form a polycrystalline silicon resistance element.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1E are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.

First, as shown in Figure 1a, a MOS FET is formed using a normal manufacturing method, and then a polycrystalline silicon film 3 for forming a resistor is grown to a thickness of 200 to 600 nm using a low pressure CVD method. do. Next, the first
_{As shown} in _{FIG .}
The polycrystalline silicon film 3 is grown to a thickness of ~500 nm, and heat treated at 300~700°C in an _N2 atmosphere for 30 minutes~3 hours to diffuse hydrogen into the polycrystalline silicon film 3. Next, as ^{shown in} FIG.
Implantation is performed under the conditions of 150keV and 1×10 ¹³ to 5×10 ¹⁴ cm ⁻² to introduce impurities that determine the resistance value. next,
As shown in FIG. 7d, the polycrystalline silicon film 3 is patterned into a predetermined shape by photolithography, and then patterned to a thickness of 0.5 to 1.5 μm by atmospheric pressure CVD.
Phosphorsilicate glass (PSG) with a thickness of After performing a PSG flow to smooth the level difference in the base, a contact hole 9 is opened using photolithography technology. Next, as shown in FIG. 1d, an Al film with a thickness of 0.5 to 1.0 μm is formed by a sputtering method, and patterned using photolithography to provide electrode wirings 10 and 11 and resistive elements 12. form. As the surface protection film 13, a plasma-deposited SiN film is used at 0.1
A bonding pad (not shown) is grown using photolithographic techniques.

Hydrogen in the plasma-deposited SiN film 6 diffuses into the polycrystalline silicon film 3 by heat treatment and saturates the dangling bonds, so the hydrogen in the surface protection film 13 does not affect the resistance value of the resistance element 12.

FIG. 2 is a schematic diagram of a plasma reactor for explaining a second embodiment of the present invention.

This embodiment differs from the first embodiment described above only in the method of introducing hydrogen into the polycrystalline silicon film, and all other steps are the same. To introduce hydrogen into a polycrystalline silicon film, after growing the polycrystalline silicon film, raise the substrate temperature to 300 to 400°C.
Just expose it to NH ₃ plasma.

This embodiment has the advantage of simplifying the process since no special heat treatment is required.

〔Effect of the invention〕

As explained above, the present invention introduces hydrogen into a polycrystalline silicon film in advance to saturate the silicon dangling bonds in the polycrystalline silicon film, and then performs ion implantation to determine the resistance value. By forming a resistive element using a plasma-deposited SiN film as a surface protection film, it is possible to suppress fluctuations (decrease) or variations in resistance to a small level, thereby improving the characteristics and reliability of integrated circuits. be.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views of a semiconductor chip arranged in the order of steps for explaining a first embodiment of the present invention, and FIG. 2 is a diagram showing a plasma reaction for explaining a second embodiment of the present invention. FIG. 2 is a schematic diagram of the device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Silicon oxide film, 3... Polycrystalline silicon film, 4... Gate electrode, 5a... Source region, 5b... Drain region, 6... Plasma deposited SiN film, 7 …… ³¹ P ⁺ , 8
...Interlayer insulating film, 9...Contact hole, 10,1
1... Electrode wiring, 12... Resistance element, 13... Surface protective film, 14... Plasma reaction device, 15, 1
6... Electrode.

Claims (1)

[Claims] 1. A step of forming a polycrystalline silicon film, and forming a silicon nitride film on the polycrystalline silicon film by a plasma CVD method and performing heat treatment to diffuse hydrogen from the silicon nitride film into the polycrystalline silicon film, or a step of exposing the polycrystalline silicon film to a plasma atmosphere containing hydrogen to diffuse hydrogen into the polycrystalline silicon film to saturate silicon dangling bonds in the polycrystalline silicon film; and forming a polycrystalline silicon resistance element by introducing an impurity into the integrated circuit.