JPH07283323A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form such gate electrode wiring that a gate oxide film below an N-type polycrystalline silicon film is not etched by leaving an alloy film of a metal having a high melting point only on the N-type polycrystalline silicon film by photoetching after forming the alloy film on the entire surface of a semiconductor substrate. CONSTITUTION:After forming a gate oxide film 8 and polycrystalline silicon film on a semiconductor substrate 1, an N-type polycrystalline silicon film 10 and P-type polycrystalline silicon film 11 are formed by adding impurities to the polycrystalline silicon film. Then, after forming an alloy filnt 13 of a metal having a high melting point is formed on the entire surface of the substrate 1, the alloy film 13 is left only on the silicon film 10 by photoetching and gate electrode wiring is formed by photoetching. Consequently, the unnecessary exposure of the gate oxide film 8 below the silicon film 10 to an etching atmosphere can be suppressed after the silicon film 10 having a high etching rate is removed. Therefore, the reliability of a semiconductor device against element characteristics can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate electrode wiring material formed on a gate oxide film of a semiconductor substrate.

[0002]

2. Description of the Related Art A gate electrode wiring is an electrode wiring formed on a gate oxide film for applying a voltage for driving an element formed on a semiconductor substrate.

The gate electrode wiring includes a polycrystalline silicon film (hereinafter referred to as an N-type polycrystalline silicon film) doped with an impurity of N type conductivity type and an impurity of P type conductivity type on the same semiconductor substrate. When a polycrystalline silicon film added with is mixed (hereinafter referred to as a P-type polycrystalline silicon film) in a mixed form, the materials have different etching rates under the same etching condition.

Therefore, in the processing of the gate electrode wiring for collectively etching the N-type polycrystalline silicon film and the P-type polycrystalline silicon film, the etching of the N-type polycrystalline silicon film having a high etching rate is performed by the P-type polycrystalline silicon film. The process ends at the stage before the etching of the crystalline silicon film ends.

Therefore, the gate oxide film, which is the lower layer of the etched N-type polycrystalline silicon film, is exposed to the etching atmosphere until the etching of the P-type polycrystalline silicon film is completed.

As a result, when the gate oxide film is thin, the gate oxide film is completely removed and the device is damaged.

A conventional method for forming gate electrode wiring is shown in FIG.
~ It demonstrates using FIG. 1 to 11 are cross-sectional views showing a conventional method of forming a gate electrode wiring in the order of steps.

First, as shown in FIG. 1, a P type diffusion layer (hereinafter referred to as a P well) 2 having a low impurity concentration and an N type diffusion layer (hereinafter referred to as a P type diffusion layer) are formed on a semiconductor substrate 1 by an ion implantation method and a thermal diffusion method. (Referred to as N-well) 3. Further, the pad oxide film 4 is formed by a thermal oxidation method in an oxygen atmosphere.

Next, as shown in FIG. 2, the pad oxide film 4 is formed.
A silicon nitride film 5 is formed thereon by a chemical vapor deposition method (hereinafter referred to as a CVD method).

Next, a photoresist 6 is formed on the entire surface by a spin coating method, exposed by using a predetermined photomask, and developed to pattern the photoresist 6, and the photoresist 6 is used as an etching mask to form a silicon film by a dry etching method. The nitride film 5 is formed on the element region.

Next, as shown in FIG.
Then, the field oxide film 7 is formed by the thermal oxidation method using the silicon nitride film 5 as an oxidation resistant film.

Next, as shown in FIG. 4, the silicon nitride film 5 is removed, and further the pad oxide film 4 under the silicon nitride film 5 is removed.

Next, as shown in FIG. 5, a gate oxide film 8 is formed on the semiconductor substrate 1 having the field oxide film 7 formed thereon by a thermal oxidation method. Then, a polycrystalline silicon film 9 is formed on the entire surface by a CVD method to have a predetermined film thickness.

Next, as shown in FIG.
Is formed on the entire surface by a spin coating method, exposed by using a predetermined photomask, and developed to remove the photoresist 6 in the region where the N-type polycrystalline silicon film 10 is formed.

Thereafter, using the photoresist 6 as an etching mask, an N-type impurity typified by phosphorus is added by ion implantation to a region of the polycrystalline silicon film 9 which is not covered with the photoresist 6. Then photoresist 6
To remove.

Next, as shown in FIG. 7, a photoresist 6 is formed on the entire surface by a spin coating method, exposed by using a predetermined photomask, and subjected to a developing process to form a region where a P-type polycrystalline silicon film 11 is to be formed. The photoresist 6 is removed.

Thereafter, using the photoresist 6 as a mask, a region of the polycrystalline silicon film 9 which is not covered with the photoresist 6 is doped with a P-type impurity typified by boron by an ion implantation method. Then, the photoresist 6 is removed.

Next, as shown in FIG. 8, a photoresist 6 is formed on the entire surface by a spin coating method, exposed using a predetermined photomask, and developed to pattern the photoresist 6 into the shape of a gate electrode wiring.

Next, as shown in FIG. 9, the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 are collectively processed as a gate electrode wiring by anisotropic etching using the photoresist 6 as an etching mask. Then, the photoresist 6 is removed.

A case where the gate electrode wiring has a polycide structure which is a laminated structure of a polycrystalline silicon film and a refractory metal film or a polycrystalline silicon film and a refractory metal silicide film will be described with reference to FIG. In the following description, a polycrystalline silicon film and a refractory metal silicide film will be described as an example. A refractory metal silicide film 12 is formed by a sputtering method on the semiconductor substrate 1 on which the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 are formed.

Thereafter, a photoresist 6 is formed on the entire surface of the refractory metal silicide film 12 by a spin coating method, exposed by using a predetermined photomask, and developed to perform patterning of the photoresist 6 into a gate electrode wiring shape. To do.

Then, as shown in FIG. 11, anisotropic etching is performed using the photoresist 6 as an etching mask.
The N-type polycrystalline silicon having the refractory metal silicide film 12 formed thereon and the P-type polycrystalline silicon are collectively processed as a gate electrode wiring. Then, the photoresist 6 is removed.

[0023]

According to the conventional manufacturing method described with reference to FIGS. 1 to 11, the N-type polycrystalline silicon film 10 is used.
And the P-type polycrystalline silicon film 11 are simultaneously processed by anisotropic etching.

At this time, the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 have different etching rates.

Therefore, the etching of the N-type polycrystalline silicon film 10 having a high etching rate is completed at a faster stage than the P-type polycrystalline silicon film 11.

The gate oxide film 8 below the N-type polycrystalline silicon film 10 removed by etching is exposed to the etching atmosphere until the etching of the P-type polycrystalline silicon film 11 is completed.

Therefore, when the polycrystalline silicon film 9 is etched under the dry etching condition with poor selectivity when etching with the gate oxide film 8, as shown in FIGS. 9 and 11, it is removed by etching. Of the gate oxide film 8 below the N-type polycrystalline silicon film 10 in the predetermined region
Is excessively etched.

When the gate oxide film 8 is thin, the gate oxide film 8 under the N-type polycrystalline silicon film 10 in a predetermined region removed by etching is completely removed, and a shallow diffusion layer is formed in a later step. Etching is performed up to region 1. As a result, the semiconductor device has a problem of increased leakage current.

The object of the present invention is to solve the above problems by providing N
It is possible to process the P-type polycrystalline silicon film and the P-type polycrystalline silicon film in the same etching time, and the gate oxide film under the N-type polycrystalline silicon film in a predetermined region removed by dry etching is excessive. Another object of the present invention is to provide a method of forming a gate electrode wiring which is not etched.

[0030]

In order to solve the above-mentioned object, the method of forming a gate electrode wiring of the present invention adopts the following steps.

A method of manufacturing a semiconductor device in which a gate electrode wiring is formed on a semiconductor substrate is as follows.
A step of forming a well, a step of forming a field oxide film by selective oxidation, a step of forming a gate oxide film and a polycrystalline silicon film, and an impurity addition to the polycrystalline silicon film,
A step of forming an N-type polycrystalline silicon film and a P-type polycrystalline silicon film, a refractory metal alloy film is formed on the entire surface, and a refractory metal alloy film is formed only on the N-type polycrystalline silicon film by photoetching. And a step of forming a gate electrode wiring by photoetching, a step of forming an N-type diffusion layer and a P-type diffusion layer to be a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned, The method is characterized by including a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a step of forming a wiring connected to the semiconductor substrate through the contact hole.

[0032]

In the processing of the gate electrode wiring by anisotropic etching, the etching rates of the N-type polycrystalline silicon film and the P-type polycrystalline silicon film are largely different, and the etching rate of the N-type polycrystalline silicon is faster.

The etching rate of the thin refractory metal alloy film formed on the upper layer of the N-type polycrystalline silicon film is sufficiently lower than the etching rates of the N-type polycrystalline silicon film and the P-type polycrystalline silicon film.

From this, a thin refractory metal alloy film having a controlled film thickness is formed on the N-type polycrystalline silicon film.

Therefore, the apparent etching rate (etching time) of the N-type polycrystalline silicon film having the thin high-melting-point metal alloy film formed thereon can be made approximately the same as that of the P-type polycrystalline silicon film. it can.

As described above, in the method for forming a gate electrode wiring according to the present invention, the N-type polycrystalline silicon film region and the P-type polycrystalline silicon film region are mixed on the same semiconductor substrate,
In addition, when the gate oxide film is thin, it is possible to correct the difference in etching time due to the difference in the impurity added to the polycrystalline silicon film during etching.

That is, after the N-type polycrystalline silicon film having a high etching rate is removed, it is possible to prevent the gate oxide film as the underlying layer from being unnecessarily exposed to the etching atmosphere.

Therefore, the reliability with respect to the device characteristics can be improved as compared with the case of using the conventional method of forming the gate electrode wiring.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device, which is a method of forming a gate electrode wiring material in an embodiment of the present invention, will be described below with reference to the drawings. 1 to 7 and 12 to 16 are cross-sectional views showing a method of forming a gate electrode wiring in the embodiment of the present invention in the order of steps.

First, as shown in FIG. 1, 10 ¹³ atoms / cm ^{2 of} boron, which is a P-type impurity, is contained in the semiconductor substrate 1.
About 10 ¹² atoms / cm 3 of phosphorus, which is an N-type impurity
An ion implantation amount of about ^{2 is} added to each of the predetermined regions by the ion implantation method.

Then, a temperature of 114 in a nitrogen atmosphere is used.
P well 2 and N well 3 are formed in semiconductor substrate 1 by thermal diffusion at 0 ° C.

Further, a pad oxide film 4 having a film thickness of 40 nm is formed by an oxidation treatment at a temperature of 1000 ° C. in an oxygen atmosphere.

Next, as shown in FIG. 2, the pad oxide film 4 is formed.
As a reaction gas, dichlorosilane (SiH ₂ Cl
₂ ) and a silicon nitride film 5 having a film thickness of 150 nm is formed by a CVD method using ammonia (NH ₃ ).

Next, a photoresist 6 is formed on the entire surface of the silicon nitride film 5 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to pattern the photoresist 6. Then, the photoresist 6 is used as an etching mask for patterning by dry etching to form the silicon nitride film 5 in the element region.

Next, as shown in FIG.
And the field oxide film 7 is formed to a thickness of 700 nm by a selective oxidation method using the silicon nitride film 5 as an oxidation resistant film.

Next, as shown in FIG. 4, the silicon nitride film 5 is removed by hot phosphoric acid (H ₃ PO ₄ ) heated to a temperature of 160 ° C., and the pad oxide film 4 under the silicon nitride film 5 is buffered. Remove with hydrofluoric acid (NH ₄ F + HF) solution.

Next, as shown in FIG. 5, a gate oxide film 8 is formed with a thickness of 30 nm on the semiconductor substrate 1 in which the field oxide film 7 region has been formed, by a thermal oxidation method.

Then, monosilane (SiH
A polycrystalline silicon film 9 is formed to a thickness of 400 nm on the entire surface by the CVD method using ₄ ).

Next, as shown in FIG.
Is formed on the entire surface by a spin coating method, exposed using a predetermined photomask, and developed to pattern the photoresist 6 so that the N-channel transistor forming region is opened.

Then, using this photoresist 6 as a mask, an N-type impurity of phosphorus is ion-implanted at a dose of 10 ¹⁵ atto the N-channel transistor forming region of the polycrystalline silicon film 9.
About ms / cm ² is added by the ion implantation method to form the N-type polycrystalline silicon film 10 in a predetermined region. afterwards,
The photoresist 6 is removed.

Next, as shown in FIG.
Is formed on the entire surface by a spin coating method, exposed using a predetermined photomask, and developed to pattern the photoresist 6 so that the P channel transistor forming region is opened.

Then, using the photoresist 6 as a mask for ion implantation, a P-type impurity of boron is ion-implanted in the P-channel transistor forming region of the polycrystalline silicon film 9 at an ion implantation amount of about 10 ¹⁵ atoms / cm ^2. Added to the P-type polycrystalline silicon film 1 in a predetermined region.
1 is formed. Then, the photoresist 6 is removed.

Next, as shown in FIG. 12, a tungsten silicide film which is the refractory metal alloy film 13 is formed on the entire surface of the semiconductor substrate 1 by the sputtering method to have a film thickness of 60 nm.

The film thickness of the tungsten silicide film which is the refractory metal film alloy film 13 is the film thickness of the polycrystalline silicon film 9, the etching rate difference between the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11, It may be adjusted and determined by the etching rate of the tungsten silicide film which is a refractory metal alloy film.

Then, a photoresist 6 is formed on the entire surface by a spin coating method, exposed using the same photomask as that used in the process described in FIG. 3, and developed to pattern the photoresist 6. That is, the photoresist 6 is formed on the N-type polycrystalline silicon film 10.

Then, using the patterned photoresist 6 as an etching mask, the tungsten silicide film which is the refractory metal alloy film 13 in a predetermined region is removed by dry etching except the region on the N-type polycrystalline silicon film 10. That is, the N-type polycrystalline silicon film 10
A refractory metal alloy film 13 is formed thereon.

Sulfur hexafluoride (SF) is used as an etching gas for patterning the tungsten silicide film.
₆ ), chlorine (Cl ₂ ) and difluoromethane (CH ₂ F
₂ ) Use and. Then, the photoresist 6 is removed.

Next, as shown in FIG.
Is formed on the entire surface by a spin coating method, is exposed by using a predetermined photomask, and is developed.
Patterning is performed so as to remain in the formation regions of the gate electrode wirings of the channel transistor and the N-channel transistor.

Next, as shown in FIG. 14, using the photoresist 6 as an etching mask, sulfur hexafluoride (SF ₆ ), chlorine (Cl ₂ ), and difluoromethane (CH ₂ F ₂ ) were used as etching gas. And N-type polycrystalline silicon film 10 on which a refractory metal alloy film 13 made of a tungsten silicide film is formed by anisotropic etching using
And the P-type polycrystalline silicon film 11 are collectively processed,
Gate electrode wiring is formed. Then, the photoresist 6 is removed.

In the processing of the gate electrode wiring by this anisotropic etching, the etching rates of the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 are very different, and the etching rates are N-type polycrystalline silicon. Membrane 1
The value of 0 is about 20% faster than that of the P-type polycrystalline silicon film 11 and is 350 nm / min.

Since the etching rate of the tungsten silicide film formed on the surface of the N-type polycrystalline silicon film 10 is about 40% slower than that of the N-type polycrystalline silicon film 10, the N-type polycrystalline film formed with the tungsten silicide film on the upper surface is formed. In the region of the silicon film 10, the apparent etching rate (etching time) can be made comparable to that of the P-type polycrystalline silicon 11. As a result, etching of the gate oxide film 8 below the N-type polycrystalline silicon film 10 can be suppressed.

Next, as shown in FIG. 15, the P well 2 region is doped with phosphorus, which is an N-type impurity, and the N well 3 region is doped with boron, which is a P-type impurity, at an ion implantation amount of 10 ¹⁵ atom.
s / cm ^{2 is} added by the ion implantation method.

Thereafter, a silicon oxide film which is the interlayer insulating film 14 is formed to a thickness of 500 nm by the CVD method.

After that, annealing is performed in a nitrogen atmosphere at a temperature of 900 ° C., and the high-concentration N-type diffusion layer 15 and the high-concentration P-type diffusion layer 1 which are the source and the drain of the MOS transistor.
6 and 6, respectively.

Although not shown, contact holes are opened at predetermined locations and aluminum wiring is formed, whereby N-type and P-type MOS transistors can be formed.

In the above-described embodiment, the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 are thin on the N-type polycrystalline silicon film 10 in order to make the apparent etching rates of them equal. A refractory metal alloy film 13 having a film thickness is formed.

However, a refractory metal film such as tungsten (W), titanium (Ti) or molybdenum (Mo) or a titanium, molybdenum and silicide film can be used instead of the refractory metal alloy film 13. .

The film thicknesses of these films are such that the film thickness of the lower polycrystalline silicon film 9, the etching rate difference between the N-type polycrystalline silicon 10 and the P-type polycrystalline silicon film 11, and the respective refractory metal films. It may be determined according to the etching rate.

When the gate electrode wiring has a polycide structure, the thickness of the polycrystalline silicon film 9 formed by the CVD method in the step of FIG. 5 is set to 200 nm. Then, according to the film thickness of the polycrystalline silicon film 9, tungsten silicide, which is the refractory metal alloy film 13 selectively formed on the N-type polycrystalline silicon film 11 by the sputtering method and the photoetching method in the step shown in FIG. The film thickness is 30 nm.

Then, as shown in FIG. 16, a tungsten silicide film which is the refractory metal silicide film 12 is formed with a thickness of 200 nm on the entire surface by a sputtering method.

After that, a photoresist 6 is formed on the entire surface by a spin coating method and exposed using a predetermined photomask,
A development process is performed to pattern the photoresist 6 into the shape of the gate electrode wiring.

Next, as shown in FIG. 17, using the photoresist 6 as an etching mask, sulfur hexafluoride (SF ₆ ), chlorine (Cl ₂ ), and difluoromethane (CH ₂ F ₂ ) were used as etching gas. A gate electrode in which a refractory metal alloy film 13 made of a tungsten silicide film is formed between the refractory metal alloy film 12 made of a tungsten silicide film and the N-type polycrystalline silicon film 10 by anisotropic etching using The wiring and the gate electrode wiring made of the P-type polycrystalline silicon film 11 are collectively processed to form a gate electrode wiring. Then, the photoresist 6 is removed.

Even in the case where the gate electrode wiring has a polycide structure, in the processing of the gate electrode wiring by anisotropic etching, it is possible to selectively form the high-melting point metal silicide film 12 between the N-type polycrystalline silicon film 10 and the high melting point metal silicide film 12. The melting point metal alloy film 13 plays the same role as when the gate electrode wiring does not have the polycide structure.

Therefore, the apparent etching rate (etching time) of the N-type polycrystalline silicon film 10 in which the refractory metal silicide film 12 is formed in the upper layer and the refractory metal alloy film 13 is further formed in the upper layer is It can be about the same as the P-type polycrystalline silicon film 11 on which the refractory metal silicide film 12 is formed.

Then, as shown in FIG. 18, the P well 2 region is doped with phosphorus, which is an N type impurity, and the N well 3 region is doped with boron, which is a P type impurity, at an ion implantation amount of 10 ¹⁵ atom.
It is added by the s / cm ² ion implantation method.

After that, a silicon oxide film which is the interlayer insulating film 14 is formed to a thickness of 500 nm by the CVD method.

Thereafter, annealing is performed in a nitrogen atmosphere at a temperature of 900 ° C. to form a high-concentration N-type diffusion layer 15 and a high-concentration P-type diffusion layer 16 which are the source and drain of the MOS transistor.

Although not shown in the subsequent steps, N-type and P-type MOS transistors can be formed by forming contact holes at predetermined locations and forming aluminum wiring.

Even when the gate electrode wiring has a polycide structure, in the embodiment, in order to make the apparent etching rates of the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 comparable, the N-type polycrystalline silicon film is formed. A refractory metal alloy film 13 having a thin film thickness is formed on 10.

However, a refractory metal film such as tungsten (W), titanium (Ti) or molybdenum (Mo) can be used as a substitute for the refractory metal alloy film 13.

The film thicknesses of these films are the same as the film thickness of the lower polycrystalline silicon film 9, the etching rate difference between the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11, and the respective refractory metal films. It may be determined by adjusting the etching rate.

Furthermore, when the gate electrode wiring has a silicide structure, the refractory metal silicide film 12 having a polycide structure is formed of a refractory metal such as tungsten (W), titanium (Ti) or molybdenum (Mo). By substituting the membrane, the application of the present invention becomes possible.

In the above description, the semiconductor substrate 1
Although the P well 2 and the N well 3 are formed in the above, it is also possible to form only one well. That is, a method of forming an N well in a semiconductor substrate having a P conductivity type or a method of forming a P well in a semiconductor substrate having an N conductivity type may be used.

[0084]

As is apparent from the above description, in the method of forming a gate electrode wiring according to the present invention, an N-type polycrystalline silicon film region and a P-type polycrystalline silicon film region are mixed on the same semiconductor substrate. In addition, when the gate oxide film is thin, it is possible to correct the difference in etching time at the time of etching due to the difference in the type of added impurities in the polycrystalline silicon film.

Therefore, after the N-type polycrystalline silicon film having a high etching rate is removed, it is possible to prevent the gate oxide film as the underlying layer from being unnecessarily exposed to the etching atmosphere. Therefore, the reliability with respect to device characteristics can be improved as compared with the case of using the conventional method of forming the gate electrode wiring.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention and a conventional example.

FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention and a conventional example.

FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention and a conventional example.

FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention and a conventional example.

FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention and a conventional example.

FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention and a conventional example.

FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention and a conventional example.

FIG. 8 is a cross-sectional view showing a method of manufacturing a semiconductor device in a conventional example.

FIG. 9 is a cross-sectional view showing a method of manufacturing a semiconductor device in a conventional example.

FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device in a conventional example.

FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device in a conventional example.

FIG. 12 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor device in the example of the present invention.

FIG. 14 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 15 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 17 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 18 is a cross-sectional view showing the method for manufacturing the semiconductor device in the example of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 6 Photoresist 7 Field oxide film 8 Gate oxide film 9 Polycrystalline silicon film 10 N-type polycrystalline silicon film 11 P-type polycrystalline silicon film 12 Refractory metal silicide film 13 Refractory metal alloy film 14 Interlayer insulating film 15 N Type diffusion layer 16 P type diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/3065 H01L 27/08 321 Z

Claims (12)

[Claims] 1. A process of forming a P well and an N well on a semiconductor substrate, a process of forming a field oxide film by selective oxidation, a process of forming a gate oxide film and a polycrystalline silicon film, and a process of forming a polycrystalline silicon film. A step of adding impurities to form an N-type polycrystalline silicon film and a P-type polycrystalline silicon film, and forming a refractory metal alloy film on the entire surface, and performing photoetching to form a refractory metal only on the N-type polycrystalline silicon film. The step of forming a metal alloy film, the step of forming a gate electrode wiring by photoetching, and the N serving as a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned with each other.
A step of forming a type diffusion layer and a P type diffusion layer, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a step of forming a wiring connecting to a semiconductor substrate through the contact hole. A method of manufacturing a semiconductor device, comprising: 2. A step of forming a well of the second conductivity type on a semiconductor substrate of the first conductivity type, and a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film. A step of adding an impurity to the polycrystalline silicon film to form an N-type polycrystalline silicon film and a P-type polycrystalline silicon film, and forming a refractory metal alloy film on the entire surface and performing photoetching on the N-type polycrystalline silicon film. A step of forming a refractory metal alloy film only on the film, a step of forming a gate electrode wiring by photoetching, and an N-type diffusion layer to be a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned with each other. A step of forming a P-type diffusion layer, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a wiring connecting to a semiconductor substrate through the contact hole A method of manufacturing a semiconductor device, comprising the step of forming a semiconductor device. 3. A step of forming a P well and an N well on a semiconductor substrate, a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and polycrystalline silicon, and impurities in the polycrystalline silicon. Is added to form N-type polycrystalline silicon and P-type polycrystalline silicon, a refractory metal film is formed on the entire surface, and a refractory metal film is formed only on the N-type polycrystalline silicon film by photoetching. A step of forming a gate electrode wiring by photoetching, a step of forming an N-type diffusion layer and a P-type diffusion layer to be a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned, A step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region,
A method of manufacturing a semiconductor device, comprising a step of forming a wiring connected to a semiconductor substrate through a contact hole. 4. A step of forming a well of the second conductivity type on a semiconductor substrate of the first conductivity type, and a step of forming a field oxide film by selective oxidation, and then forming a gate oxide film and polycrystalline silicon. Impurities are added to polycrystalline silicon, and N
-Type polycrystalline silicon and P-type polycrystalline silicon are formed, a refractory metal film is formed on the entire surface, and a refractory metal film is formed only on the N-type polycrystalline silicon film by photoetching, and photoetching. To form a gate electrode wiring, a step of forming an N-type diffusion layer and a P-type diffusion layer to be a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned, and an interlayer insulating film is formed on the entire surface. A method of manufacturing a semiconductor device, comprising: forming and forming a contact hole in a predetermined region; and forming a wiring connected to a semiconductor substrate through the contact hole. 5. A step of forming a P well and an N well on a semiconductor substrate, a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film, and a polycrystalline silicon film. A step of adding an impurity to the N-type polycrystalline silicon film and the P-type polycrystalline silicon film, and after forming a refractory metal alloy film on the entire surface, photoetching is performed only on the N-type polycrystalline silicon film. A step of forming a melting point metal alloy film, a step of forming a refractory metal silicide film on the entire surface and forming a gate electrode wiring by photoetching, and a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned. A step of forming an N-type diffusion layer and a P-type diffusion layer that are formed, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a contact hole A method of manufacturing a semiconductor device, comprising a step of forming a wiring connected to a semiconductor substrate via 6. A step of forming a second conductivity type well on a first conductivity type semiconductor substrate, and a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film. , A step of adding impurities to the polycrystalline silicon film to form an N-type polycrystalline silicon film and a P-type polycrystalline silicon film, and after forming a refractory metal alloy film on the entire surface,
A step of forming a refractory metal alloy film only on the N-type polycrystalline silicon film by photoetching, a step of forming a refractory metal silicide film over the entire surface, and a gate electrode wiring by photoetching; A step of forming an N-type diffusion layer and a P-type diffusion layer to be a source / drain region in a region aligned with the field oxide film, and a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region. A method of manufacturing a semiconductor device, comprising: forming a wiring connected to a semiconductor substrate through a contact hole. 7. A step of forming a P well and an N well on a semiconductor substrate, a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film, and a polycrystalline silicon film. A step of forming an N-type polycrystal silicon film and a P-type polycrystal silicon film by adding impurities, and forming a refractory metal film over the entire surface, and then performing photoetching to form a refractory metal only on the N-type polycrystal silicon film. A step of forming a metal film, a step of forming a second refractory metal silicide film on the entire surface, and a step of forming a gate electrode wiring by photoetching, and a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned. A step of forming an N-type diffusion layer and a P-type diffusion layer, which are to be formed, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, A method of manufacturing a semiconductor device, comprising a step of forming a wiring connected to a semiconductor substrate via the semiconductor device. 8. A step of forming a second conductivity type well on a first conductivity type semiconductor substrate, and a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film. A step of adding impurities to the polycrystal silicon film to form an N-type polycrystal silicon film and a P-type polycrystal silicon film, and forming a refractory metal film on the entire surface, followed by photoetching to form the N-type polycrystal silicon film The step of forming the refractory metal film only on the upper surface, the step of forming the second refractory metal silicide film on the entire surface and forming the gate electrode wiring by photoetching, and the step of aligning the gate electrode wiring with the field oxide film N to be the source / drain region in the region
A step of forming a type diffusion layer and a P type diffusion layer, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a step of forming a wiring connecting to a semiconductor substrate through the contact hole. A method of manufacturing a semiconductor device, comprising: 9. A step of forming a P well and an N well on a semiconductor substrate, a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film, and a polycrystalline silicon film. A step of adding impurities to the N-type polycrystalline silicon film and the P-type polycrystalline silicon film to form a refractory metal alloy film on the entire surface, and performing photoetching to form a refractory metal only on the N-type polycrystalline silicon film. A step of forming a metal alloy film, a step of forming a refractory metal film on the entire surface, and a step of forming a gate electrode wiring by photo-etching, and a source / drain region which becomes a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned with each other. A step of forming a type diffusion layer and a P type diffusion layer, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a semiconductor substrate via the contact hole. A method of manufacturing a semiconductor device, comprising the step of forming a wiring connected to a plate. 10. A step of forming a second conductivity type well on a semiconductor substrate of a first conductivity type, and a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film. A step of adding an impurity to the polycrystalline silicon film to form an N-type polycrystalline silicon film and a P-type polycrystalline silicon film, and forming a refractory metal alloy film on the entire surface and performing photoetching on the N-type polycrystalline silicon film. The step of forming the refractory metal alloy film only on the upper surface, the step of forming the refractory metal film on the entire surface and forming the gate electrode wiring by photo-etching, and the source in the region where the gate electrode wiring and the field oxide film are aligned. N-type diffusion layer to be the drain region and P
A step of forming a mold diffusion layer, a step of forming an interlayer insulating film on the entire surface, and forming a contact hole in a predetermined region,
A method of manufacturing a semiconductor device, comprising a step of forming a wiring connected to a semiconductor substrate through a contact hole. 11. A step of forming a P well and an N well on a semiconductor substrate, a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film, and a polycrystalline silicon film. A step of adding an impurity to the N-type polycrystalline silicon film and the P-type polycrystalline silicon film, and forming a refractory metal film on the entire surface and performing photoetching on the N-type polycrystalline silicon film only. A step of forming a film, a step of forming a refractory metal film on the entire surface, and a step of forming a gate electrode wiring by photoetching, and an N-type diffusion which becomes a source / drain region in a region where the gate electrode wiring and the field oxide film are aligned. Layer and a P-type diffusion layer, a step of forming an interlayer insulating film on the entire surface and forming a contact hole in a predetermined region, and a step of contacting the semiconductor substrate through the contact hole. A method of manufacturing a semiconductor device, comprising the step of forming a continuous wiring. 12. A step of forming a well of the second conductivity type on a semiconductor substrate of the first conductivity type, and a step of forming a field oxide film by selective oxidation and then forming a gate oxide film and a polycrystalline silicon film. A step of adding impurities to the polycrystalline silicon film to form an N-type polycrystalline silicon film and a P-type polycrystalline silicon film, and forming a refractory metal film on the entire surface, and performing photoetching on the N-type polycrystalline silicon film. A step of forming a refractory metal film only on the
A step of forming a gate electrode wiring by photoetching, a step of forming an N-type diffusion layer and a P-type diffusion layer to be source / drain regions in a region where the gate electrode wiring and the field oxide film are aligned, and interlayer insulation over the entire surface. A method of manufacturing a semiconductor device, comprising: a step of forming a film and forming a contact hole in a predetermined region; and a step of forming a wiring connecting to a semiconductor substrate through the contact hole.