JP2811798B2 - Semiconductor substrate manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing an SOI (silicon on insulator) substrate by bonding wafers.

[Summary of the Invention]

The present invention provides a method for manufacturing a semiconductor substrate, comprising: forming a polycrystalline semiconductor layer at a low growth temperature on a semiconductor wafer via an insulating film; annealing the semiconductor wafer to a bonding temperature; By bonding another wafer and polishing the semiconductor wafer, the growth of Glen during bonding is suppressed, and the occurrence of pinholes in the polycrystalline semiconductor layer is prevented, and the reliability of the semiconductor substrate is improved. This is also intended to improve the yield of devices formed on the substrate.

The present invention also provides a method for manufacturing a semiconductor substrate, comprising: forming a thin film having a high crystal growth nucleation rate on a semiconductor wafer via an insulating film; and forming a polycrystalline semiconductor layer on the thin film.
By bonding another wafer on the polycrystalline semiconductor layer and polishing the semiconductor wafer, pinholes are prevented from being generated in the polycrystalline semiconductor layer, the reliability of the semiconductor substrate is improved, and the manufacturing time is reduced. In addition, the manufacturing process is simplified, and the yield of devices formed on the substrate is also improved.

[Conventional technology]

In recent years, development of fabricating a VLSI using a so-called SOI substrate having a thin film single crystal silicon layer formed on an insulator has been advanced. Among various SOI substrate manufacturing methods, a bonding method that is considered to have the best crystallinity and excellent characteristics is the bonding method.

FIG. 6 shows an example of an SOI substrate by a bonding method. As shown in FIG. 6A, patterning is performed on the main surface of the mirror-finished silicon wafer (1) using a photolithography technique so as to leave a step where a plurality of element formation regions (2) become convex portions. Then, an insulating film such as SiO ₂ is formed on the main surface.
A film (3) is formed, and a flattening layer, for example, a polycrystalline silicon layer (4) is formed on the entire surface to fill the steps. The surface of the polycrystalline silicon layer (4) is polished flat. Next, after bonding the separate mirror silicon wafer (5) in the polycrystalline silicon layer is flattened as shown in FIG. 6 B (4), as shown in FIG. 6 C SiO ₂ film (3 ) Is used as a polishing stopper and polished from the back surface of the silicon wafer (1).
An SOI substrate (6) having a plurality of island-shaped silicon thin films having a thickness of about 1000 ° separated by an O ₂ film (3), that is, an element formation region (2) is obtained.

[Problems to be solved by the invention]

However, in the conventional method of manufacturing a semiconductor substrate, as shown in FIG. 6A, when the polycrystalline silicon layer (4) is polished flat, a large number of pinholes (7) are generated in the layer (4). After the bonding step, the pinhole (7) remains as an air bubble (8), and the air bubble (8) ruptures during a high-temperature, low-pressure process at the time of device fabrication that is performed thereafter, thereby causing contamination of the furnace or the like. , Lowering the yield.

As the reason, when forming a polycrystalline silicon layer by CVD on the SiO ₂ film (3) (4), since performed at high growth temperatures (1000 ° C. to 1150 ° C.), SiO ₂ film (3) When a nucleus is locally formed on the nucleus, a single crystal is rapidly grown from the nucleus, and a polycrystalline silicon layer (4) having a desired thickness is formed.
At the stage of formation on the SiO ₂ film (3), the portion where the single crystal was grown abnormally grows as a so-called whisker (10), which is a needle-shaped crystal ten and several times higher than the desired thickness (see FIG. 7).
As shown in FIG. A, it is considered that the whisker (10) is extracted from the root in the flattening and polishing processing for the polycrystalline silicon layer (4) in a later step, and the extracted portion becomes a pinhole (7). The above phenomenon also occurs when dirt, foreign matter, etc. adhere to the SiO ₂ film (3), and the whisker (10) is formed as a single crystal with the dirt and foreign matter as nuclei as described above, and the pinhole (7) is formed. ) It is a factor of occurrence.

As a method of controlling the growth of such whiskers (10), nuclei are first found on the SiO ₂ film (3) by growing the polycrystalline silicon layer (4) at a low growth temperature of 950 ° C. or lower. A method was proposed to reduce the number of pinholes by uniformly generating the nuclei without causing local abnormal growth of nuclei.

By the way, in manufacturing an SOI substrate, good bonding cannot be performed unless the surface is polished by polishing the surface to a height of 2 to 3 μm after embedding a step with polycrystalline silicon, so that the polycrystalline silicon layer (4) The thickness needs to be about 5 μm. In order to form polycrystalline silicon having a thickness of 5 μm in a short time, SiH ₄ has been decomposed and deposited at a growth temperature of about 900 ° C. However, this method still found that about 10 bubble bursts per wafer occurred during the high temperature, low pressure process.

In view of the above, the present invention is intended to further prevent the occurrence of pinholes (accordingly, the generation of bubbles) in a polycrystalline silicon layer, to increase the reliability of a semiconductor substrate, and to improve the yield of devices. It is intended to provide a method of manufacturing a semiconductor substrate which can be performed.

[Means for solving the problem]

According to the method of manufacturing a semiconductor substrate of the present invention, a polycrystalline semiconductor layer (4) is formed at a low growth temperature on a semiconductor wafer (1) via an insulating film (3), and the semiconductor wafer (1) is bonded to a bonding temperature. After annealing, another wafer (5) is bonded onto the polycrystalline semiconductor layer (4), and the semiconductor wafer (1) is polished. The low growth temperature is lower than 900 ° C., and the lower the temperature, the more whiskers can be suppressed. However, when the temperature is lowered below 600 ° C., the state changes from an almost amorphous state to an amorphous state. Therefore, a low growth temperature of about 650 ° C. is preferable.

According to another method of manufacturing a semiconductor substrate of the present invention, a thin film (15) having a high crystal growth nucleation rate is formed on a semiconductor wafer (1) via an insulating film (3), and a plurality of thin films (15) are formed on the thin film (15). After forming a crystalline semiconductor layer (4) and bonding another wafer (5) on the polycrystalline semiconductor layer (4), the semiconductor wafer (1) is polished.

As the thin film (15) having a high crystal growth nucleus generation rate, for example, a polycrystalline semiconductor film having a growth temperature of about 650 ° C. or a semiconductor nitride film (Si ₃ N ₄ ) can be used. The step of forming the thin film (15) having a high crystal growth nucleation rate and the step of forming the polycrystalline semiconductor layer (4) on the thin film (15) can be performed continuously in the same reactor. And

[Action]

According to the first generation method described above, the insulating film (3)
By forming the polycrystalline semiconductor layer (4) thereon at a low growth temperature (lower than 900 ° C., preferably about 650 ° C.), nuclei are apparently generated uniformly on the insulating film (3). As a result, the generation of whiskers is greatly suppressed. Incidentally, the polycrystalline semiconductor layer (4) deposited at a low growth temperature has a considerably small grain size. Thereafter, at the high temperature of about 1100 ° C. at the time of bonding with another wafer (5), the grain growth easily occurs, and an adverse effect is caused. Bring. However, according to the present invention, after the polycrystalline semiconductor layer (4) is deposited at a low growth temperature, the semiconductor wafer (1) is once annealed to a bonding temperature to sufficiently grow the polycrystalline semiconductor layer (4). Therefore, there is almost no grain growth in the subsequent bonding step. Accordingly, the amount of pinholes generated in the polycrystalline semiconductor layer (4) is greatly reduced, and no bubbles remain at the bonding interface after bonding. Therefore, the bubbles are ruptured by the heat treatment in the subsequent device forming process. And contamination of the furnace can be prevented. Also, since there is no grain growth of the polycrystalline semiconductor layer (4) at the time of bonding, there is no adverse effect on the bonded wafer. As a result, a highly reliable semiconductor substrate (13) can be manufactured, and devices can be manufactured with a high yield.

Further, according to the manufacturing method of the second invention, the insulating film (3)
After forming a thin film (15) with a high crystal growth nucleation rate on it,
Since the polycrystalline semiconductor layer (4) is formed on the thin film (15), a large number of nuclei are uniformly generated on the thin film (15).
Whisker generation is greatly suppressed in the polycrystalline semiconductor layer. In addition, since the polycrystalline semiconductor layer (4) is formed on the thin film (15) having a high crystal growth nucleation rate, the growth temperature of the polycrystalline semiconductor layer (4) should be, for example, 900 ° C. or higher, which can be performed in a short time. Can be. Further, when the formation of the thin film (15) having a high crystal growth nucleus generation rate and the formation of the polycrystalline semiconductor layer (4) are continuously performed in the same reactor, contamination on the surface of the polycrystalline semiconductor layer is avoided. Accordingly, as in the first invention, the occurrence of pinholes in the polycrystalline semiconductor layer (4) is greatly reduced, and no air bubbles remain at the bonding interface, so that the air bubbles burst during the subsequent device fabrication process. The contamination of the furnace is also prevented. Further, the deposition time of the polycrystalline semiconductor layer is shortened, and post-deposition annealing as in the first invention is also omitted. As a result, a highly reliable semiconductor substrate (16) can be manufactured, the manufacturing time can be reduced, the manufacturing process can be simplified, and devices can be manufactured with a high yield.

〔Example〕

Hereinafter, an example of a method for manufacturing an SOI substrate according to the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In this example,
First, as shown in FIG. 1A, a mirror-finished silicon wafer (1)
Is patterned using photolithography technology so that the element formation region (2) remains at a step so as to be a projection. Next, an SiO ₂ film (3) is formed on the main surface of the stepped silicon wafer (1) by thermal oxidation and CVD (chemical vapor deposition) to a thickness of about 1 μm, for example.

Next, as shown in FIG.
A polycrystalline silicon layer (4) is deposited on the O ₂ film (3) by CVD, for example, to a thickness of about 5 μm. The polycrystalline silicon layer (4) is deposited at a growth temperature of 650 ° C. and a low pressure of 0.6 Torr under a low pressure.

Next, as shown in FIG. 1C, a polycrystalline silicon layer (4)
The silicon wafer (1) on which is formed is annealed to a temperature at the time of laminating in a later step, for example, 1100 ° C., so that the polycrystalline silicon layer (4) is sufficiently grown.

Next, as shown in FIG. 1D, a polycrystalline silicon layer (4)
Is polished flat.

Next, as shown in FIG. 1E, another mirror surface silicon wafer (5) is directly bonded to the planarized polycrystalline silicon layer (4) to form a bonded wafer (11). At this time, both wafers (1) and (5) self-adsorb by hydrogen bond based on OH group, and then in an oxygen atmosphere or a nitrogen atmosphere.
Heat treatment at 1100 ° C for 2 hours to bond.

Next, as shown in FIG. 1F, grinding and polishing are performed from the back surface of one silicon wafer (1), and polishing is performed on this surface with the surface of the SiO ₂ film (3) also serving as a polishing stopper as a reference surface. Then, a target SOI substrate (13) having a plurality of island-shaped element forming regions (2) formed of silicon thin films which are insulated and separated from each other by the SiO ₂ film (3) is obtained.

According to the method for manufacturing the SOI substrate (13), when forming the polycrystalline silicon layer (4) on the SiO ₂ film (3) in the step shown in FIG. 1B, it is performed at a low growth temperature of about 650 ° C. Thus, nuclei are apparently generated uniformly on the SiO ₂ film (3) when the polycrystalline silicon layer (4) is formed, and the nuclei grow relatively slowly, so that the amount of generated nuclei increases. as a result,
The polycrystalline silicon layer (4) grows uniformly, and a locally generated nucleus grows abnormally as in the prior art, resulting in a whisker having a thickness several to tens of times higher than the layer thickness (about 5 μm) of the polycrystalline silicon layer. Generation can be suppressed. Even if the whisker grows, its size is very small (about buried in the polycrystalline silicon layer (4)), so that it will not be extracted in the subsequent flat polishing. Since the polycrystalline silicon layer (4) is formed at a low growth temperature, the grain size is small. Next, in the step of FIG. 1C, the polycrystalline silicon layer (4) is annealed at a bonding temperature (1100 ° C.). 1), after the grain growth, the wafer is bonded to another silicon wafer (5) in the step shown in FIG. 1E. At this bonding, the grain growth of the polycrystalline silicon layer (4) does not occur, and the bonded wafer ( 12) will not be adversely affected. Therefore, the occurrence of pinholes due to whiskers is greatly reduced, and no bubbles remain after bonding,
During the process of device fabrication using the SOI substrate (13), bubble rupture is eliminated and contamination of the furnace can be prevented. As a result, a highly reliable SOI substrate (13) can be manufactured, and devices can be manufactured with a high yield.

FIG. 2 shows another embodiment of the present invention. In this example, as shown in FIG. 2A, a mirror-finished silicon wafer (1)
Is patterned so that the element formation region (2) is left with a step so as to be a convex portion, and a thickness of, for example, 1
An SiO ₂ film (3) is formed by thermal oxidation and CVD of about μm.

Next, as shown in FIG. 2B, a polycrystalline silicon film or silicon nitride (Si ₃ N ₄ ) at a low growth temperature of about 650 ° C.
A thin film (thickness of, for example, about 1000 °) (15) having a high so-called silicon growth nucleation rate, such as a film, is formed. In the case of polycrystalline silicon at a low growth temperature, the generation of whiskers can be suppressed as apparent from the above. Then, without taking out from the reactor,
A polycrystalline silicon layer (4) having a thickness of, for example, about 5 μm is continuously deposited in the same reaction furnace. At this time, the polycrystalline silicon layer (4) is formed by raising the temperature, that is, under conventional production conditions, for example, at a growth temperature of about 900 ° C. and a pressure of about 100 Torr.

Next, as shown in FIG. 2C, a polycrystalline silicon layer (4)
Is polished flat.

Next, as shown in FIG. 2D, another mirror surface silicon wafer (5) is directly bonded to the planarized polycrystalline silicon layer (4) to form a bonded wafer (12).

Next, as shown in FIG. 1E, grinding and polishing are performed from the back surface of one silicon wafer (1), polishing is stopped on the surface of the SiO ₂ film (3), and a plurality of island-like silicon thin films are formed. An intended SOI substrate (16) on which the element formation region (2) is formed is obtained.

According to the method of manufacturing the SOI substrate (16), in the step of FIG. 2B, a polycrystalline silicon layer (4) is formed on the SiO ₂ film (3).
Is formed, the polycrystalline silicon layer (4) is formed through a thin film (15) having a high silicon growth nucleation rate by a polycrystalline silicon film or a silicon nitride film at a low growth temperature. According to (15), nuclei are generated uniformly, and the polycrystalline silicon layer (4) grows uniformly, so that generation of conventional whiskers can be suppressed. Therefore, as in the first embodiment, the generation of pinholes by the whiskers is greatly reduced, and no bubbles remain even after bonding, so that the subsequent bubble rupture during the device fabrication process and contamination in the furnace based on the bursting of bubbles. Can be prevented. Since the polycrystalline silicon layer (4) has a thin film (15) with a high growth nucleation rate as an underlayer and is grown uniformly, it can be deposited at a high temperature of about 900 ° C.
The deposition time of the polycrystalline silicon layer (4) can be reduced as compared with the first embodiment. Further, the annealing treatment after the deposition of the polycrystalline silicon layer (4) as in the first embodiment can be omitted. Since the formation of the thin film (15) and the formation of the polycrystalline silicon layer (4) are continuously performed in the same reactor by changing the temperature or the temperature with the raw material gas, contamination on the surface of the polycrystalline silicon is avoided. be able to. Therefore, a highly reliable SOI substrate can be manufactured, and the manufacturing time and the process can be shortened. At the same time, devices can be created with high yield.

Next, an example of a method for manufacturing a device using an SOI substrate will be described. The underlying silicon wafer used for the bonding type SOI substrate has extremely good flatness and crystallinity, and is crystallographically independent of the SOI portion (so-called element formation region). Can be set completely freely. Therefore, in this example, in the layout design of an IC (integrated circuit), as shown in FIG. 3, an insulating layer (23) including a planarization film is selectively removed from a part of a bonding type SOI substrate (18). Form a part (21A) where the underlying silicon substrate (21) is exposed, and replace the logic part requiring high speed with the SOI part (22A)
Bipolar circuits and CCD sensors that require bulk silicon-specific techniques such as gettering are laid out on the underlying silicon substrate (21A). In this way, an embedded device utilizing the characteristics of the SOI substrate (18) can be realized at an early stage. For example, in a 2/3 to 1/2 inch optical imaging device for high definition, a CCD sensor (25) is formed on a base silicon substrate (21A) as shown in the plan view of FIG. By forming the shift register (26) on (22A), an image sensor for high definition capable of driving at an ultra-high speed can be obtained.

Also, in the conventional NTSC type CCD image sensor of 1/2 inch or the like, it is required to incorporate a peripheral circuit such as a clock generator and a shift register circuit into one chip, that is, to make the image sensor intelligent. Also in this case, using the SOI substrate (18) shown in FIG. 3, a CCD sensor is formed on the underlying silicon substrate portion (21A), and a peripheral circuit is formed on the SOI portion (22A). It is possible to achieve intelligent elements. Further, this technique can be applied to Bi-CMOS. Thus, for example the fifth first element formation region of the SOI portion (22A) as shown in FIG. (22 ₁₎ to form a p-channel MOS transistor (27), n in the second element forming region (22 ₂₎ A channel MOS transistor (28) is formed, an Al wiring (30) is formed, a CMOS (29) is formed, and a collector (31),
By forming a bipolar npn transistor (34) including a base (32), an emitter (33), and an Al wiring (30), a Bi-CMOS is formed.

As described above, the device creation method of this example is based on the bonding method.
The SOI part (22A) of the SOI substrate (18) and the underlying silicon substrate part (2
By using 1A), a hybrid LSI can be obtained, which can be applied, for example, to the creation of intelligent sensors with a built-in clock generator and shift register, ultra-high-speed AD / DA converters with a built-in analog amplifier, and the like.

〔The invention's effect〕

As described above, according to the method for manufacturing a semiconductor substrate of the present invention, a polycrystalline semiconductor layer is formed on a semiconductor wafer at a low growth temperature via an insulating film, and after annealing the semiconductor wafer to a bonding temperature, By bonding another wafer on the polycrystalline semiconductor layer and polishing the semiconductor wafer, it is possible to suppress the growth of Glen during the bonding and to prevent the occurrence of pinholes in the polycrystalline semiconductor layer. As a result, a highly reliable semiconductor substrate can be manufactured, and the yield of devices formed on this substrate can be improved.

According to another method for manufacturing a semiconductor substrate of the present invention,
After forming a thin film having a high crystal growth nucleation rate on a semiconductor wafer via an insulating film, a polycrystalline semiconductor layer is formed on the thin film, and another wafer is bonded on the polycrystalline semiconductor layer to form a semiconductor wafer. By polishing, it is possible to prevent the occurrence of pinholes in the polycrystalline semiconductor layer, to manufacture a highly reliable semiconductor substrate, to shorten the manufacturing time, and to simplify the manufacturing process. Can be achieved. At the same time, the yield of devices formed on the semiconductor substrate can be improved.

[Brief description of the drawings]

1A to 1F are process diagrams of an example of a method of manufacturing a semiconductor substrate of the present invention, FIGS. 2A to 2E are process diagrams of another example of a method of manufacturing a semiconductor substrate of the present invention, and FIG. Sectional view of the main part of a bonding type SOI substrate applied to
FIG. 5 is a schematic plan view of an image sensor manufactured using a substrate, FIG. 5 is a cross-sectional view of a main part of a Bi-CMOS manufactured using the SOI substrate, and FIGS. 6A to 6C are examples of a conventional SOI substrate manufacturing method. FIG. 7 is a cross-sectional view used for explanation of the conventional art. (1) and (5) are mirror-surface silicon wafers, (2) is an element formation region, (3) is an SiO ₂ film, (4) is a polycrystalline silicon layer,
(15) is a thin film with high silicon growth nucleation rate, (13),
(16) is an SOI substrate.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Soharu Shimanoe 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Michio Negishi 6-7-1 Kita Shinagawa, Shinagawa-ku, Tokyo No. 35 Inside Sony Corporation (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/02 H01L 27/12

Claims (2)

(57) [Claims] A step of forming a polycrystalline semiconductor layer on a semiconductor wafer at a low growth temperature via an insulating film; a step of annealing the semiconductor wafer to a bonding temperature; and a step of placing another wafer on the polycrystalline semiconductor layer. A method of manufacturing a semiconductor substrate, comprising a step of bonding and a step of polishing the semiconductor wafer. 2. A step of forming a thin film having a high crystal growth nucleation rate on a semiconductor wafer via an insulating film, a step of forming a polycrystalline semiconductor layer on the thin film, and another wafer on the polycrystalline semiconductor layer. Bonding a semiconductor wafer, and polishing the semiconductor wafer.