CN113421849A - Preparation process of silicon substrate with insulating buried layer - Google Patents
Preparation process of silicon substrate with insulating buried layer Download PDFInfo
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- CN113421849A CN113421849A CN202110644599.2A CN202110644599A CN113421849A CN 113421849 A CN113421849 A CN 113421849A CN 202110644599 A CN202110644599 A CN 202110644599A CN 113421849 A CN113421849 A CN 113421849A
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- 239000000758 substrate Substances 0.000 title claims abstract description 95
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 54
- 239000010703 silicon Substances 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 37
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052786 argon Inorganic materials 0.000 claims abstract description 14
- 230000004913 activation Effects 0.000 claims abstract description 11
- 238000000227 grinding Methods 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000003746 surface roughness Effects 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 14
- 239000011164 primary particle Substances 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 30
- 239000013078 crystal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 238000001994 activation Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000678 plasma activation Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000003471 anti-radiation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention relates to a preparation process of a silicon substrate with an insulating buried layer, which comprises the steps of preparing a polished silicon wafer as a device layer silicon substrate and a silicon oxide wafer as a supporting silicon substrate, respectively carrying out plasma surface activation treatment, carrying out low-temperature annealing after normal-temperature bonding, reducing the thickness to a target thickness by mechanical grinding, then carrying out CMP polishing treatment, and finally carrying out high-temperature argon annealing treatment on a polished bonding wafer. The invention has the advantages that under the premise that the high temperature thermal budget is not greatly increased for the bonded silicon wafer, the bonding strength is reinforced and simultaneously the extremely low primary particle defect density in the silicon substrate with the insulating buried layer can be realized through the two-step annealing mode of low-temperature annealing and high-temperature argon annealing.
Description
Technical Field
The invention relates to a preparation method of an integrated circuit material, in particular to a preparation process of a silicon substrate with an insulating buried layer.
Background
The SOI semiconductor device based on the silicon substrate with the insulating buried layer realizes complete physical isolation, eliminates latch-up effect, reduces parasitic capacitance, has obvious advantages in the aspects of power consumption, running speed, irradiation resistance and device integration level, and is concerned about. In recent years, with the continuous progress of process technology, the preparation of SOI materials has been rapidly developed.
For thick-film SOI with the top silicon thickness of more than 1um, the application range is wider, such as automobile electronics, wireless communication, sensors, anti-radiation devices and the like. At present, the preparation technology of the thick film silicon-on-insulator material mainly comprises a Smart-cut (Smart-cut) overlay epitaxial technology and a BESOI bonding thinning technology. Smart-cut (Smart-cut) technology is limited by IP patents and is available to only a few authorized silicon vendors; the BESOI bonding thinning technology has the characteristics of simple process, low cost and the like, and although the thickness uniformity of a top device silicon layer is difficult to be accurately controlled due to the thinning process, the BESOI silicon wafer has the crystal defect density and the surface quality which are similar to those of bulk silicon, can be adjusted in a large range, and has wide application in the aspect of power device substrates.
The conventional BESOI silicon wafer generally adopts a common czochralski CZ single crystal polished wafer as a substrate, and a support substrate wafer and a device substrate wafer are directly subjected to high-temperature annealing treatment after being bonded so as to improve and reinforce the bonding strength and then be thinned to reach the target thickness of top silicon of a device layer. The crystal quality influence of the czochralski single crystal, especially the COP (original particle defect), can affect the final device gate oxide integrity of the silicon-on-insulator substrate and possibly cause other electrical failures, so that measures are required to be taken to reduce the crystal defects of the top silicon of the device layer to the maximum extent while the silicon-on-insulator substrate is prepared.
Disclosure of Invention
The invention aims to provide a preparation process of a silicon substrate with an insulating buried layer, which is characterized in that on the basis of a conventional BESOI bonding and thinning process, through plasma activation treatment before bonding and two-step annealing after bonding, the first-step low-temperature annealing can ensure that the silicon substrates subjected to plasma surface activation treatment can be firmly attached together, enough bonding strength is ensured to cope with the subsequent thinning process, and the second-step high-temperature argon annealing is carried out after thinning is finished, so that the bonding strength is improved, and an almost perfect single crystal silicon layer with extremely low primary particle defects can be formed on the surface of top silicon of a device layer.
The invention realizes the purpose through the following technical scheme: a preparation process of a silicon substrate with an insulating buried layer comprises the following steps:
s101, providing a common CZ single crystal silicon substrate, wherein the front surface of the silicon substrate is a polished surface, and bulk silicon contains COP (coefficient of performance) primary particle defects;
s102, providing a supporting substrate, wherein the front surface of the supporting substrate is a polishing surface;
s103, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s104, respectively carrying out plasma surface activation treatment on the polished surface of the monocrystalline silicon substrate and the surface of the support substrate with the insulating layer as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together at normal temperature to form a bonded substrate;
s105, placing the bonded substrate into a furnace tube for low-temperature annealing;
s106, grinding the bonded substrate to a target thickness in a mechanical grinding thinning mode;
s107, carrying out CMP polishing on the bonded substrate to obtain the required flatness and surface roughness;
and S108, performing high-temperature argon annealing treatment on the polished bonded substrate to further improve the bonding strength and ensure that the surface layer of the silicon substrate on the insulating layer has extremely low COP (coefficient of performance) primary particle defect density.
Further, the S101 monocrystalline silicon substrate is a Czochralski CZ monocrystalline polished silicon wafer, the front surface of the silicon substrate is a polished surface, and bulk silicon contains COP (coefficient of performance) primary particle defects.
Further, the S102 monocrystalline silicon substrate is a Czochralski CZ monocrystalline polished silicon wafer.
Further, the thickness of the silicon dioxide of the S103 is 0.1-2 um.
Further, the plasma surface activation of S104 adopts N2Or O2Or N2/O2Mixed gas, bondThe resultant temperature is normal temperature.
Further, the annealing temperature of S105 is not more than 400 ℃, and the time is more than 1 hour.
Further, the thickness of the top silicon reserved after the mechanical grinding of the S106 is 10-50 um.
Further, the CMP polishing removal amount in S107 is greater than 5 um.
Further, the high-temperature argon annealing in the step S108 is an annealing atmosphere of argon, the process temperature is not lower than 1180 ℃, and the process time is not lower than 1 hour.
Compared with the prior art, the preparation process of the silicon substrate on the power insulator has the beneficial effects that: on the basis of the process for preparing the silicon substrate material on the insulator by the conventional bonding thinning process, the plasma surface activation treatment and the low-temperature annealing process are comprehensively applied to ensure relatively strong bonding strength to cope with the subsequent thinning process, and finally, the bonding strength is further improved by the high-temperature argon annealing process, and simultaneously, the device layer top silicon with the extremely low primary particle defect of nearly perfect crystals is obtained, so that the silicon substrate material with the insulating buried layer is prepared.
Drawings
FIG. 1 is a flow chart of the steps performed in accordance with an embodiment of the present invention.
Fig. 2 is a schematic diagram of the product state of step S101 and step S102.
Fig. 3 is a schematic diagram of the product status in step S103.
Fig. 4 is a schematic diagram of the product status of step S104.
Fig. 5 is a schematic diagram of the product status in step S106.
Fig. 6 is a schematic diagram of the product state in step S107.
Fig. 7 is a schematic diagram of the product status of step S108.
Detailed Description
The following describes in detail a specific embodiment of a method for manufacturing a silicon substrate with a buried insulating layer according to the present invention with reference to the accompanying drawings.
Fig. 1 is a flowchart illustrating implementation steps of this embodiment, and a process for manufacturing a silicon substrate with a buried insulating layer includes the following steps:
step S101, providing a common CZ single crystal silicon substrate, wherein the front surface of the silicon substrate is a polished surface, and bulk silicon contains COP (coefficient of performance) primary particle defects;
step S102, providing a support substrate, wherein the front surface of the support substrate is a polishing surface;
step S103, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
step S104, respectively carrying out plasma surface activation treatment on the polished surface of the monocrystalline silicon substrate and the surface of the support substrate with the insulating layer as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together at normal temperature to form a bonded substrate;
step S105, placing the bonded substrate into a furnace tube for low-temperature annealing;
step S106, grinding the bonded substrate to a target thickness by adopting a mechanical grinding thinning mode;
step S107, carrying out CMP polishing on the bonded substrate to obtain the required flatness and surface roughness;
and step S108, performing high-temperature argon annealing treatment on the polished bonded substrate to further improve the bonding strength and ensure that the silicon substrate surface layer on the insulating layer has extremely low COP (coefficient of performance) primary particle defect density.
Referring to steps S101 and S102, as shown in fig. 2, a single crystal silicon substrate 100 is provided, wherein the doping material of the single crystal silicon substrate 100 may be B, P, As or another impurity element, and the bulk silicon contains a certain amount of COP grown-in grain defects.
Referring to step S103 shown in fig. 3, a monocrystalline silicon supporting substrate 200 is provided, the front surface of the supporting substrate 200 is a polished surface, and then thermal oxidation is performed to form a front surface oxide layer and a back surface oxide layer 220 on the front and back surfaces of the supporting substrate, respectively, wherein the front surface oxide layer is to serve as an insulating layer 210. The thickness of the silicon dioxide is preferably 0.5-1 um.
Referring to step S104 shown in fig. 4, plasma surface activation is performed on the surface of the insulating layer 210 of the supporting substrate and the surface of the single crystal substrate silicon layer 100, respectively, and then the two surfaces are bonded together at normal temperature to complete bonding, thereby forming a bonded substrate. Preferably, the plasma treatment is performed in a vacuum chamber using N2 as a gas source.
Referring to step S105, the bonded substrate is subjected to low temperature annealing at an annealing temperature of not higher than 400 ℃.
Because the surface before bonding is subjected to plasma activation treatment in the step S104, the bonding strength can be strong enough only by low-temperature annealing; the annealing atmosphere may be nitrogen, oxygen, or other inert gas. The annealing time is more than 2 hours. The annealing temperature is lower than 400 ℃, so that hot carrier effect can be avoided, and the requirement of the subsequent thinning process on bonding strength can be met. The annealing temperature is preferably 300 ℃ and the annealing time is preferably 3 hours.
Fig. 5 refers to step S106, and the thickness of the single crystal substrate 100 is thinned to a reserved thickness of <80um by using a mechanical grinding thinning manner; preferably, the reserved thickness is 20-40 um;
referring to step S107 in fig. 6, CMP polishing is performed on the mechanically ground and thinned bonded substrate, where the removal amount of polishing is not less than 5um, which not only satisfies the requirement of completely removing the surface stress damage layer caused by mechanical grinding, but also satisfies the requirements of surface roughness and flatness. The removal amount is preferably 8-10 um.
Referring to step S108 in fig. 7, the polished bonded substrate is subjected to high-temperature argon annealing at an annealing process temperature of not less than 1180 degrees for an annealing time of not less than 2 hours in an atmosphere of argon gas. Through high-temperature argon annealing treatment, the bonding strength can be further improved, and the thinned device layer top silicon can form a nearly perfect crystal clean layer area with extremely low COP primary particle defects. The high temperature argon annealing temperature of 1200 ℃ is preferred, and the annealing time is 2 hours.
On the basis of the process for preparing the silicon-on-insulator substrate material by the conventional bonding and thinning process, the invention comprehensively utilizes the plasma surface activation treatment before bonding to improve the bonding strength and combines a two-step annealing mode to prepare the silicon-on-insulator substrate material with the insulating buried layer, which has extremely low primary particle defect density and is almost perfect crystal.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and adjustments can be made without departing from the principle of the present invention, and these modifications and adjustments should also be regarded as the protection scope of the present invention.
Claims (9)
1. A preparation process of a silicon substrate with an insulating buried layer is characterized by comprising the following steps:
s101, providing a monocrystalline silicon substrate, wherein the front surface of the silicon substrate is a polished surface;
s102, providing a supporting substrate, wherein the front surface of the supporting substrate is a polishing surface;
s103, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s104, respectively carrying out plasma surface activation treatment on the polished surface of the monocrystalline silicon substrate and the surface of the support substrate with the insulating layer as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together at normal temperature to form a bonded substrate;
s105, placing the bonded substrate into a furnace tube for low-temperature annealing;
s106, grinding the bonded substrate to a target thickness in a mechanical grinding thinning mode;
s107, carrying out CMP polishing on the bonded substrate to obtain the required flatness and surface roughness;
and S108, performing high-temperature argon annealing treatment on the polished bonding substrate.
2. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: and in the step S101, the monocrystalline silicon substrate is a conventional polished silicon wafer.
3. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: the supporting substrate in S102 is a conventional polished silicon wafer.
4. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: and in S103, the thickness of the oxide layer of the support substrate is 0.1-2 um.
5. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: n is adopted for the surface activation of the plasma in S1042Or O2Or N2/O2The mixed gas is used as a gas source, the activation treatment time is not less than 10 seconds, and then bonding is carried out at normal temperature.
6. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: the process temperature of the low-temperature annealing treatment in the step S105 is not more than 400 ℃.
7. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: and the target thickness of the mechanical grinding in the S106 is 10-50 um.
8. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: and the CMP polishing removal amount in the S107 is not less than 5 um.
9. The process for preparing a silicon substrate with a buried insulating layer according to claim 1, wherein: and the process temperature of the high-temperature argon annealing in the step S107 is not lower than 1180 ℃, and the time is not lower than 2 hours.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115799273A (en) * | 2022-12-21 | 2023-03-14 | 中环领先半导体材料有限公司 | Silicon wafer on insulator, preparation method and semiconductor device |
| CN116053191A (en) * | 2022-12-21 | 2023-05-02 | 中环领先半导体材料有限公司 | Silicon-on-insulator substrate and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115799273A (en) * | 2022-12-21 | 2023-03-14 | 中环领先半导体材料有限公司 | Silicon wafer on insulator, preparation method and semiconductor device |
| CN116053191A (en) * | 2022-12-21 | 2023-05-02 | 中环领先半导体材料有限公司 | Silicon-on-insulator substrate and preparation method thereof |
| CN115799273B (en) * | 2022-12-21 | 2024-02-09 | 中环领先半导体科技股份有限公司 | Silicon-on-insulator wafer, preparation method and semiconductor device |
| CN116053191B (en) * | 2022-12-21 | 2024-02-09 | 中环领先半导体科技股份有限公司 | Silicon-on-insulator substrate and preparation method thereof |
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