CN1241803A

CN1241803A - Process for manufacturing semiconductor substrate as well as semiconductor thin film and multilayer structure

Info

Publication number: CN1241803A
Application number: CN 99109898
Authority: CN
Inventors: 坂口清文; 米原隆夫; 佐藤信彦
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1998-05-15
Filing date: 1999-05-14
Publication date: 2000-01-19

Abstract

A process for manufacturing a semiconductor substrate, comprising the step of preparing a first substrate which has a surface layer portion subjected to hydrogen annealing, the separation-layer formation step of implanting ions of hydrogen or the like into the first substrate from the side of the surface layer portion, thereby to form a separation layer, the adhesion step of bonding the first substrate and a second substrate to each other so that the surface layer portion may lie inside, thereby to form a multilayer structure, and the transfer step of separating the multilayer structure by utilizing the separation layer, thereby to transfer the less-defective layer of the surface layer portion onto the second substrate. The less-defective layer is a single-crystal silicon layer in which defects inherent in a bulk wafer, such as COPs and FPDs, are decreased.

Description

Process for producing semiconductor substrate, semiconductor thin film, and multilayer structure

The present invention relates to a semiconductor substrate and a process for producing asemiconductor thin film. More specifically, the present invention relates to a process for producing a semiconductor substrate including a single crystal semiconductor layer over an insulating layer and a single crystal compound semiconductor layer over a Si (silicon) substrate. Further, the present invention relates to a multilayer structure suitable for manufacturing an electronic device or an integrated circuit over a single crystal semiconductor layer, and a manufacturing process of the multilayer structure.

The formation of a single-crystal Si semiconductor layer on an insulator is a well-known "silicon-on-insulator" (SOI) technology, and devices using SOI technology have many advantages not attainable by conventional bulk silicon substrate fabrication of Si Integrated Circuits (ICs), and thus many studies have been conducted. More precisely, the use of SOI technology can bring the following advantages:

1, medium isolation is easy to realize so as to improve the integration level;

2, the radiation protection performance is excellent;

3 stray capacitance can be reduced to achieve higher operation speed;

4 the step of forming the well can be omitted;

5 the device is prevented from latching;

6 due to the thin film, a fully depleted FET (field effect transistor) can be fabricated.

(these features have been described in detail in some specialty journals, e.g., "Single-crystal silicon non-Single-crystal Instrument", by G.W.Cullen, Journal of Crystal growth, Volume 63, No3, pp 429-590 (1983).)

Moreover, in recent years, a large number of papers have reported that using SOI as a substrate can achieve higher operation speed and reduce power consumption ofMOSFET (Metal-Oxide-Semiconductor field Effect transistor) (IEEE SOI conference, 1994).

Further, since the SOI structure is covered with the SOI layer via an insulating layer on the support substrate so that the insulating layer is located below the circuit element, it is possible to simplify the element isolation process as compared with the case where the circuit element is formed on one silicon wafer. As a result, the manufacturing process of the circuit device can be shortened by using the SOI structure.

That is, the fabrication of a MOSFET or IC on an SOI substrate can both improve its performance and reduce the cost of the wafer and the overall cost of the processing process as compared to fabrication directly on a silicon wafer.

In all such devices, the driving force is enhanced to increase the operating speed of a fully depleted metal oxide field effect transistor (FD MOSFET) and to reduce its power consumption, and in general, the threshold voltage of a MOSFET is determined by the impurity concentration of its channel, but in the case of FD MOSFET using SOI, the thickness of its depletion layer is affected by both the thickness of the SOI layer and the quality of the SOI layer.

Therefore, there has been a demand for a method for manufacturing a large scale integrated circuit (LSI) having a uniform SOI film thickness and a high SOI film quality at a good applicable ratio.

Since 1970, research into forming SOI substrates has been quite intense. In the early days, the hot spot of research was the SOS process (silicon on sapphire), in which single crystal silicon was heteroepitaxially grown on a sapphire substrate as an insulator. There is also the FIPOS process (porous silicon oxide full isolation) which is based on oxidation of porous silicon and implantation of oxygen ions to form dielectric separation to form SOI structures.

In addition to the above-mentioned manufacturing process of the SOI substrate, a manufacturing process of the SOI substrate called "bonding or bonding technique" has been proposed in recent years.

Such bonding techniques have been described by Bruel in Electronic letters, 31(1995), p, 1201 ", and Japanese patent application publication No.5-211128, U.S. Pat. No.5,374,564.

This bonding technique is also called "Smart Cut Process" (registered trademark), and is mainly composed of 5 steps, which will be described below with reference to the drawings.

(first step) As shown in FIG. 24, a 1 st silicon substrate (bulk wafer) 41 having an oxide film 43 on its surface is prepared.

(second step) the 1 st silicon substrate is implanted with hydrogen ions from the oxide film side 43 (FIG. 25). These hydrogen ions are implanted to a desired depth of the substrate 41 to be separated by a later step, at the implanted region of the hydrogen ions. A layer (44) of microbubbles called "microbubbles" or "micropores" is formed.

(third step) the 1 st silicon substrate (41) obtained above and the 2 nd silicon substrate (46) as a support substrate are bonded to each other with the oxide film 43 interposed therebetween (fig. 26).

After the bonding (fourth step), the resultant structure is subjected to a heat treatment at a low temperature of 400-600 c or the like, and thus, as shown in fig. 27, the 1 st substrate 41 bonded to the 2 nd substrate 46 is separated at the boundary of the micro bubble layer (44). More specifically, this is due to the heat treatment realigning the crystals of the microbubble layer (44) and also causing the microbubbles to coalesce to form macrocells that exert strain pressure on and near the microbubble region. As a result, the substrate (41) is separated at the bubble layer (44).

(fifth step) then, the resultant structure including the support substrate (46) is subjected to heat treatment at a high temperature to stabilize the bonding surface and improve the bonding strength, and then, the microbubble layer (44) remaining on the SOI layer (42) as shown in fig. 27 is polished away as shown in fig. 28.

Through the above steps, the 1 st silicon substrate is partially transferred onto the 2 nd substrate, and thus an SOI substrate can be obtained.

When the SOI layer is formed by implantation of hydrogen ions or the above-described steps, the thickness of the SOI layer is substantially determined by the ion implantation region, and therefore, it is important how to control the desired ion implantation region (the thickness of the SOI layer).

Further, since the SOI layer itself is formed on the basis of a bulk wafer, it contains defects or defects inherent to the bulk wafer, such as OSF (oxidation induced stacking faults), COP (crystal originated particles) and FPD (flow state defects).

Since the leakage current increases when there is an OSF defect in the device operating region near the wafer surface, it is desirable to provide a process for manufacturing an SOI substrate which has no defects such as OSF or the like or has fewer defects.

OSF and COP will be explained later (Hidekaze Yamamoto: "Problem of Large-diameter Silicon Wafer to be Solved", 23^rdUltraclean TechnologyCollege(Aug.1996))and the FPD(T.Abe：Extended Abst.Electrochem.Soc.，Spring Meeting，vol.95-1p.596(May，1995))。

An object of the present invention is to provide a process for producing a semiconductor thin film which has less defects and whose thickness is highly uniform.

It is another object of the present invention to provide a process for manufacturing an SOI substrate in which the thickness of an SOI layer is highly uniform.

It is another object of the present invention to provide a process for the manufacture of semiconductor films which are free from or less defective in bulk silicon wafers such as OSF, COP and FPD.

It is a further object of the present invention to provide a process for manufacturing an SOI substrate that is based on bonding techniques and that makes it possible to make good use of the substrate material and to make the process economically feasible.

Incidentally, the present invention expresses the "SOI substrate" and includes not only a substrate having a single crystal silicon semiconductor layer on an insulator. But also a substrate having a compound semiconductor layer such as GaAs, InP, or the like on a support substrate.

The manufacturing process of the semiconductor substrate of the present invention is characterized by comprising the steps of: preparing a first substrate 1 having a surface layer portion subjected to hydrogen annealing; a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen and a rare gas into the 1 st silicon substrate from a side near the surface layer portion; a bonding step of bonding the 1 st substrate and the 2 nd substrate to each other with the surface layer portion inside, thereby forming a multilayer structure; and a transfer step of separating the multilayer structure by a separation layer, so that at least a part of the surface layer portion is transferred onto the 2 nd substrate.

The manufacturing process of the semiconductor substrate of the present invention is further characterized in that: the number of COPs per unit wafer in the surface layer portion of the 1 st substrate transferred onto the 2 nd substrate decreases with the depth of the surface layer portion when measured from the outer surface thereof.

The manufacturing process of the semiconductor substrate of the present invention is further characterized in that: and a step of performing heat treatment on the surface layer portion of the 1 st substrate transferred onto the 2 nd substrate in a reducing atmosphere containing hydrogen after the transfer step.

In another aspect, the present invention provides a process for manufacturing a semiconductor substrate, comprising: a step of preparing a 1 st silicon substrate having a surface layer portion subjected to hydrogen annealing; a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas into the 1 st silicon substrate from a side near the surface layer portion, thereby forming a separation layer; a step of bonding the 1 st substrate and the 2 nd substrate to each other, thereby forming a multilayer structure; a step of heat-treating the 1 st and 2 nd substrates at a first temperature at or after the formation of the multilayer structure; a transfer step of separating the multilayer structure on the separation layer, thereby transferring at least a part of the surface layer portion of the 1 st substrate to the 2 nd substrate; and a step of heat-treating the surface layer portion transferred onto the 2 nd substrate at a second heat treatment temperature higher than the first heat treatment temperature.

Further, a process for producing a semiconductor thin film of the present invention is characterized by comprising: a step of preparing a 1 st silicon substrate having a surface layer portion subjected to hydrogen annealing; a separation layer forming step of implanting ions of at least one element selected from the group consistingof hydrogen, nitrogen, and a rare gas into the 1 st silicon substrate from a side closer to the surface layer portion, thereby forming a separation layer; and a separation step of separating at least a part of the surface layer portion of the separation layer.

Further, a process for producing a semiconductor substrate of the present invention includes: a step of heat-treating the silicon substrate in a reducing atmosphere containing hydrogen; a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas into the silicon substrate from a side near the surface layer portion, thereby forming a separation layer; a step of bonding the silicon substrate and the 2 nd substrate to each other, thereby forming a multilayer structure; a transfer step of separating the multilayer structure at the separation layer, thereby transferring at least a part of the surface layer portion to the 2 nd substrate.

The multilayer structure according to the present invention is a multilayer structure in which a 1 st silicon substrate and a 2 nd substrate are bonded to each other, the 1 st silicon substrate including a separation layer formed by implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas; characterized in that the 1 st silicon substrate includes a surface layer portion whose surface is formed by hydrogen annealing.

The process for peeling a semiconductor film of the present invention is characterized by comprising: a step of preparing a 1 st silicon substrate having a surface layer portion subjected to hydrogen annealing; a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas into the 1 st silicon substrate from a side near the surface layer portion, thereby forming a separation layer; and a step of peeling off at least a part of the surface layer portion by using the separation layer.

FIG. 1 is a flowchart showing an example of a process for manufacturing a semiconductor substrate according to the present invention;

FIGS. 2, 3, 4,5 and 6 are schematic cross-sectional views showing an example of a process for manufacturing a semiconductor substrate according to the present invention;

FIGS. 7, 8, 9, 10 and 11 are schematic cross-sectional views showing another example of a process for manufacturing a semiconductor substrate according to the present invention;

FIGS. 12, 13 and 14 are schematic sectional views showing still another example of a semiconductor substrate manufacturing process according to the present invention;

FIG. 15 is a schematic sectional view showing a case where hydrogen annealing is performed using a vertical type batch furnace for heat-treating a wafer;

FIG. 16 is a graph showing the temperature dependence of the etch rate as a function of surface material relative to the substrate in accordance with the present invention;

FIG. 17 is a graph showing the amount of hydrogen anneal etching in the case of silicon versus silicon dioxide control in accordance with the present invention;

FIG. 18 is a graph showing the number of silicon atoms removed by hydrogen annealing in the case of silicon versus silicon dioxide control in accordance with the present invention;

FIG. 19 is a schematic sectional view showing an example of arrangement in the case where the material of the opposite surface is a silicon dioxide layer in the present invention;

FIGS. 20 and 21 are schematic sectional views for explaining the operational effect of the etching method according to the present invention;

FIG. 22 is a schematic sectional view showing that a semiconductor substrate is set in a vertical type furnace in the present invention;

FIG. 23 is a graph showing a relationship between a depth from a wafer surface and the number of COPs per unit wafer;

fig. 24, 25, 26, 27 and 28 are schematic sectional views showing a conventional SOI substrate manufacturing process;

fig. 29, 30 and 31 are schematic cross-sectional views showing an example of a process for manufacturing an SOI substrate.

First, the present invention will be described with reference to fig. 1, which illustrates a process flow for manufacturing a semiconductor substrate in fig. 1.

A 1 st substrate is prepared. The surface layer portion on at least one principal plane of the substrate is subjected to hydrogen annealing (step S1).

Next, ions such as hydrogen are implanted into the 1 st substrate. Thereby forming a separation layer at a predetermined position (step S2).

Further, the 1 st substrate and the 2 nd substrate are bonded to each other. So that the principal plane thereof is located inside to form a multilayer structure (step S3).

Then, the multilayer structure is separated by the separation layer (step S4).

By the above-described steps S1 to S4, and completing step S5, an SOI substrate can be manufactured. Such a substrate has a thin film whose thickness is uniform and in which the number of defects such as OSF and COP is extremely small.

Hereinafter, the present invention will be described in detail with reference to fig. 2 to 6.

A 1 st substrate (10) is prepared having a surface layer portion (12) with one major surface hydrogen annealed as shown in fig. 2. The surface layer portion (12) is formed in such a manner that a bulk wafer serving as a seed crystal is heat-treated in a reducing atmosphere containing hydrogen (hereinafter, this heat treatment is referred to as hydrogen annealing). The expression "surface layer portion" in the present invention means a layer (low-defect layer) in which the defects caused by bulk wafers such as OSF, COP and FPD are reduced in number or eliminated (hereinafter, "surface layer portion" is also expressed as "low-defect layer").

Reference numeral 11 denotes such a region. The effect of reducing defects such as OSF and COP is reduced by hydrogen annealing, and it is needless to say that the 1 st substrate (10) can be entirely formed with the low-defect layer (12). Although fig. 2 shows the low-defect layer (12) and the region (11) as abruptly changing at a certain boundary, in practice, they gradually change without any strict boundary. Both surface layers of the No. 1 substrate (10) may be low-defect layers.

It is also possible to perform subsequent steps after forming a circuit element such as a MOSFET on the low-defect layer (12).

Subsequently, as shown in fig. 3, ions such as hydrogen are implanted into the 1 st substrate (10), so that a separation layer (14) is formed.

The separation layer (14) needs to be formed within the low-defect layer (12) or at the interface between the region (11) and the low-defect layer (12). When the separation layer (14) is formed in the low-defect layer (12), the low-defect layer (12) is divided into a layer (16) (hereinafter referred to as an "SOI layer") covering the separation layer (14) and a layer (17) below the separation layer. In other words, the separation layer (14) may also be formed within the region (11).

The insulating layer (13) may be formed before or after ion implantation. An insulating layer (13) separates the bonding interface from the active layer (SOI layer) (16). In particular, the insulating layer (13) is formed before the ion implantation step, and the surface of the low-defect layer can be effectively prevented from being roughened by the ion implantation. In particular, when the low-defect layer (12) is oxidized to form the insulating layer (13), in fact, by bonding the resultant 1 st substrate 10 to the 2 nd substrate 15, it can be used as a buried oxide film of an SOI wafer.

Next, the No. 1 substrate (10) is bonded to the No. 2 substrate (15) so that the low-defect layer (12) is located in the middle. Thus, a multilayer structure (18) is formed (shown in FIG. 4).

Thereafter, as shown in fig. 5, the multilayer structure (18) is separated by means of the separation layer (14), wherein the multilayer structure (18) is separated either within the separation layer (14) or at the interface of the separation layer (14) near the region (11) or near the SOI layer (16). The multilayer structure (18) may also be separated such that a portion is within the separation layer (14) and another portion is spaced at the interface of the separation layer.

Thus, the semiconductor substrate is formed such that the SOI layer (16) is transferred onto the 2 nd substrate (15), as shown in fig. 5. Since the SOI layer (16) is formed on the basis of the low-defect layer (12), it is completely free from, or eliminates, defects such as OSF, COP, etc., which are peculiar to bulk wafers.

When the separation layer (14) is formed in the region (11), unnecessary portions of the region (11) and the like can be removed by polishing, etching with a liquid etchant, or hydrogen annealing etching after the transfer step until the SOI layer (16) (low-defect layer (12)) is exposed.

According to the present invention, particularly when the separation layer (14) is formed in the low-defect layer (12), implanted ions are less scattered by defects such as OSF, COP, and the like in the separation step. Therefore, the separation layer formed is more uniform than the separation layer formed in the region having a large number of COP defects. In other words, this improves the uniformity of the thickness of the SOI layer (16).

Furthermore, after the separation, a part of the separation layer (14) and/or a part of the region (11) remains on the SOI layer (16), and they must be removed, so that the semiconductor substrate referred to in the present invention is completed (fig. 6).

Incidentally, the 1 st substrate (particularly, the region (11)) obtained after the separation can be reused for manufacturing the semiconductor substrate as described above. In this case, when a part of the separation layer (14) is left on the region (11), it is removed, and when the surface of the 1 st substrate is too rough to meet the requirements, the resulting 1 st substrate (10) is subjected to the flattening treatment and then used as a new 1 st substrate. Of course, it can also be used as the 2 nd substrate (15).

If the low-defect layer (12) formed in advance is relatively thick, hydrogen annealing may not be required when the substrate (10) is reused next time as the 1 st substrate (10).

Now, the respective constituent parts and process steps of the semiconductor substrate according to the present invention will be described in detail.

(1 st substrate)

Bulk silicon wafers, particularly CZ silicon wafers, are used as feedstock for the No. 1 substrate (10).A1 st substrate 10 having a surface layer portion 12 is appropriately used, and a raw material wafer is subjected to hydrogen annealing to reduce the number of COP (Crystal originated particle) defects therein.

The "CZ silicon wafer" is a silicon substrate produced by a pulling method (Czochralski method). CZ wafers contain a large number of defects inherent to bulk wafers, such as OSF (oxidation induced stacking faults), COP and FPD (flow defects).

Here, OSF is a minute defect induced in the growth of a crystal wafer, which is so minute that the oxidation process takes it as a nucleus. For example, on a wafer surface that is subjected to wet oxidation, a ring-shaped OSF is sometimes seen.

On the other hand, the "COP" and the "FDP" are observed without any heat treatment, it is considered that the same cause causes defects (defects in generation), and they are not strictly defined or distinguished. However, roughly speaking, the former defect "COP" refers to an etch pit that can be detected by a fine grain detector or a foreign matter detection device based on the principle of light scattering, before detection, the wafer is immersed in SC-1 (NH)₄CH/H₂O₂: ammonia water/hydrogen peroxide) solution, which is a constituent solution of the RCA cleaning solution. While the latter defect "FDP" refers to the wafer being immersed in Secco (K)₂Cr₃O₇/HF/H₂O) about 30 minutes later, pits were observed with an optical microscope.

Incidentally, the causes of defects such as "OSF", "COP", "FPD", and the like have not been clarified yet. However, it has been reported that all of these defects are closely related to the concentration of oxygen in the Wafer, and that defects such as these "OSF" may be generated when the oxygen concentration is high (see, for example, "Problim of silicon Crystal and Wafer technology" issued by Reaize Inc., p.55).

Next, the low-defect layer (12) formed by hydrogen annealing will be explained.

Usually, CZ silicon wafer contains oxygen atomsOf the order of 10¹⁸Atom/cm³. When the wafer is hydrogen annealed, oxygen contained in the wafer diffuses out, reducing the oxygen concentration at the wafer surface and in the vicinity thereof.

Due to the reduction of the oxygen concentration, the surface layer portion of the wafer is reformed, thus forming a low-defect layer (12) in which the number of defects such as COP, OSF and the like is reduced. For example, the "OSF" defect occurs such that oxygen atoms accumulate as precipitation nuclei and oxygen precipitation occurs, and on the upper side thereof, a defect (stacking fault) grows with the precipitation nuclei as the origin.

Further, the COP density in the CZ silicon wafer was 10⁵-10⁷/cm³For example, in the case of an 8-inch CZ wafer, for example, in the vicinity of its surface layer there are COP in the order of 400-500/unit wafer. However, when the CZ wafer was subjected to hydrogen annealing, the number of COPs in the vicinity of the surface layer suddenly decreased to about 10. This is to form a substantially defect-free layer (DZ layer: gettering layer). Incidentally, the "number per unit wafer" in the present invention means the number of defects such as "COP" in the surface area occupied by one wafer. For example, for an 8 inch wafer, the "number of wafers per unit" would correspond to about 324cm²Number of COPs on.

Thus, when a CZ silicon wafer after hydrogen annealing is used, defects existing in the SOI layer (16) transferred onto the 2 nd substrate (15) are eliminated or reduced, thereby immediately improving the thickness uniformity of the SOI layer (16).

The thickness of the low-defect layer (12) formed by hydrogen annealing is preferably on the order of 500-.

The oxygen concentration of the low-defect layer (12) should be 5X 10¹⁷Atom/cm³Or below, preferably 1X 10¹⁷Atom/cm³Or less, and preferably 5X 10¹⁶Atom/cm³Or the following.

Further, the oxygen concentration of the separation layer formed by ion implantation is required to be within the above-mentioned specific range.

COP density per unit volume of the low-defect layer should be at 0/cm³To 5X 10⁶Per cm³Or below, and if preferred at 0/cm³To 1X 10⁶Per cm³Or below, preferably at 0/cm³To 1X 10⁵Per cm³Or the following. In particular, the COP density in a depth region extending from the outermost surface of the surface layer portion (12) to within the projected range of ion implantation is required to be within the above-mentioned predetermined value.

Further, in the case of an 8-inch wafer, the number of COP per unit wafer in the low-defect layer (12) should be 0 to 500 or less, preferably 0 to 100 or less, more preferably 0 to 50 or less, and most preferably 0 to 10 or less. Incidentally, the COP distribution of the wafer surface is such that COPs have a strong tendency to concentrate toward the vicinity of the center of the wafer (within a range extending from the center by about 6 cm). It is therefore desirable that the number of COPs per unit wafer be approximately equal to the number of COPs in an 8-inch wafer, or even in a 12-inch or larger wafer.

In addition, the number of COP per unit area of the wafer surface should be 0/cm²To 1.6 pieces/cm²Or lower at 0/cm²To 0.5 pieces/cm²Preferably, theconcentration is 0/cm²To 0.05 pieces/cm²It is more preferable.

Further, the COP density per unit volume (or per unit area) in the separation layer (14) is also required to be within the above range.

Also, the number of FPDs per unit area in the low-defect layer (12) should be 0/cm²To 500 pieces/cm²Or below, and preferably should be at 0/cm²To 100/cm²Or the following.

Furthermore, in the case of a specific low-defect layer (12) OSF, the OSF density per unit area should be at 0 defects/cm²To 100 defects/cm²Or the following; preferably at 0/cm²To 50/cm²Or the following; and more preferably at 0/cm²To 10/cm²Or the following.

A1 st substrate (10) is heat-treated in a reducing atmosphere containing hydrogen to form a low-defect layer (12). The atmosphere may be hydrogen gas or a mixed gas containing hydrogen gas and a rare gas (e.g., Ar, He, Ne, Xe, Kr).

The temperature of the hydrogen anneal should be from 500 ℃ up to below the melting point of the No. 1 substrate material 10; preferably from 800 c to below the melting point of the 1 st substrate material 10 and most preferably from 1000 c to below the melting point of the 1 st substrate material 10.

In the case where the silicon substrate (the melting point of silicon is approximately 1412 c) is the 1 st substrate (10), it is preferable that the annealing temperature be 800 to 1350 c in consideration of the oxygen diffusivity and the bearing capacity of the heat treatment furnace. Preferably between 900 and 1250 deg.c.

The hydrogen-containing atmosphere pressure for the hydrogen annealing may be atmospheric pressure, reduced pressure or increased pressure. At atmospheric pressure, or at atmospheric pressure (1X 10)⁵Pa) to 1X 10⁴It is appropriate to perform hydrogen annealing at a pressure between Pa. At about 100mmH below atmospheric pressure₂It is more preferable to perform hydrogen annealing under reduced pressure of O. In particular, when hydrogen annealing is performed under reduced pressure, defects such as COP can be more effectively reduced due to oxygen out-diffusion, and the effect of reducing defects is also related to the structure of the heat treatment furnace.

The furnace for hydrogen annealing may be a vertical type heat treatment furnace or a horizontal type heat treatment furnace which is generally used, and the usable heater is any one of a resistance type heater, a radio frequency heater, or the like.

On the other hand, hydrogen annealing may be performed by a heat lamp using heat radiation or by RTA (rapid thermal annealing). In this case, the rapid annealing device may be, for example, an infrared annealing device based on a halogen lamp, an arc lamp, or the like, or a flash lamp annealing device based on a xenon flash lamp or the like. In particular, in the case of using a heating lamp, hydrogen annealing can be completed in a short time.

The time required for hydrogen annealing should be between several seconds and several tens of hours, but is preferably between several seconds and several hours.

Incidentally, in the case of the low-defect layer (12) formed by hydrogen annealing a CZ silicon wafer, the number of defects per unit wafer on the outermost surface thereof is the smallest, and the number of defects increases in a deeper portion of the wafer. However, in the case of manufacturing an SOI substrate by a bonding technique (bonding method), the number of COPs in the SOI layer (16) shown in fig. 6 is the smallest at the interface between the insulating layer (13) and the SOI layer (16), and the number of COPs in the outermost surface of the SOI layer (16) is the largest.

After the SOI layer (16) is exposed by the separation process, hydrogen annealing is also performed to further reduce the COP number on the outermost surface of the SOI layer (16). Thus, an SOI layer (16) having both surfaces subjected to hydrogen annealing can be obtained. Particularly, in the case where a CZ silicon wafer is subjected to hydrogen annealing for several seconds to 3 hours or the like to form a low-defect layer (12), it is more desirable to perform hydrogen annealing on both sides thereof.

Further, the material of the 1 st substrate (10) subjected to hydrogen annealing is not limited to a CZ silicon wafer, but a silicon wafer produced by an MCZ method (magnetic controlled czochralski method) (hereinafter referred to as "MCZ silicon wafer") is also applicable. It has been reported that MCZ silicon wafers inhibit the increase in the size of COPs present in silicon compared to CZ silicon wafers ("Electronic Materials", June Issue (1998), p., 22). Upon hydrogen annealing, the MCZ silicon wafer is capable of forming a low-defect layer (12) of better quality than CZ silicon wafers.

In addition, in the case of using silicon as the 1 st substrate (10), it is possible to use a P-type or N-type CZ silicon wafer having a resistivity of 0.1-100. omega. cm, but it is more appropriate to use a CZ wafer having a resistivity of 0.5-50. omega. cm.

Considering that impurity elements such as boron and phosphorus can be diffused from silicon by hydrogen annealing, the resistivity of the CZ silicon wafer used as a substrate subjected to hydrogen annealing is preferably lower than the above resistivity, however, the low-defect layer (12) itself should preferably be of P-type or N-type, having a resistivity of 0.1-100. omega. cm, and more preferably 0.5-50. omega. cm.

Of course, wafers of unspecified concentration or reused wafers may also be used if the desired SOI layer (16) is obtained. When the specification of the SOI layer of the SOI wafer requires a resistivity outside the above range, it is desirable to use a silicon wafer having a resistivity that meets the specification.

Further, the material of the 1 st substrate (10) is not limited to a CZ or MCZ single crystal silicon substrate, and it may be any of a Ge substrate, a SiC substrate, a SiGe substrate, a GaAs substrate, an InP substrate, and the like.

Further, when the material of the 1 st substrate (10) is a silicon substrate, a silicon oxide layer can be used as the insulating layer (13) by oxidizing the surface of the substrate. The insulating layer (13) can be preferably realized by forming a silicon nitride layer by depositing a silicon oxide film or a silicon nitride film on the surface of the low-defect layer (12) by nitriding the surface of the silicon substrate or by a CVD (chemical vapor deposition) method.

The thickness of the insulating layer (13) is preferably several nm to several μm.

Of course, it is also possible to omit the formation of the insulating layer (13) on the 1 st substrate (10), or the formation of the insulating layer (13) on the 1 st substrate (10) and the 2 nd substrate (15) in advance.

(ion implantation)

The ions to be implanted for forming the separation layer (14) may be ions implanted with hydrogen or a rare gas such as helium, neon, krypton, or xenon, or nitrogen ions alone or in combination with any of the above elements. It is possible to implant such as H even with the same element⁺And H₂ ⁺Such ions of different masses may therefore facilitate the separation of the multilayer structure (18). The step of ion implantation is not limited to the step of implanting ions of the same element at once, but may be performed by multiple times of implantation so as to have the same projection range. The type, energy, dose, etc. of the implanted ions are varied in steps and are also suitable for trying to form the insulating layer (14). In particular, it is suitable to form a separation layer (14) which, due to its close transfer to the 2 nd substrate (15) acting as a support substrate, performs a separation step, as desired, in order to have a lower or higher mechanical strength. Generally, when implanting ions in a doseThe larger the size of the microbubbles increases, the lower the mechanical strength of the injection zone becomes.

The ion implantation may be performed by setting an acceleration voltage in a range of 1KeV to 10 MeV. Since the thickness of the implanted layer (14) varies with the acceleration voltage, the acceleration voltage is preferably set to the order of tens of KeV to 500KeV to satisfy the required conditions.

In summary, it is important to perform ion implantation so that the multilayer structure (18) can be easily separated at the separation layer (14).

In the invention, the ion implantation is carried out, and the ion implantation is also suitable for obtaining uniform implantation depth and projection range R of the ion implantation_pThe (depth of implantation) should be within the low-defect layer (12). The thickness of the SOI layer (16) is typically a few nanometers to 5 microns.

The thickness of the separation layer (14) formed by ion implantation is usually 0.5 μm or less. In particular, in order to form a thin film (12) having a uniform thickness, which is to be transferred onto a No. 2 substrate (15), the thickness of the separation layer is preferably several thousand angstroms or less. The separation layer (14) comprises, for example, a projected range of ion implantation.

The implantation dose can be 1.0 × 10¹⁵/cm²To 1.0X 10¹⁸/cm²But preferably in the range of 1.0X 10¹⁶/cm²To 2.0X 10¹⁷/cm²。

The temperature of ion implantation is preferably in the range of-200 ℃ to 600 ℃; more preferably below 500 ℃; preferably below 400 deg.c. This is because, when the temperature exceeds 500 ℃, implanted ions accumulated in the vicinity of the projection range are rapidly emitted from the 1 st substrate (12), so that a separation layer (microbubble layer) (14) cannot be formed.

Another method for forming the separation layer is a plasma ion implantation method which permeates hydrogen ions into a desired region of the 1 st substrate by using plasma. Using plasma, an ion-implanted layer (separation layer 14) can be formed in a shorter time and with a more uniform thickness than in the conventional ion implantation method.

(bonding)

The aforementioned 2 nd substrate (15) bonded to the 1 st substrate (10) is of the kind of a single crystal silicon substrate, a polycrystalline silicon substrate, an amorphous silicon substrate, a sapphire substrate, a light-transmitting substrate such as a quartz substrate or a glass substrate, a metal substrate of aluminum or the like, a ceramic substrate of aluminum oxide or the like, a compound semiconductor substrate of GaAs, InP or the like. The type of the 2 nd substrate is suitably selected in accordance with the intended use of the finished product, including the SOI layer (16). The 1 st substrate (10) can also be bonded to a substrate of plastic or the like, if the latter is suitably flat.

It is also suitable to form an insulating layer on the bonding surface of the No. 2 substrate (15).In the bonding of the 1 st substrate and the 2 nd substrate, an insulating sheet is sandwiched therebetween well, thereby forming a three-layer-stacked structure. When a light-transmitting substrate is used as the No. 2 substrate (15), a photosensor or a touch sensor of a projection type liquid crystal image display panel can be constituted. In this case, a high-performance driving element can be manufactured which is sufficient to improve the pixel density of the sensor or display panel and the resolution and definition of the sensor or display panel.

A1 st substrate (10) and a 2 nd substrate (15) are bonded at room temperature to form a multilayer structure (18).

In this case, before bonding, if the surfaces of the 1 st substrate and the 2 nd substrate are activated in advance with plasma of nitrogen or oxygen, then rinsed with water, and dried. The temperature of the next heat treatment for enhancing the bonding strength can be lowered.

In the case of closely adhering the 1 st substrate (10) and the 2 nd substrate by enhancing the bonding strength, heat treatment is appropriately performed during or after the bonding (hereinafter referred to as "1 st heat treatment"). The 1 st heat treatment is desirably a low-temperature treatment which can be carried out at a temperature of from room temperature to 500 c, preferably from room temperature to 400 c.

It is also suitable to bond the 1 st substrate (10) and the 2 nd substrate (15) by extrusion of the multilayer structure (18) or by anodic bonding, with no heat treatment.

In the case of a protective atmosphere for bonding operation, the 1 st and 2 nd substrates may be bonded under the conditions of atmosphere, oxygen, nitrogen, vacuum, and the like.

The atmosphere of the 1 st heat treatment may be N₂、O₂Oxygen, oxygenA chemical atmosphere, or a combination thereof.

Incidentally, the 1 st substrate (10) may also be bonded to another substrate at a time and thereafter bonded to a desired supporting substrate, instead of being directly bonded to the 2 nd substrate serving as a support.

(separation)

The multilayer structure (18) can be separated or separated by heat treatment. Specifically, the heat treatment is carried out at a temperature of 400 ℃ to 1350 ℃, preferably 400 ℃ to 1000 ℃, more preferably 400 ℃ to 600 ℃.

When the heat treatment as described above is performed, a low-defect layer (12) is peeled off partially or entirely by subjecting the separation layer (14) to an internal pressure due to crystal rearrangement and polymerization of microbubbles in the separation layer (14).

The multilayer structure (18) can also be separated by means of accelerated oxidation of the separation layer (14). More specifically, the ion-implanted layer (separation layer 14) is oxidized from the periphery of the multilayer structure (18). Therefore, the bulk expansion of the ion-implanted layer is large near its periphery, which appears as if a wedge is uniformly wedged into the ion-implanted layer from the periphery. Thus, only the ion-implanted layer is subjected to the internal pressure, while the entire wafer separates the multilayer structure (18) within the ion-implanted layer or at its interface.

Incidentally, the ion-implanted layer and even the peripheral portion are usually covered with a non-porous layer. In this connection, it is also suitable to expose the peripheral portion of the ion-implanted layer or the end face thereof after or before the 1 st substrate and the 2 nd substrate are bonded into the multilayer structure (18). When such a multilayer structure (18) is oxidized, since the ion-implantedlayer has a large surface area, oxidation is rapidly started from the periphery of the ion-implanted layer.

When Si is converted into SiO₂Its volume is enlarged by a factor of 2.27. Therefore, the oxidized ion-implanted layer also exhibits a volume expansion phenomenon under the condition that the porosity is less than 56%. Since the closer to the center of the wafer, the lower its oxidation level. The larger the volume expansion of the oxidized ion implantation layer is at the peripheral portion of the wafer. This phenomenon and the wedge inserting ion implantation from the wafer end faceThe same is true for the case of ingress. Thus, only the ion-implanted layer is subjected to the internal pressure, and the multilayer structure (18) is subjected to a force so as to be separated within the ion-implanted layer. Moreover, oxidation proceeds uniformly at the peripheral edge of the wafer, and thus the multilayer structure (18) is peeled off uniformly from the periphery thereof.

According to the present invention, the rapid oxidation capability of the porous ion-implanted layer, as well as its volume expansion and fragility, are combined by using a conventional Si-IC oxidation process with excellent uniformity. Therefore, the internal pressure generated is made to act only on the porous ion-implanted layer, so that the wafer is separated in the ion-implanted porous layer with good controllability.

Further, the bonded substrate (or laminated substrate) may be separated at the fragile ion implantation porous layer by heating the entire bonded substrate to generate thermal stress by utilizing the fragile characteristics of the multi-layer and ion implantation layer porous materials in the structure of the bonded wafer. The heating in this case may be performed, for example, by heat treatment at a temperature of 1150 ℃ for a duration of 30 seconds.

In the present invention, the porous ion-implanted material is structurally fragile, and when the porous ion-implanted material alone or including its peripheral portion is heated, the porous ion-implanted material can be separated from the multilayer structure (18) by the action of thermal stress, softening or the like.

In particular when heating by means of a laser, it is possible to heat only a specific layer so that it absorbs energy, instead of heating the entire bonded substrate. Here, the local heating may be performed by using a long wavelength laser that can be absorbed only by the ion-implanted porous layer or adjacent to the ion-implanted porous layer. For example, a laser, e.g. CO, may be used₂The output power of the laser is about 500-1000W.

The ion-implanted porous layer may be heated rapidly so that a current flows through the ion-implanted porous layer or in the wafer surface in the vicinity of the ion-implanted porous layer. Heating may also be performed with pulsed current flow.

It is also feasible to use high water pressure jets or the like as an inexpensive way of separating the multilayer structures (18).

The multilayer structure (18) may be separated at the ion-implanted layer (separation layer 14) by the well-known so-called "water jet method" in which a water stream under high pressure is injected from a nozzle.

It is also possible to use, in addition to water, a liquid which is capable of selectively etching the separation areas, such as, for example, an organic solvent, an acid such as alcohol, fluoric acid or nitric acid, or a base such as potassium hydroxide. Further, a gas such as air, nitrogen, carbon dioxide, or a rare gas can also be used as a good ejection fluid. Cryogenic fluids or extremely low temperature liquids can be used.

An electron beam, gas, or plasmacapable of etching the separation region may also be used.

The separation zones can be removed from the end faces of the multilayer structure 18 by injecting or spraying water streams into the separation zones in line with the bonding seams on the side faces. In this case, first, the jet of water is directly injected to the separation layer exposed at the end face of the bonded substrate and the separation region thereof near the 1 st and 2 nd substrate member portions. Thus, the jet of water removes only the frangible separation zone without damaging the discrete substrate body members until the bonded substrates separate. Even if the detachment zone is not previously exposed but is for some reason covered by a thin layer, it is possible to eject a jet of water, first to remove the layer covering the detachment layer and then to continue to remove the exposed detachment layer. In addition, the bonded wafer can also be separated by widening or destroying the fragile separation region by jetting a water jet into the bonded wafer gap on the peripheral end face of the bonded wafer, although this method has not been used frequently so far. In this case, since the intention is to perform cutting or removal, cutting chips of the separation layer are hardly generated. Furthermore, even if the separation region cannot be removed by the jet of water itself, the bonded wafer can be separated without using an abrasive material and without damaging the surface of the separation layer. In this way, the effect can be thought of as a fluid-based wedge effect, unlike cutting and polishing effects. Therefore, in the case where there is a concave slit on the side surface of the bonded wafer body and an external force is present in the direction of the peeling area, such an effect is extremely expected by jetting a jet of water. If this effect proves satisfactory, the shape of the side surface of the bonded substrate body is preferably concave, not convex.

Incidentally, in the case of separation by the jet method, the temperature of the multilayer structure (18) is set to be in the range of-200 ℃ to 450 ℃, preferably in the range of room temperature to 350 ℃.

In addition, for the separation of the multilayer structure (18), the separation layer can be broken by any one of the following methods:

sufficient tension or pressure is applied uniformly over and in the plane of the normal bonded wafer.

Wave energy of the applied ultrasound.

A similar doctor blade edge (e.g., a wedge made of Teflon resin) was used to insert the release layer from the wafer end face (the periphery of the bonded wafer).

Leaving the separation layer exposed at the wafer end face, porous Si is etched to some extent, and the resulting separation layer is inserted with a doctor blade edge or the like.

Exposing the porous layer at the wafer end face, impregnating the porous silicon with a liquid such as water, and then heating or cooling the entire bonded wafer to expand the liquid.

Apply force (shear or rotational force) horizontally to the 2 nd (or 1 st) substrate with respect to the 1 st (or 2 nd) substrate.

That is, only the ion-implanted layer (separation layer 14) is selectively separated by an electroless wet chemical etching method, in which the multilayer structure (18) is immersed in a mixture of hydrofluoric acid or hydrofluoric acid added with at least alcohol and hydrogen peroxide, or in buffered hydrofluoric acid or buffered hydrofluoric acid added with at least alcohol and hydrogen peroxide.

(removal of residue on the 2 nd substrate)

When the separation layer (14) is left on the SOI layer (16) after the multilayer structure (18) is separated by the separation layer (14), a step of removing these residues is required. Of course, if the separation occurs at the interface between the separation layer (14) and the SOI layer (16), then this removal process is not necessary.

Polishing or grinding, in particular Chemical Mechanical Polishing (CMP), is also suitable for eliminating residues on the SOI layer (16). As the polishing agent, any of polishing abrasives such as borosilicate glass, titanium dioxide, titanium nitride, aluminum oxide, ferric nitrate, cerium oxide, colloidal silica, silicon nitride, silicon carbide, graphite and diamond, or H mixed with the above abrasives, may be used as required₂O₂，KIO₃And the like, or a polishing liquid mixed with a strong alkali solution such as NaOH or KOH.

Because of the low mechanical strength and large surface area of the separation layer (14), the invention uses the single crystal layer as a polishing barrier layer, and can realize the removal of the separation layer (14) through selective polishing.

The residues of the separation layer (14) can also be removed by etching.

Here, hydrofluoric acid or nitric acid type, 1, 2-ethylenediamine type, KOH type or hydrazine type may be used as the etchant. Also, a mixed solution of hydrofluoric acid or hydrofluoric acid with at least alcohol or hydrogen peroxide added thereto, or a mixed solution of buffered hydrofluoric acid or buffered hydrofluoric acid with at least alcohol or hydrogen peroxide added thereto is used. Therefore, a solution containing hydrogen fluoride can be used as an etchant.

In the case where the residual separation layer (14) is thin or the multilayer structure (18) is substantially separated at the interface between the SOI layer (16) and the separation layer (14), hydrogen annealing after separation can smooth the surface of the SOI layer (16)

The hydrogen annealing is performed by heat treatment in a reducing atmosphere containing hydrogen. The atmosphere may be hydrogen gas, or a mixed gas of hydrogen gas and other rare gases (e.g., Ar).

The temperature for hydrogen annealing should be in the range of 800-1350 deg.c, preferably 850-1250 deg.c.

The pressure of the hydrogen-containing atmosphere for hydrogen annealing may be atmospheric pressure or reduced pressure. At atmospheric pressure, or at atmospheric pressure (1X 10)⁵Pa)-1×10⁴Hydrogen annealing in the Pa range is suitable, at about less than atmospheric pressure100mH₂It is more preferable to perform hydrogen annealing under a slightly reduced pressure of O.

In the case where the remaining separation layer (14) is removed by hydrogen annealing, the separation layer (14) should be opposed to the silicon oxide.

More specifically, when the remaining separation layer opposite to the silicon oxide is heat-treated, the silicon oxide reacts with silicon constituting the separation layer (14) in an atmosphere as follows:

therefore, the ion implantation residue layer can be effectively removed. Moreover, the conversion of silicon is simultaneously performed so as to lower the surface level, with the result that the surface of the SOI layer (16) is smoothed.

Thus, the single crystal silicon film can have a surface as smooth as a single crystal silicon wafer and can be thinned under control without causing crystal defects such as processing distortion and the like which are caused by polishing the single crystal silicon film formed on the surface of the semiconductor substratematerial. That is, it is possible to simultaneously perform smoothing of the surface of the SOI substrate, lowering of the boron concentration, and etching of silicon without impairing the uniformity of the film thickness between each wafer and the two wafers.

It is also possible to carry out a hydrogen anneal after the separation layer (14) has been partially or completely removed by polishing or etching.

Incidentally, in the case where a separation layer is formed in the ion implantation region (11), the partial region (11) may be removed together with the remaining separation layer (14) by the above-described method.

(removal of residue on the 1 st substrate)

When the separation layer (14) partially remains on a part of the surface of the 1 st substrate obtained after separation of the multilayer structure (18) (for example, in the case of forming a separation layer in the low-defect layer (12), on the region (11) or and on the low-defect layer 17), the residue can be removed by the above-described method, for example, polishing, grinding or etching, followed by a planarization treatment for any surface with unsatisfactory flatness, whereupon the 1 st substrate can be used again as a new 1 st substrate or continued as a 2 nd substrate. Although the surface layer planarization treatment can be preferably performed by a method commonly used in semiconductor processes such as polishing or etching, the surface layer planarization can be performed by heat treatment in a reducing atmosphere containing hydrogen. Depending on the selected conditions, the thermal treatment may planarize the substrate surface to the extent that atomic steps are partially exposed.

Specifically, in the case where the separation layer (14) is formed within the low-defect layer (12), the low-defect layer (17) is located on the region (11) even after the separation. Therefore, a series of process steps for manufacturing the SOI substrate can be performed after the separation layer (14) is formed again in the low-defect layer (17).

In the case of manufacturing an SOI substrate by a bonding method or a bonding method, one SOI substrate is manufactured from two wafers. Here, the 1 st substrate obtained after the separation is used. The SOI substrate can be manufactured more economically.

(annealing after separation)

In the present invention, in order to improve the bonding strength between the support substrate (the 2 nd substrate (15)) and the SOI layer (16) disposed thereon, it is also possible to perform a heat treatment (hereinafter referred to as "the 2 nd heat treatment") after separating the multilayer structure (18) by the separation layer (14).

The temperature of the 2 nd heat treatment is set higher than the temperature of the 1 st heat treatment (low-temperature heat treatment performed during bonding or immediately after bonding) described above. Specifically, the temperature of the 2 nd heat treatment should be in the range of 600-.

In the process after forming the microbubble layer (separation layer 14) in bulk silicon by ion implantation of hydrogen or the like, it is desirable not to perform heat treatment or to perform heat treatment at a lower temperature, except in the case of performing separation by heat treatment. This is because, when the temperature exceeds about 500 degrees, microbubble polymerization occurs, and separation which has not been expected originally occurs. Thus, in the case where the adhesive strength is improved after bonding, it is advantageous to perform the low-temperature heat treatment (1 st heat treatment) at less than 500 ℃.

After the multilayer structure (18) is separated by any practicable method, a heat treatment for improving the bonding strength between the SOI layer (16) and the 2 nd substrate (15) and stabilizing the bonding face of the resulting SOI substrate should be performed at a temperature of the 2 nd heat treatment higher than the temperature of the 1 st heat treatment (for example, about 900 ℃ C.)

When heat treatment is carried out at a high temperature of at least 800-. However, in the present invention, the concentration of oxygen in the low-defect layer is considerably low. Therefore, it is possible to prevent an increase in defects caused by performing a high-temperature heat treatment subsequent to a low-temperature heat treatment.

Finally, according to the invention, a part of the surface layer of the wafer is heat-treated in a hydrogen-containing atmosphere and can be removed and transferred to another silicon wafer by means of an ion-implanted layer. Since the defects inherent in bulk Si near the major surface layer of the wafer (COP, internally generated defects, etc.) can be eliminated by heat treatment, the effective ratio of the device can be increased.

For example, in manufacturing a 16M (megabit) DRAM (dynamic random access memory), the presence of COP is not significantly problematic with respect to the size of COP, with sufficient margin to produce the DRAM. However, when the 16M DRAM is shifted to the 64M DRAM, the elements of each device have a size almost equal to the COP, and thus, the effective use ratio of the device is drastically reduced because of the COP. Therefore, the present invention is very effective from the viewpoint that the number of COPs in the SOI layer (16) of the SOI substrate can be made extremely small.

The heat treatment of the wafer in the hydrogen-containing atmosphere has no doubt an advantage in cost and mass production, and it will replace the wafer having an epitaxial thin film. It is said that the diameter of the wafer will increase in the future, which makes it difficult to draw a high quality crystal. Further, bulk wafer quality may also degrade. It is therefore useful to manufacture an SOI substrate using a wafer including a heat-treated low-defect layer in a hydrogen-containing atmosphere.

In the following, it should be noted that in the case of removing the separation layer (14) by the process including the hydrogen annealing, the effect of the hydrogen annealing differs depending on the material opposed to the substrate to be processed in the heat treatment furnace and also depending on the distance between the surface opposed to the substrate to be processed and the substrate to be processed.

The surface of the substrate to be processed (SOI layer) is sometimes etched by hydrogen annealing (heat treatment in a hydrogen-containing reducing atmosphere), and the quality of etching differs depending on the material of the opposite surface of the SOI layer, which will be explained in detail below.

In the vertical type batch processing furnace for heat-treating a wafer as shown in fig. 15, the etching rate of each single-crystal silicon layer (SOI layer) greatly varies due to the difference of the material surface (opposed surface) opposed to the surface of the single-crystal silicon layer. In fig. 15, reference numeral 1 denotes a plurality of wafers, reference numeral 2 denotes a core tube made of quartz, reference numeral 3 denotes a heater, and reference numeral 4 denotes a flow of process gas.

FIG. 16 is a graph showing the relationship between the etching rate and the temperature and the opposing surface materials, in which the lower abscissa represents the reciprocal of the temperature in units of the reciprocal of electron volts (eV), the upper abscissa represents the temperature corresponding to 1/T, and the vertical axis represents thelogarithmic curve of the etching rate (nm/min).

In the case of an SOI substrate, the thickness of the SOI layer, i.e., the thickness of the single crystal silicon layer on the buried insulating layer, can be easily measured using a commercially available photorefractive thin film thickness measuring instrument, and is changed during the heat treatment, and the change in the thickness of the film layer (rate of change) before and after the heat treatment can be measured, and the relationship of the rate of change with respect to the etching time can be calculated. Thus, the etching rate can be obtained.

On the graph of FIG. 16, data A represents a base material (material for substrate) SiO to be etched₂The etch rates at the respective temperatures while the counter surface is held in place against the surface material Si. In this case, the activation energy E is calculated from the slope of the approximate line of the curve according to the least square method_aAbout 4.3 eV. In addition, parentheses in the respective description data indicate the materials of the opposing surfaces.

The data B indicates a case where the base material Si is heat-treated while being held in a position facing the surface material Si.

The data C indicates that the base material Si was heat-treated while being held in a position opposed to the facing material Si. In this case, the activation energy E_aApproximately 4.1 eV.

Further, data D represents that the base material SiO₂Opposed to the opposite material SiO₂Is subjected to a heat treatment. In this case, the activation energy E_aAbout 5.9 eV.

As can be seen from the difference between the etching rate data B, C in fig. 16, the etching rate of silicon as a base material increases by about 9times by heat treatment in a hydrogen-containing reducing atmosphere due to the exchange of the opposite material from silicon to silicon dioxide, and is independent of the temperature.

In the case where both the base material and the facing material were single crystal silicon, the etching rate at a temperature of 1200C was about 0.045nm/min, which was quite small (data C of fig. 16). The etching amount after the 60-minute heat treatment is less than 3 nm. On the other hand, in the case where the opposite material of silicon is silicon dioxide, the etching rate at 1200 ℃ is about 0.36nm/min (data B of fig. 16), and the etching amount reaches 21.6nm over one hour, which is equivalent to that of contact polishing.

FIG. 17 illustrates the use of silicon as the base material, SiO₂Is a facing material, and SiO₂The etch amount curve for the base material, silicon, and the opposite material, in both cases. The abscissa represents the etching time (in minutes) and the ordinate represents the etching thickness (in nm). White circles for heat-treated SiO₂(base material) versus Si (opposite material), and the black circles represent the heat treatment of Si (base material) versus SiO₂(opposite material) case. The heat treatment temperature T was 1200 ℃.

As shown in FIG. 17, after the same heat treatment time, the white circles represent heat-treated SiO₂The etching amount of the silicon-based alloy is larger than that of the silicon-based alloy with the black circle representing the heat treatment of the silicon-based alloy₂The etching amount of (2) is large. That is, in SiO₂In the case of heat treatment of silicon facing each other, SiO₂Is etched more (its etching thickness is larger).

FIG. 18 shows the number of Si atoms calculated from the results of FIG. 17, i.e., Si (SiO, which is a base material)₂Held in opposition to the opposing material Si) and SiO₂(substrate material Si opposed to opposite material SiO₂Position (d) of the surface. The abscissa represents the etching time, and the ordinate represents the number of silicon atoms removed (atoms/cm)²). In the graph of FIG. 18, the blank circles, triangles, and squares correspond to SiO₂The surface is black circle, triangle and square corresponding to the silicon surface.

When the etching amounts of silicon dioxide and single crystal silicon shown in fig. 17 were calculated based on the atomic number of silicon, a uniform result was generally obtained as shown in fig. 18. Therefore, it can be said that when the Si surface and SiO opposed to each other are opposed to each other₂In the case of heat treatment of the surfaces, the number of silicon atoms lost from both surfaces is equal.

That is, because of the Si surface and the SiO opposed thereto₂Surface interactions accelerate the etching of silicon. The reaction formula of etching is as follows: wherein the ratio of silicon to silicon dioxide is 1: 1.

In addition, the etch rate of silicon is also affected by the distance between the surface to be etched and the opposite surface. When Si is disposed as the opposite material, the etching rate is limited as the distance between both surfaces is shortened, and when silicon dioxide is disposed as the opposite material, the etching rate is increased as the distance between both films is shortened.

Meanwhile, the etching rate in the heat treatment atmosphere in the absence of a reducing gas typified by hydrogen is significantly lower than that in the hydrogen-containing atmosphere. That is, the presence of a reducing atmosphere typified by hydrogen in hydrogen annealing is onefactor for accelerating etching. On silicon and SiO₂In the case of opposing surfaces, the two surfaces are such thatEtched, whichever surface material reaches the other surface, react with the material of that surface by reacting with a reducing gas, typically hydrogen. By way of example, the reactionIs composed of And . Silicon atoms dissociated from the silicon surface are transported to and reacted with the silicon dioxide surface in the form of a vapor phase, thereby being converted into SiO of a high saturated vapor pressure. Due to SiH₂Is consumed at any time, which promotes etching of the Si surface. Further, when the surfaces of silicon are opposed to each other, the etching rate is not significantly increased due to the following reasons: when the silicon atoms dissociated from the Si surface reach the gas phase saturation concentration, the speed of the subsequent reaction is determined by the diffusion of the gas phase silicon atoms. However, the saturation concentration of dissociated silicon atoms is not high.

On the other hand, in maintaining SiO₂When the surface is opposed to the silicon surface, silicon atoms dissociated from the silicon surface are consumed on the surface of the oxide film, and the reaction proceeds further. Because in SiO₂The SiO generated on the sides of the surface has a high vapor pressure and therefore its reaction rate is more difficult to determine than if the two silicon surfaces were opposed.

In addition, in the case where the single crystal silicon thin film is opposed to a silicon carbide material, the etching amount of the single crystal silicon thin film is substantially equal to that in the case where the opposed surface material is silicon. In addition, when the opposite surface material of the single crystal silicon film layer is silicon nitride, the etching amount thereof is suppressed similarly to the case where the opposite surface material thereof is silicon.

More specifically, the facing surface material is SiO₂The etching amount of the single crystal silicon film is about 10 times as much as that of the other two cases: the single crystal silicon thin film is heat-treated in a hydrogen-containing atmosphere with respect to the opposed surfaces made of silicon or made of a material containing silicon and carbon as its main components and not containing oxygen as its main component.

Further, the distance from the opposed surface to the semiconductor base film to be etched depends on the surface size of the single-crystal silicon thin film as the semiconductor base material. In the case of a semiconductor substrate material having a diameter of at least 100mm or more, if the above-mentioned distance is about 20mm or less, preferably 10mm or less, there is an effect of increasing the etching rate due to interaction with the opposed surface material.

Further, when the heat treatment process is performed in a reducing atmosphere containing hydrogen, the occurrence of oxidizing impurities such as water content and oxygen content in the atmosphere increases the etching rate of the single crystal silicon on the main surface of the semiconductor substrate. In order to suppress the supply of the oxidizing substance, the flow rate of the atmospheric gas in the vicinity of the principal plane is reduced. Thus, the etching component due to the impurity gas is reduced, and the controllability of the etching of the present invention based on the interaction of the opposing surfaces is improved. In the case shown in fig. 19, a single crystal silicon layer (53) formed on the main surface of a semiconductor base material (51) (constituting a wafer 1) through an insulating layer (52) is disposed in a core tube so as to be perpendicular to the gas flow direction, and an opposed surface (55) made of silicon dioxide is also disposed therein so that the gas flow velocity (56) of the atmospheric gas passing through the main surface is substantially almost 0, so that the etching effect based on the opposed silicon oxide is sufficiently exhibited.

Further, in the case of etching silicon as a base material by forming an opposite silicon oxide film on silicon or a material containing silicon and carbon as its main components and containing no oxygen as its main component, that is, not reacting with silicon as a base material by a gas phase, when the silicon oxide film is lost due to a decrease in the thickness thereof upon etching, the etching rate drops to about 1/10. Therefore, by determining the thickness of the silicon oxide film in advance so that the number of silicon atoms contained in the silicon oxide film at this thickness is equal to the number of silicon atoms to be removed from the base silicon at the corresponding thickness, the amount of base silicon to be removed can be controlled. In the case of forming a silicon oxide film by a thermal oxidation method which is often used in a semiconductor process, the thickness of the film should be about 2.22 times the thickness of a silicon layer to be etched.

No significant difference was seen in evaluating the effect of the opposing surfaces in smoothing the rough surface.

FIG. 20 is a schematic cross-sectional side view showing the surface to be smoothed by hydrogen annealing immediately after the removal of the residual separation layer by etching. When the rough surface shown in fig. 21 is subjected to heat treatment in a reducing atmosphere, it can be smoothed to be equivalent to the surface of a commercially available silicon wafer as shown in fig. 21. In fig. 20 and 21, the symbols W3 and W4 refer to SOI substrates.

It has been revealed that when a heat treatment such as hydrogen annealing is performed in a reducing atmosphere and the surface roughness of a single crystal silicon is observed, the height h is several nanometers (nm) to several tens of nanometers and the period p is several nanometers to several hundreds of nanometers, a surface (in fig. 21) which is flat like a single crystal silicon wafer can be obtained, the difference being at a level of several nanometers or less, preferably at a level of 2 nanometers or less under more appropriate conditions.

It is also disclosed that by appropriate selection of the opposing surface material of the SOI layer relative to the SOI substrate, the amount of etching based on hydrogen annealing can be controlled.

The above phenomenon is considered as etching, but is not as precise as surface reconstruction. More specifically, on the rough plane, there are numerous corners having high surface energy, and a large number of crystal planes having higher order crystal plane orientations than the crystal plane orientation of the crystal layer are exposed to the outside. The surface energy levels of these regions are higher than the surface energy levels of the regions associated with the crystal plane orientation of the single crystal surface.

By performing the heat treatment in a reducing atmosphere containing hydrogen, for example, the natural oxide film on the surface layer is removed by the reduction action of hydrogen. Moreover, during the heat treatment, the reduction action is continued without generating a natural oxide film. Therefore, it is considered that the energy barrier for the migration of the surface silicon atoms is lowered, and therefore the silicon atoms excited by the thermal energy migrate to constitute a plane having a low surface energy. Planarization according to the present invention may be more promoted as the crystal plane orientation ofthe single crystal surface is at a lower index.

As described above, in the hydrogen annealing, silicon dioxide is used as a material to be treated with respect to the surface (SOI layer), and the etching rate of silicon can be increased. In the present invention, even if the separation layer formed by ion implantation remains on the surface of the SOI layer after the separation step, these residues on the surface of the SOI layer can be effectively removed by hydrogen annealing.

Even at temperatures below 1200 c, smoothing cannot be achieved with nitrogen or other noble gas atmospheres, and with hydrogen-containing atmospheres, the rough surface can be satisfactorily smoothed. The temperature of the smoothing and etching operation according to the present invention is in the range of about 300 c to below the melting point of the material to be treated, preferably above 500 c, more preferably above 800 c, and particularly preferably above 1200 c, although the treatment temperature is also dependent on the composition, pressure, etc. of the treatment gas. Further, even when the heat treatment time is extended by slowly smoothing, a similar smooth surface can be obtained. The pressure of the process gas may be reduced to account for the effect of the composition of the opposing surface materials, making etching based on the interaction between the opposing surfaces more efficient even if the two surfaces are spaced the same distance apart. This is because as the pressure drops, the diffusion length of the gas molecules also increases.

As the temperature of the heat treatment increases, the oxygen and water contents of the atmosphere oxidize the silicon surface and prevent the surface from being smoothed. Therefore, the content thereof must be reduced. In high temperature thermal processing, oxygen and water can cause an undesirable reduction in the thickness of the silicon film due to oxidation and etching. Therefore, the content thereof must be reduced as well. The content should be controlled below-92 ℃ according to the dew point.

This phenomenon is obtained because the surface to be treated is subjected to a heat treatment in a clean environment. Therefore, when a natural oxide film is formed thickly on the surface, it should be removed by etching with dilute hydrofluoric acid or the like before the heat treatment. This speeds up the process of starting the surface smoothing.

The thus obtained smooth single crystal surface is suitable from the viewpoint of semiconductor device fabrication.

The boron out-diffused from the silicon layer upon heat treatment in a hydrogen-containing atmosphere does not differ significantly by the difference in the opposing surface materials. This is because, with a boron content of less than 1/100 for single crystal silicon relative to silicon, the amount of boron released from the gas phase during etching will be much less than the amount of silicon released and will not saturate.

Yonehara, one of the inventors of the present invention, has reported a manufacturing process of a bonded SOI substrate which is excellent in film thickness uniformity and crystallinity (T. Yonehara et al, Appl phys.Lett, Vol.64,2108 (1994); and U.S. patent No.5,371,037).

An example of such a process is illustrated in the schematic cross-sectional flow diagrams of fig. 29-31. First, a porous material layer (62) on a silicon substrate (61) is used as a material for selective etching. A non-porous crystalline silicon layer (63) is epitaxially grown onto the porous layer (62). Then, the resulting silicon substrate (61) and the 2 nd substrate (64) are bonded together through the silicon oxide layer (65) (fig. 29). Next, the 1 st substrate (61) is thinned by a method such as grinding from its back surface until poroussilicon is exposed throughout the surface of the bonded substrate structure (fig. 30).

Then, a selective etching solution, such as KOH or HF and H₂O₂The silicon layer (62) is etched away and exposed by the mixed solution (fig. 31). Thus, an SOI substrate is obtained. In addition, in this case, under the condition of controlling the jet flow, hydrogen annealing is required in order to make the surface of the SOI layer (63) more flat and smooth.

At this time, the etching selectivity of the etched porous silicon layer (62) with respect to bulk silicon (non-porous single crystal silicon layer) is set sufficiently high so as to be 100000 times. Therefore, an SOI substrate is formed in a state where a non-porous single crystal silicon layer 63 is grown in advance on a porous material, and after being peeled off on a 2 nd substrate 64, the thickness of the layer 63 is remarkably reduced.

Sakaguchi is also one of the members of the present invention, and he discloses the fact that the bonded substrate structure (fig. 29) can be separated with the porous material layer (62) as compared with other regions, because the porous material layer (62) shown in fig. 29 is low in mechanical strength, etc. (japanese patent application laid-open publication No. 7-302889).

[ example 1]

Embodiment 1 of the present invention will be explained with reference to figures 2-6,

referring to fig. 2, a 1 st single crystal silicon substrate (10) is first prepared. At least the principal plane of the 1 st substrate (10) is subjected to a heat treatment in a reducing atmosphere containing hydrogen, thereby forming a surface layer portion (low-defect layer) (12) on the surface of the substrate (10), in which region intrinsic bulk defects are larger than those of the substrateLess. Although the region (11) and the low-defect layer (12) are described as abrupt at a certain boundary, they are actually gradual. Then, SiO is formed on the surface layer of the resultant 1 st substrate₂(13) In order to separate the bonding surface from the active layer (i.e. the SOI layer as will be explained below).

Next, elemental ions of at least one rare gas, hydrogen, and nitrogen are implanted from one main surface of the 1 st substrate (10) with the insulating layer (13) to form a separation layer (ion implantation accumulation region) (14) (see fig. 3). The separation layer (14) is formed into the low-defect layer (12). Since the ion-implanted region (12) is within the low-defect layer (12), the position of the separation layer (14) can be accurately and uniformly determined.

Next, as shown in fig. 4, the obtained 1 st substrate (10) is bonded to the 2 nd substrate (15) at room temperature, and the separation layer (13) is located inside.

Although fig. 4 illustrates the 1 st substrate (10) and the 2 nd substrate (15) being bonded together through the insulating layer (13), the insulating layer (13) may be omitted entirely in the case where the 2 nd substrate is not silicon.

The next step, at the separation layer (14), separates or separates the bonded multilayer structure (fig. 5). The separation is achieved by heat treating the bonded substrate structure at a temperature of 400-600 ℃.

After the separation, a separation layer containing defects such as microvoids and stacking faults sometimes remains in the separation layer (14) on the 2 nd substrate (15), and thereafter, the residue is selectively removed.

The removal is carried out with the desired selectivity of the etching solution. When the remaining separation layer (14) is not large, it can be removed by hydrogen annealing. In other words, the ion-implanted accumulation layer (14) can also be removed by selective polishing, in which the SOI layer (16) is used as a polishing stop layer. Instead of selective polishing, removal can also be carried out by ordinary polishing.

In addition, in the case where the bonded substrate structure is separated at the interface between the SOI layer (16) and the separation layer (14), the step of removing the remaining separation layer (14) can be omitted.

Fig. 6 shows a semiconductor substrate made in accordance with the present invention. The No. 2 substrate (15) is covered with an SOI layer, such as a single crystal silicon thin film 16, which is flat and thin uniformly and is formed over a large area on the entire wafer. The semiconductor substrate thus obtained is also suitable from the viewpoint of producing an isolation element of an electronic device when the 1 st and 2 nd substrates are bonded together through an insulating layer (13).

After removing the residual ion implantation accumulation layer (14) (in the case where the surface of the 1 st substrate (11) is too rough to be used, the surface is also made flat), the 1 st single-crystal silicon substrate (11) can be used as a new single-crystal silicon 1 st substrate. Or reused as a new 2 nd substrate.

The ion-implanted accumulation layer (14) on the side of the substrate 1 can also be reused by only a surface smoothing process, such as a heat treatment process in a hydrogen-containing atmosphere, as described above.

[ example 2]

Embodiment 2 of the present invention is explained below with reference to fig. 7 to 11.

Referring to fig. 7, a single-crystal silicon 1 st substrate (21) is first prepared. From one main surface of the 1 st substrate (21), ions of at least one rare gas, hydrogen, and an element of nitrogen are implanted to form an implanted ion accumulation layer (separation layer) 24. In order to prevent the surface of the 1 st substrate (21) from being roughened by ion implantation, SiO is formed in advance₂The layer (23) serves as a surface layer. On forming SiO₂In the case of (2), the layer is removed. Then, at least one main surface of the 1 st substrate (21) is subjected to heat treatment in a reducing atmosphere containing hydrogen, thereby forming a layer (low-defect layer (22)) on the surface of the substrate 21 (see fig. 8) to reduce bulk defects. In the present embodiment, the hydrogen annealing needs to be performed at a low temperature of less than 500 ℃, or for a short time of several seconds to several tens of seconds. Here, an element structure such as a MOSFET can be formed well in the low-defect layer (22). Further, SiO formed in advance₂(25) As a surface layer of the low-defect layer (22), the bonding interface layer can be separated from the active layer in a more advantageous sense. As shown in FIG. 9, the surfaces of the 1 st substrate 21 and the 2 nd substrate 26 thus obtained were bonded together at room temperature.

In the case where the bonding strength of the two substrates is insufficient, the bonded substrate structure is subjected to heat treatment at a temperature of about 400 ℃ or is pressurized.

The bonded substrate structures are then separated or separated at a separation layer (24) (fig. 10). The separation may be performed by spraying a liquid, such as water, or a gas, such as nitrogen, onto the side of the bonded substrate structure. Of course, the separation method is not limited to the above method, and may be split or applied with a wedge.

Since defects such as microholes or dislocations are sometimes contained in the separation layer (24) remaining on the 2 nd substrate (26), the remaining separation layer (24) is selectively removed.

Can be selectively polished by using an etching solution or using the SOI layer (22) as a polishing stopperThe remaining separation layer (24) is removed. When the remaining separation layer (24) is thin or minute, it can be selectively removed by hydrogen annealing. In this case, in order to increase the etching rate by hydrogen annealing, a layer of SiO is attached to the surface layer thereof₂The substrate (2) is required to be opposed to the residual separation layer (24) as a counter material.

The etching solution removal method, the removal method based on polishing, and the removal method based on hydrogen annealing may be appropriately combined to remove the residual separation layer.

Fig. 11 shows a semiconductor substrate made in accordance with the present invention. The No. 2 substrate (26) is covered with a single crystal silicon thin film (22) which is formed in a large area over the entire wafer and is planarized to be uniformly thinned.

In this embodiment, the low-defect layer (22) is formed after the separation layer (24). Therefore, an SOI layer (22) can be obtained, and defects due to ion implantation for forming the separation layer (24) are eliminated.

Incidentally, in the case of separating the bonded substrate structure at the separation layer (24) at the interface between the separation layer (24) and the SOI layer (22), the step of removing the remaining separation layer can be omitted, or the surface of the SOI layer (22) can be subjected to a slight etching treatment by hydrogen annealing.

After the residual separation layer (24) is removed (and after the surface of the 1 st substrate (21) is planarized to an unallowable length), the 1 st silicon single crystal substrate 21 is reused as a new 1 st single crystal silicon substrate (21) or a next 2 nd substrate (26). Of course, when the separation is performed at the interface between the separation layer (24) and at the separation layer (24), the step of removing the remaining separation layer (24) can be omitted.

As described above, the separation layer (24) on the side surface of the 1 st substrate can also be reused only by the surface flattening process, for example, by heat treatment in an atmosphere containing hydrogen.

In a heat treatment in an atmosphere containing hydrogen, when the surface of a residual separation layer (24) on a 2 nd substrate (26) provided with an SOI layer (22) is kept opposite to silicon oxide, the silicon oxide opposed to the separation layer and the component silicon in the separation layer are reacted by the atmosphere as follows:

thus, the remaining separation layer (24) can be effectively removed, and Si migration continues to progress in order to reduce the surface energy of the SOI layer (22), resulting in smoothing of the surface of the layer (22).

[ example 3]

Embodiment 3 of the present invention will be explained with reference to fig. 12 to 14.

As shown in fig. 12, by using two 2 nd substrates. On both surfaces of the 1 st substrate, the steps explained in the above-described

embodiment

1 or 2 are performed. This is to enable two semiconductor substrates (SOI substrates) to be manufactured simultaneously.

In fig. 12, reference numeral 31 denotes a 1 st substrate, and

reference numerals

32 and 35 denote ion-implanted layers (separation)Layer),

reference numerals

33 and 36 denote low-defect layers, and

reference numerals

34 and 37 denote SiO₂Layers, and

reference numerals

38 and 39 denote the 2 nd substrate. Fig. 12 is a sectional view showing a state where both surfaces of the 1 st substrate (31) are bonded to the 1 st substrate (31) obtained after the steps described in example 1 are performed, respectively, by the 2

nd substrates

38 and 39. FIG. 13 shows a state where the bonded multilayer structure is separated or separated at the separation layers 32 and 35 (similar to the separation method in example 1), and FIG. 14 shows a state where the separation layers 32 and 35 have been separatedA removed state. Of course, when separation of the bonded structure occurs at the interfaces between the separation layer 32 and the low-defect layer 33, and between the separation layer 35 and the low-defect layer 36, the step of removing the residual separation layer can be omitted.

After removing the residual ion-implanted accumulation layers (32, 35) (and performing surface planarization in the case where the surface of the 1 st substrate (31) is too rough to allow), the 1 st single-crystal silicon substrate (31) is reused as a new 1 st single-crystal silicon substrate (31) or a next 2 nd substrate (38).

The ion-implanted accumulation layers (32) and (35) on the 1 st substrate side can also be reused after being planarized by a surface planarization process, such as a heat treatment process in a hydrogen-containing atmosphere as described above.

The support substrates (38) and (39) do not have to be identical. Furthermore, the insulating layers (34) and (37) may also be omitted entirely.

Now, an example of the present invention will be described in detail with reference to the drawings.

(example 1)

21 st silicon single crystal substrates (8 inches in diameter) manufactured by the CZ method were prepared. Each of the 1 st substrates was hydrogen annealed to improve the surface quality thereof, in other words, to form a low-defect layer in their surface. The hydrogen annealing was performed under a hydrogen atmosphere at a temperature of 1200 ℃ for 1 hour.

One of the above CZ silicon wafers was washed with SC-1 (a solution containing 1 wt.% NH)₄OH，6wt.％H₂O₂Mixed liquid with water), the number of COPs contained on the wafer surface after cleaning is detected by a foreign matter detection device. The COP number is about 8 per wafer. That is, the density of COP is about 0.02/cm². Here, particles having a size greater than about 0.1 μm are detected as COP.

Incidentally, the COP number X per wafer will be hereinafter referred to as "X/W".

Forming the surface of the 1 st substrate (another CZ silicon wafer) with SiO of 200nm by thermal oxidation₂And (3) a layer. Further, SiO passes through the surface₂Layer at an acceleration energy of 40KeV and a dose of 5X 10¹⁶cm^-2Hydrogen ions are implanted into the 1 st substrate. The projection range of the ion implantation is adjusted so as to be in the low defect layer. Thus, the 1 st substrate becomes a single crystal silicon layer (an SOI layer or a low defect layer) on the separation layer.

Subjecting the obtained SiO₂The upper 1 st substrate surface is placed on and in contact with the surfaces of the Si substrates (2 nd substrate) prepared separately. When the contacted substrate structure is subjected to a thermal treatment at 600 c, it is separated or divided into two parts in the vicinity of the projected range of ion implantation. Since the ion-implanted layer (separation layer) is porousAnd is therefore rough and uneven in the surface of the separated portions. The separation layer remaining on the obtained 2 nd substrate was removed by selectively etching the surface of the side surface of the 2 nd substrate while stirring a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water. The ion-implanted layer is selectively etched and completely removed without etching the single-crystal silicon on the SOI layer, and the single-crystal silicon is used as an etching stopper.

The etching rate of non-porous single crystal silicon with the above etching solution is very low, and in practical application, the etching amount of single crystal silicon (in the order of tens of angstroms), which corresponds to the thickness reduction, is negligible.

In addition to the selective etching method, a non-selective etching method or a polishing method such as a contact polishing method and CMP may be used for removing the ion-implanted layer. This is the same as the other examples. In the case of the polishing method, heat treatment with hydrogen is not required to planarize the surface of the SOI substrate. However, in the case where polishing damage is left, it is more advantageous to perform heat treatment or remove the surface layer of the SOI substrate.

Specifically, a single crystal silicon layer having a thickness of about 0.2 μm may be formed on the silicon dioxide film. The thickness of the formed single-crystal silicon layer was measured at any 100 points over the surface of the SOI substrate. The uniformity of the layer thickness was 201nm +6 nm. Therefore, the resulting SOI substrate is excellent in the uniformity of the thickness of the SOI layer. The number of COP defects contained in the surface of the SOI layer was 65/W. Since the COP number of the surface of the conventional CZ wafer is about 400/W, it is shown that the SOI layer obtained according to the present invention has much fewer defects.

Further, the SOI substrate was heat-treated in hydrogen gas at a temperature of 1100 ℃ for 1 hour. When the roughness of the resulting SOI substrate was estimated by an interatomic force microscope, the root mean square (R) in the 50 μm square region thereof_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer. The number of COP contained in the surface of the SOI layer was 8/W.

Incidentally, when the SOI layer after the separation step is subjected to hydrogen annealing, the number of COPs in the outermost layer of the SOI layer is further reduced, and the defect distribution in the SOI layer can be uniformized. This effect will be specifically described below with reference to fig. 23.

Fig. 23 shows the number of COPs per single wafer as a function of depth from the wafer surface. As for each CZ silicon wafer (diameter: 8 inches), it is a wafer obtained by subjecting a CZ silicon wafer to hydrogen annealing ("NIKKEIMICRODEVICE", Feb, issue (1998), p.31). In the case of the CZ silicon wafer subjected to hydrogen annealing, the number of COPs in the vicinity of the wafer surface was the smallest, but the number of COPs increased as the depth thereof increased, as shown by the graph, although the case varied depending on the conditions of hydrogen annealing.

By way of example, an SOI substrate is formed by setting an ion projection area (separation layer) to about 400nm from the surface of a CZ silicon wafer which has been subjected to hydrogen annealing; bonding the resulting wafer to a 2 nd substrate; and subsequently separating the bonded structure at the separation layer. At this time, the number of COPs at the outermost surface of the SOI layer is largest, and the closer to the interface between the SOI layer and the insulating layer, the smaller its amount. Therefore, the number of COPs near the surface of the SOI layer needs to be further reduced, and it is more advantageous to perform hydrogen annealing after the separation step. At this time, defects on both surfaces of the SOI layer are reduced by hydrogen annealing.

Incidentally, in order to facilitate detection of COP contained on the surface of the SOI layer, SC-1 solution (consisting of 1.0 wt.% NH) was used₄OH, 6.0 wt.% H₂O₂And water) was processed for ten minutes. In addition, the detection device is a surface particle detector (e.g., by KLA Tencor)Inc. Manufactured "SP-1").

Even when the separated SOI substrate is left intact, the heat treatment is performed in hydrogen without removing the residual ion-implanted layer, simultaneously causing elimination of pores and defects due to migration of silicon, and flattening the surface of the SOI layer, with the result that the ion-implanted layer is eliminated.

The cross section of the silicon layer was observed with a transmission electron microscope. The results demonstrate that the silicon layer maintains good crystallinity without introducing new crystal defects into the silicon layer.

Also, the mixed solution including 49% concentration hydrofluoric acid, 30% concentration hydrogen peroxide and water was stirred, and the ion-implanted layer remaining on the 1 st substrate side was selectively etched away. Thereafter, the 1 st substrate is subjected to a surface treatment such as hydrogen annealing or polishing. The resulting 1 st substrate will be available again as a new 1 st substrate or a new 2 nd substrate.

Even when the separated 1 st substrate is left intact and heat treatment is performed in hydrogen gas, the residual ion-implanted layer is not removed, but the elimination of micropores and defects at the surface of the substrate and the planarization are simultaneously caused due to the migration of silicon, with the result that the ion-implanted layer is eliminated.

Incidentally, the ion implantation regionalso exhibits an absorption action. Even if metal impurities are present, the two bonded substrates can be separated after the impurities are absorbed by the ion implantation region, and therefore the SOI substrate according to the present invention is still effective in the case of contamination with impurities.

(example 2)

Two 1 st silicon single crystal substrates (8 inches in diameter) manufactured by the CZ method were prepared. Each of the 1 st substrates was heat-treated under the conditions described below to improve the quality of the surface layer thereof. One of the two 1 st substrates was used for analysis.

The heat treatment (hydrogen annealing) is carried out in H₂The atmosphere was carried out at a temperature of 1200 c for 2 hours, thereby forming a low-defect layer on the surface of each 1 st substrate. The number of COP contained in the surface layer of the No. 1 substrate for analysis was measured by a foreign matter measuring instrument, and the number of COP was about 5/W.

Then, at an acceleration voltage of 50KeV, the dose was 6X 10¹⁶/cm²Under the conditions of (1), H⁺Ions are implanted into the 1 st substrate. The projected range of the ion implantation is located in the vicinity of about 600nm from the 1 st substrate surface.

Prepared separately, the surface of the resultant 1 st substrate was set to have a layer of SiO 500nm thick₂Silicon lining of a layerOn the bottom surface and in contact therewith, the contacted substrate structure, when annealed at 550 c, is divided into two parts in the vicinity of the projected range of ion implantation. Since the ion-implanted layer is porous, the surface of the separated portion is rough. While stirring a mixed solution composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the surfaceon the 2 nd substrate side was selectively etched. This process can completely remove the ion-implanted layer without damaging the single-crystal silicon of the SOI layer, and selectively etches and completely removes the ion-implanted layer using the single-crystal silicon as an etching stopper, while leaving the single-crystal silicon of the SOI layer unetched.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, it is not necessary to planarize the surface of the SOI substrate with hydrogen annealing. However, when polishing damage remains, it is preferable to perform heat treatment or remove the surface of the SOI substrate.

The etching rate of the non-porous single crystal silicon by the etching solution is very small, and in practical application, the etching amount of the single crystal silicon is negligible to reduce the thickness (in the order of tens of angstroms).

Thereafter, only the end faces of the non-porous single crystal silicon are polished to be flat.

Specifically, a single crystal silicon layer (SOI layer) having a thickness of 0.5 μm can be formed on the silicon oxide film. The thickness of the formed single-crystal silicon layer was measured at arbitrary 100 points over the entire surface of the SOI substrate. The uniformity of the layer thickness was 498 nm. + -.15 nm. The SOI layer surface contains COP in an amount of the order of 50/W. Therefore, the COP amount of the SOI layer outer surface was 50/W. Further, in the SOI layer on the side of the silicon oxide film, the number of COPs was 5/W. It is known that the density of COP gradually decreases from the outer surface of the SOI layer inward. Since the typical CZ wafer surface contains COP in an amount of about 400/W, it can be seen that defects are greatly reduced in the SOI layer according to the present invention.

When using an atomic force microscope, the roughness of the surface of the resulting SOI substrate was estimated as the root mean square (R) of the 50um square region_rsm) Approximately 0.2nm, which is equivalent to that of commercially available silicon wafers.

As a result of observation of a cross section of the silicon layer with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer and the silicon layer maintained good crystallinity

Incidentally, by further performing hydrogen annealing on the SOI substrate produced in this example, the number of COPs contained in the surface of the SOI layer can be further reduced to be close to the number (5/W) of COPs in the SOI layer in the vicinity of the silicon oxide layer.

Therefore, both surfaces of the single crystal silicon layer, i.e., the SOI layer on the silicon oxide layer, are subjected to hydrogen annealing, thereby reducing defects such as COP inherent in the bulk wafer as well as reducing the amount of COP of the SOI layer. Even if defects remain, they can be distributed, with substantial homogenization, within the SOI layer.

And, while stirring a mixed liquid composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the ion-implanted layer remaining on the 1 st substrate side was selectively etched. Thereafter, the 1 st substrate is subjected to a surface treatment such as a hydrogen annealing method or a polishing method. The resulting 1 st substrate can be used again as a new 1 st substrate or a new 2 nd substrate.

Even when the separated 1 st substrate is left intact and heat treatment is performed in hydrogen gas, the residual ion-implanted layer is not removed, but the removal of micropores and defects of the substrate surface and planarization are simultaneously caused due to the migration of silicon, with the result that the ion-implanted layer is eliminated.

(example 3)

A 1 st silicon single crystal substrate (8 inches in diameter) manufactured by the CZ method was prepared. And (3) carrying out thermal annealing on the 1 st substrate to improve the quality of the surface layer of the substrate. For the heat treatment, in H₂Gas atmosphere at 1200 deg.CHydrogen annealing was performed for 4 hours.

Next, by thermal oxidation, the surface of the substrate was formed to have SiO with a thickness of 200nm₂And (3) a layer. In addition, at an acceleration voltage of 40KeV, the dose was 5X 10¹⁶/cm²By SiO on its surface₂Layer of (a) H⁺Ions are implanted into the 1 st substrate.

The surface of the resultant 1 st substrate was placed on and brought into contact with the surface of a silicon substrate (2 nd substrate) formed with a layer of SiO 500nm thick at room temperature₂Layers, respectively, are prepared. The bonded substrate structure is then annealed at 300 c to enhance the bonding force of the 1 st and 2 nd substrates. Thereafter, the mixture was pressurized at high pressure (200kg. f/cm)²) Water is sprayed onto the peripheral end face of the bonded structure to separate or divide the bonded substrate structure in the vicinity of the ion-implanted layer (ion-implanted layer formed by the above-described ion implantation). Here, the bonded substrate structure is separated into two parts in the vicinity of the projected range of ion implantation. While stirring a mixed solution composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the surface on the 2 nd substrate side was selectively etched to remove the remaining portion of the separation layer. The single crystal silicon of the formed SOI layer is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion implanted layer. In the case of the polishing method, it is not necessary to planarize the surface of the SOI substrate with hydrogen annealing. However, when polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

In addition to selective etching, non-selective etching and polishing can be used to remove the ion-implanted layer, and if polishing is used, hydrogen annealing is not required to planarize the surface of the SOI substrate. However, if the polishing damage remains, it is preferable to perform a hydrogen heat treatment or remove the surface layer of the SOI substrate.

The etching rate of the etching solution to the non-porous monocrystalline silicon is very low, and in practical application, the etching amount (in the order of tens of angstroms) of the monocrystalline silicon is negligible to the thickness reduction.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on the silicon oxide film. The thickness of the single-crystal silicon layer formed was measured at 100 points over the surface of the SOI substrate. Thus, the thickness uniformity was 201 nm. + -.6 nm.

Subsequently, the SOI substrate was heat-treated at 1100 ℃ for 1 hour in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, which is equivalent to that of commercially available silicon wafers. Cleaning SiO with SC-1 cleaning solution₂After the surface of the single crystal silicon layer was formed, the number of COP on the cleaned surface was measured by a foreign matter detecting apparatus, and the number of COP was 3/W.

Incidentally, even when the separated SOI substrate is left intact and the heat treatment is performed in hydrogen, the residual ion-implanted layer is not removed, but the removal of the micro-pores and defects is caused simultaneously due to the migration of silicon and the surface of the SOI layer is planarized, with the result that the ion-implanted layer is eliminated.

As a result of observing the cross section of the silicon layer with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer and good crystallinity was maintained in the silicon layer.

Even when the separated 1 st substrate remains intact, the heat treatment in hydrogen gas does not remove the remaining ion-implanted layer, simultaneously causes elimination of micro-pores and defects of the substrate surface due to migration of silicon, and the planarization results in elimination of the ion-implanted layer.

Although the bonded structures are separated in this example by jets of water, it is also possible to use another method, by high pressure jets of gas, for example nitrogen.

(example 4)

A 1 st silicon single crystal substrate (8 inches in diameter) manufactured by the CZ method was prepared. And (3) carrying out thermal annealing on the 1 st substrate to improve the quality of the surface layer of the substrate. For the heat treatment, in H₂The hydrogen annealing was carried out in a gas atmosphere at a temperature of 1100 ℃ for 4 hours.

Then, the surface of the substrate was formed to have a thickness of 200nm of SiO by thermal oxidation₂And (3) a layer. In addition, at an acceleration voltage of 40KeV, the dose was 5X 10¹⁶/cm²By SiO on its surface₂Layer of (a) H⁺Ions are implanted into the substrate.

SiO to separately prepared 1 st substrate₂The surface of the layer and the surface of the fused quartz substrate (No. 2 substrate) were treated with plasma and washed with water. Then, the 1 st and 2 nd substrates are placed on the upper side so as to be in contact with each other. When the contacted substrate structure is annealed at 600 ℃, the substrate structure is separated into two parts near the projected range of ion implantation. Since the ion-implanted layer is porous, the separation partThe divided surface is rough. Then, while stirring a mixed liquid composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the 2 nd substrate side was selectively etched. The single crystal silicon of the formed SOI layer is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon serving as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, the surface of the SOI substrate does not need to be planarized by heat treatment in hydrogen gas. However, when polishing damage remains, it is preferable to perform heat treatment or removethe surface layer of the SOI substrate.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of polishing, the surface of the resulting SOI substrate is planarized without heat treatment in hydrogen. However, in the case where polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

The etching rate of the non-porous monocrystalline silicon by using the etching solution is very low, and in practical application, the etching amount (in the order of tens of angstroms) of the monocrystalline silicon is negligible corresponding to the thickness reduction.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on a transparent quartz substrate. The thickness of the single-crystal silicon layer formed was measured at arbitrary 100 points over the surface of the SOI substrate. Furthermore, the uniformity of the layer thickness was 201 nm. + -.6 nm. When the COP number contained in the surface of the silicon single crystal was measured, the COP number was about 80/W.

Subsequently, the SOI substrate was heat-treated at 1100 ℃ for 1 hour in hydrogen. When the surface roughness of the resulting SOI substrate was evaluated by an interatomic force microscope, it was 50um²Root mean square (R) within a region_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer.

Even if the separated SOI substrate is left intact, the residual ion-implanted layer is not removed when the heat treatment is performed in hydrogen, and the removal of the micro-pores and defects is caused simultaneously due to the migration of silicon, and the surface of the SOI layer is planarized, with the result that the ion-implanted layer is eliminated.

And, while stirring a mixed liquid composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the ion-implanted layer remaining on the side of the 1 st substrate was selectively etched. Thereafter, the 1 st substrate is subjected to a surface treatment such as a hydrogen annealing method or a polishing method. The resulting 1 st substrate can be used again as a new 1 st substrate or a new 2 nd substrate.

Even when the separated 1 st substrate is left intact and heat treatment is performed in hydrogen, the remaining ion-implanted layer is not removed, but simultaneously removal and planarization of micro-pores and defects on the surface of the SOI layer are caused due to migration of silicon, with the result that the ion-implanted layer is eliminated.

Although the bonded structures are separated in this example by jets of water, it is also possible to alternatively inject a gas, such as nitrogen, at high pressure.

(example 5)

A 1 st silicon single crystal substrate (8 inches in diameter) manufactured by the CZ method was prepared. And carrying out thermal annealing on each 1 st substrate to improve the quality of the surface layer of the substrate. More specifically, in the context of H₂And carrying out hydrogen annealing at 1100 ℃ for 4 hours in a mixed atmosphere of 4% of gas and 96% of Ar gas. This forms a low-defect layer in the 1 st substrate surface.

When the number of COP contained in the surface layer of one of the two 1 st substrates was examined, the number of COP was 30/W.

Next, another 1 st substrate surface having SiO with a thickness of 20Onm was formed by thermal oxidation₂And (3) a layer. In addition, at an acceleration voltage of 60KeV, the dose was 5X 10¹⁶/cm²By passing SiO through the surface₂Layer of (a) H⁺Ions are implanted into the substrate.

SiO to separately prepared 1 st substrate₂The layer surface and the surface of the sapphire substrate (2 nd substrate) were treated with plasma and washed with water. Then, the 1 st and 2 nd substrates are placed on the upper side so as to be in contact with each other. When the contacted substrate structure is annealed at 600 c, it is separated or split into two portions near the projected range of ion implantation. Since the ion-implanted layer is porous, the surface of the separated portion is rough. Then, while a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water was stirred, the 2 nd substrate side was selectively etched. The single crystal silicon of the formed SOI layer is left without etching, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, the surface of the SOI substrate does not need to be planarized by heat treatment in hydrogen gas. However, when polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

The etching rate of the non-porous monocrystalline silicon by using the etching solution is very low, and in practical application, the etching amount (in the order of tens of angstroms) of the monocrystalline silicon is negligible relative to the thickness reduction.

Then, only the end face of the non-porous single crystal silicon is planarized by polishing.

Specifically, a single crystal silicon layer having a thickness of 0.4 μm may be formed on a transparent sapphire substrate. The thickness of the formed single-crystal silicon layer was measured at 100 points over the surface of the SOI substrate. Furthermore, the uniformity of the layer thickness was 402 nm. + -. 12 nm. When the COP number contained in the surface of the silicon single crystal is measured, the COP number is about 120/W.

Next, when the surface roughness of the obtained SOI substrate was evaluated by an atomic force microscope, it was 50 μmRoot mean square (R) in square region_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer.

While stirring a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the ion-implanted layer remaining on the side surface of the 1 st substrate was selectively etched. Thereafter, the 1 st substrate is subjected to a surface treatment such as a hydrogen annealing method or a polishing method. The resulting 1 st substrate can be used again as a new 1 st substrate or a new 2 nd substrate.

Even if the separated 1 st substrate is left intact and the remaining ion-implanted layer is not removed when the heat treatment is performed in hydrogen, the ion-implanted layer is eliminated as a result of removal and planarization of micropores and defects of the substrate surface caused by migration of silicon.

(example 6)

A1 st single crystal silicon substrate manufactured by a CZ method is prepared and each 1 st substrate is subjected to thermal annealing to improve the quality of the surface layer thereof. More precisely, in H₂Hydrogen annealing in gas at 1150 deg.C for 10 min as heat treatment

Next, the surface of each 1 st substrate having SiO with a thickness of 200nm was formed by thermal oxidation₂And (3) a layer. In addition, at an acceleration voltage of 70KeV, the dose was 5X 10¹⁶/cm²By passing SiO through the surface₂Layer of (a) H⁺Ions are implanted into the substrate.

SiO to separately prepared 1 st substrate₂The surface of the layer and the surface of the glass substrate (No. 2 substrate) were treated with plasma and washed with water. Then, the 1 st and 2 nd substrates are placed on the upper side so as to be in contact with each other. When the contacted substrate structure is annealed at 600 c, it is separated or split into two portions near the projected range of ion implantation. Since the ion-implanted layer is porous, the surface of the separated portion is rough. Then, while a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water was stirred, the 2 nd substrate side surface was selectively etched. The single crystal silicon of the formed SOI layer is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

Specifically, a single crystal silicon layer having a thickness of 0.5 μm may be formed on a transparent glass substrate. The thickness of the formed single-crystal silicon layer was measured at 100 points over the surface of the entire SOI substrate. Furthermore, the uniformity of the layer thickness was 501 nm. + -.15 nm. When the COP number contained in the surface of the silicon single crystal is measured, the COP number is about 100/W. Since the number of COP contained on the surface of the conventional CZ wafer is about 400/W, it can be seen that the SOI layer according to the present invention has very few defects.

(example 7)

A 1 st silicon single crystal substrate (8 inches in diameter) manufactured by the CZ method was prepared. After forming a surface of a substrate by thermal oxidation to have a silicon dioxide layer of 200nm, the surface was exposed to an acceleration voltage of 80KeV and a dose of 5X 10¹⁶/cm²By passing SiO through the surface₂Layer of (a) H⁺Ions are implanted into the substrate. Then, the 200nm silicon dioxide film was etched and removed with an HF solution. Subsequently, the resultant 1 st substrate is heat-treated. To improve the quality of its surface layer. For heat treatment, the hydrogen anneal is in H₂O atmosphere at 1200 deg.C for 1 hr. In this case, the COP number contained in the substrate surface was 8/W.

Forming 200nm of oxygen on the 1 st substrate again by thermal oxidationThin film (SiO)₂). Next, SiO of the 1 st substrate₂The layer surface and the surface of the silicon substrate (2 nd substrate) are placed to the upper side so as to be in contact with each other. When the contacted substrate structure is annealed at 600 c, it is separated or split into two portions near the projected range of ion implantation. Since the ion-implanted layer is porous, the surface of the separated portion is rough. Then, while stirring a mixed liquid of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the surface on the 2 nd substrate side was selectively etched. The single crystal silicon of the formed SOI layer is left without etching, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, the surface of the resulting SOI substrate is planarized without heat treatment in hydrogen. However, in the case where polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on a silicon oxide film. The thickness of the formed single-crystal silicon layer was measured at 100 points on the surface of the entire SOI substrate. Furthermore, the uniformity of the layer thickness was 201 nm. + -.6 nm.

Next, the SOI substrate was subjected to heat treatment at 1100 ℃ for 1 hour in hydrogen. When the roughness of the resulting SOI substrate is estimated by an interatomic force microscope, the root mean square (R) in the 50um square region thereof_rms) Approximately 0.2nm, and this value is equal to that of a commercially available ordinary silicon wafer. When the COP number contained in the surface of the single crystal silicon layer was measured, the COP number was about 8/W.

Even if theseparated SOI substrate is left intact and the remaining ion-implanted layer is not removed when the heat treatment is performed in hydrogen, the ion-implanted layer is eliminated as a result of removal and planarization of pores and defects on the surface of the SOI layer due to migration of silicon.

(example 8)

A1 st silicon single crystal substrate manufactured by a CZ method is prepared. And (3) carrying out thermal annealing on the 1 st substrate to improve the quality of the surface layer of the substrate. For the heat treatment, in H₂Hydrogen annealing was performed at 1200 ℃ for 3 hours in a gas atmosphere.

Then, the surface of the substrate was formed to have a thickness of 200nm of SiO by thermal oxidation₂And (3) a layer. In addition, at an acceleration voltage of 40KeV, the dose was 5X 10¹⁶/cm²By passing SiO through the surface₂Layer of (a) H⁺Ions are implanted into the substrate.

SiO of the 1 st substrate to be prepared separately₂The layer surface and the surface of the silicon substrate (2 nd substrate) are placed to the upper side so as to be in contact with each other.

Removing the oxide film on the back surface of the 1 st substrate, and adding CO₂Laser beam of laser, from substrate structureSubstrate 1 side, the entire surface of the crystalline sheet (bonded substrate structure) is irradiated. At the bonding interface of the substrate structure, the CO₂The laser beam of the laser is 200nm SiO₂Absorbed by the layer, thereby rapidly raising the SiO₂The temperature near the layer. As a result, the substrate structure is separated or divided into two parts in the vicinity of the projected range of ion implantation due to the strong thermal stress action in the ion-implanted layer (separation layer formed by ion implantation).

Since the ion-implanted layer is porous, the surface of the separated portion is rough. Thus, while a mixed liquid composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water was stirred, the surface on the 2 nd substrate side was selectively etched. The single crystal silicon of the formed SOI layer is left without etching, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of polishing, there is no need to perform annealing in hydrogen gas to planarize the surface on which the SOI substrate is formed. However, in the case where polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on the silicon dioxide film. The thickness of the formed single-crystal silicon layer was measured at 100 points over the surface of the SOI substrate. Furthermore, the uniformity of the layer thickness was 201 nm. + -.6 nm.

Next, the SOI substrate was subjected to heat treatment at 1100 ℃ for 1 hour in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, and this value is equal to that of a commercially available ordinary silicon wafer. When the COP number of the surface of the single crystal silicon layer is measured, the COP number is about 3/W.

Even if the separated SOI substrate is left intact and the remaining ion-implanted layer is not removed when the heat treatment is performed in hydrogen, the ion-implanted layer is eliminated as a result of removal and planarization of pores and defects on the surface of the SOI layer due to migration of silicon.

Even if the separated 1 st substrate is left intact and the remaining ion-implanted layer is not removed when the heat treatment is performed in hydrogen, the removal and planarization of the micro-pores and defects of the substrate surface are simultaneously caused due to the migration of silicon, and as a result, the ion-implanted layer is also eliminated.

(example 9)

A 1 st single crystal silicon substrate (8 inches in diameter) produced by the CZ method was prepared and subjected to thermal annealing to improve the surface layer quality thereof. For the heat treatment, in H₂Hydrogen annealing was performed at a temperature of 1200 c for 1 hour in a gas atmosphere, thereby forming a low-defect layer.

SiO of the 1 st substrate to be prepared separately₂The layer surface and the surface of the silicon substrate (2 nd substrate) are placed to the upper side so as to be in contact with each other. When SiO is present₂The layer and the single crystal silicon layer, when etched at the end faces of the bonded wafers (substrate structures), exhibit the end faces of the ion-implanted layer (formed by ion implantation).

When in 1When the resulting bonded wafer was subjected to high-temperature oxidation at 000 ℃, the two substrates were completely separated or separated in the ion-implanted layer within 10 hours. When the peeled substrate surface was observed, the ion-implanted layer of the peripheral portion of the wafer had been converted into SiO₂But is virtually unchanged in the central portion of the wafer.

Then, while stirring a mixed solution composed of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the residual ion-implanted layer on the 2 nd substrate side was selectively etched. The single crystal silicon of the formed SOI layer is left without etching, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, it is not necessary to perform heat treatment in hydrogen gas to planarize the surface of the SOI substrate. However, in the case where polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

The etching rate of the non-porous monocrystalline silicon by the etching solution is low, and the selectivity ratio of the etching rate of the non-porous monocrystalline silicon to the etching rate of the ion implantation layer reaches 10⁵The above. In practical applications, the amount of etching of the non-porous layer (on the order of tens of angstroms) is negligible in relation to the reduction in thickness.

Next, the SOI substrate was subjected to heat treatment at 1100 ℃ for 2 hours in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, and this value is equal to that of a commercially available ordinary silicon wafer. When the COP number contained in the surface of the single crystal silicon layer was measured, the COP number was about 8/W.

Even if the separated SOI substrate is left intact and the remaining ion-implanted layer is not removed when the heat treatment is performed in hydrogen, the ion-implanted layer is eliminated as a result of the removal and planarization of the pores and defects on the surface of the SOI layer due to the migration of silicon.

Even if the separated 1 st substrate is left intact and the remaining ion-implanted layer is not removed when the heat treatment is performed in hydrogen, the ion-implanted layer is eliminated as a result of the removal and planarization of the micro-pores and defects of the substrate surface caused by the migration of silicon.

(example 10)

A1 st single crystal silicon substrate (8 inches in diameter) produced by the CZ method was prepared, and the 1 st substrate was subjected to thermal annealing to improve the surface layer quality. For the heat treatment, in H₂The hydrogen annealing was performed in a gas atmosphere at a temperature of 1200 ℃ for 1 hour.

SiO to separately prepared 1 st substrate₂The surface of the layer and the surface of the silicon substrate (2 nd substrate) were treated with plasma and washed with water. Then, the 1 st and 2 nd substrates are placed on the upper side so as to be in contact with each other. The resulting substrate structure was heat-treated at 300 c for 1 hour to improve the bonding strength between the 1 st and 2 nd substrates. When the wedge wedges the bonded substrate structure from its periphery, the structure is separated into two parts near the projected range of ion implantation. Since the ion-implanted layer (formed by ion implantation) is porous, the surface of the separated portion is rough. Thus, 49% hydrofluoric acid, 30% hydrogen peroxide and water were mixed under stirringIn the case of the mixed solution, the 2 nd substrate side surface is selectively etched. The single crystal silicon of the formed SOI layer is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon serving as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, it is not necessary to perform heat treatment in hydrogen gas to planarize the surface of the resulting SOI substrate. However, in the case where polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on the silicon dioxide film. The thickness of the single-crystal silicon layer formed was measured at 100 points over the surface of the SOI substrate. Furthermore, the uniformity of the layer thickness was 201 nm. + -.6 nm.

Subsequently, the SOI substrate was heat-treated at 1100 ℃ for 2 hours in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer. When the COP number contained in the surface of the single-crystal silicon layer was measured, the COP number was about 8/W. For COP detection, after the surface of the silicon layer was washed with SC-1 washing liquid, COP having a particle size of more than 0.1 μm was detected with a foreign matter detecting device.

As a result of observing the cross section of the silicon layer with a transmission electron microscope, it was confirmed that no new crystal defects were introduced intothe silicon layer and good crystallinity was maintained in the silicon layer.

While stirring a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the ion implantation remained on the side surface of the 1 st substrate was selectively etched. Thereafter, the 1 st substrate is subjected to a surface treatment such as a hydrogen annealing method or a surface polishing method. The resulting 1 st substrate can be used again as a new 1 st substrate or a new 2 nd substrate.

Even when the separated 1 st substrate is left intact and heat treatment is performed in hydrogen gas, the remaining ion-implanted layer is not removed, but simultaneously removal and planarization of micropores and defects of the substrate surface are caused due to migration of silicon, with the result that the ion-implanted layer is eliminated.

(example 11)

A1 st silicon single crystal substrate (8 inches in diameter) produced by the CZ method was prepared, and the 1 st substrate was subjected to thermal annealing to improve the surface layer quality. For the heat treatment, in H₂The hydrogen annealing was performed in a gas atmosphere at a temperature of 1200 ℃ for 2 hours.

SiO to separately prepared 1 st substrate₂The surface of the layer and the surface of the silicon substrate (2 nd substrate) were treated with plasma and washed with water. Then, the 1 st and 2 nd substrates were placed on the upper side to be brought into contact with each other, and the resultant substrate structure was subjected to a heat treatment at 300 ℃ for 1 hour, thereby improving the bonding strength between the 1 st and 2 nd substrates. Ion implantation of a bonded substrate structure when a shear force is applied to the structureSplit or divided into two parts near the projection range. Since the ion-implanted layer (formed by ion implantation) is porous, the surface of the separated portion is rough. Thus, while stirring a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the 2 nd substrate side surface was selectively etched. Of the formed SOI layerThe single crystal silicon is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on the silicon dioxide film. The thickness of the single-crystal silicon layer formed was measured at 100 points over the surface of the SOI substrate. Furthermore, the uniformity of the layer thickness was 201 nm. + -.6 nm. When the COP number contained in the surface of the single-crystal silicon layer was measured, the COP number was about 50/W.

Subsequently, the SOI substrate was heat-treated at 1100 ℃ for 2 hours in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer. When the COP number contained in the surface of the silicon single crystal layer was measured after the heat treatment for 2 hours, the COP number was about 6/W.

While stirring a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the ion-implanted layer remaining on the side surface of the 1 st substrate was selectively etched. Thereafter, the 1 st substrate is subjected to a surface treatment such as a hydrogen annealing method or a surface polishing method. The obtained 1 st substrate can be used again as a new 1 st substrate or a new 2 nd substrate

(example 12)

A1 st silicon single crystal substrate (8 inches in diameter) produced by the CZ method was prepared, and the 1 st substrate was subjected to thermal annealing to improve the surface layer quality. For the heat treatment, in H₂The hydrogen annealing was performed in a gas atmosphere at a temperature of 1200 ℃ for 1 hour.

Then, the surface of the substrate was formed to have a thickness of 200nm of SiO by thermal oxidation₂And (3) a layer. In addition, at an acceleration voltage of 40KeV, the dose was 5X 10¹⁶/cm²By plasma immersion ion implantation through the SiO of the surface thereof₂Layer of (a) H⁺Ions are implanted into the substrate.

SiO of the 1 st substrate to be prepared separately₂The layer surface and the surface of the silicon substrate (2 nd substrate) are placed to the upper side so as to be in contact with each other. The resulting substrate structure, when annealed at 600 c, is separated or split into two portions near the projected range of ion implantation. Since the ion-implanted layer (formed by ion implantation) is porous, the surface of the separated portion is rough. Then, while a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water was stirred, the 2 nd substrate side was selectively etched. The single crystal silicon of the formed SOI layer is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon serving as an etching stopper.

In addition to selective etching, non-selective etching and polishing may also be used to remove the ion-implanted layer. In the case of the polishing method, it is not necessary to perform heat treatment in hydrogen gas to planarize the surface of theresulting SOI substrate. However, in the case where polishing damage remains, it is preferable to perform heat treatment or remove the surface layer of the SOI substrate.

Further, the remaining portion of the 1 st substrate corresponds to the depth of ion implantation removed by the "oxidation + stripping" or "etching" method.

Specifically, a single crystal silicon layer having a thickness of 0.2 μm may be formed on the silicon dioxide film. The thickness of the single-crystal silicon layer formed was measured at 100 points over the surface of the SOI substrate. Furthermore, the uniformity of the layer thickness was 201 nm. + -.7 nm.

Subsequently, the SOI substrate was heat-treated at 1100 ℃ for 1 hour in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer. When the COP number contained in the surface of the single-crystal silicon layer was measured, the COP number was 10/W.

As a result of observing the cross section of the siliconlayer with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the silicon layer and good crystallinity was maintained in the silicon layer.

While stirring a mixed solution of 49% hydrofluoric acid, 30% hydrogen peroxide and water, the ion-implanted layer remaining on the side surface of the 1 st substrate was selectively etched. Thereafter, the 1 st substrate is subjected to a surface treatment such as a hydrogen annealing method or a surface polishing method. The resulting 1 st substrate can be used again as a new 1 st substrate or a new 2 nd substrate.

(example 13)

The 1 st substrate, polished on both surfaces, was subjected to the same processing steps as described in one of examples 1 to 12.

In any of the foregoing examples, the solution for selectively etching the ion-implanted layer is not limited to a mixed solution composed of 49% hydrofluoric acid, 30% hydrogen peroxide, and water. Since the ion implantation extends over a large surface area, the ion implanted layer is selectively etched, which can be:

HF；

HF + alcohol;

HF+H₂O₂+ an alcohol;

buffered HF + H₂O₂；

Buffered HF + alcohol;

buffered HF + H₂O₂+ an alcohol;

buffered HF;

such as an etching solution, or any suitable mixture of hydrofluoric acid, nitric acid and acetic acid.

Other processing steps can also be performed under various conditions and are not limited to the conditions specified in the foregoing examples.

(example 14)

A boron-doped (100) silicon wafer having a resistivity of 10. omega. cm produced by the CZ method was subjected to a heat treatment at 1200 ℃ for one hour in a hydrogen atmosphere. Then, the surface of the wafer was oxidized to form an oxide film of 250nm, and hydrogen ions were implanted into the resultant wafer. The ion implantation conditions were an acceleration voltage of 50KeV and a dose of 4X 10¹⁶/cm². Thus, the 1 st silicon wafer is produced.

The 1 st and 2 nd silicon wafers, respectively, are subjected to wet scrubbing employed in conventional silicon device processing to form them with clean surfaces. Then, the 1 st silicon wafer and the 2 nd silicon wafer were bonded to each other so that an oxide film having a thickness of 250nm was located inside. The bonded silicon wafer structure or assembly is placed in a heat treatment furnace and treated at 600 c for 10 hours, thereby enhancing the adhesive strength between the 1 st and 2 nd silicon wafers. The atmosphere for the heat treatment is oxygen. During the thermal treatment, the silicon wafer structure is separated or split at a depth corresponding to the projected range of ion implantation. The single crystal silicon film of the 1 st silicon wafer is transferred to the 2 nd silicon wafer together with the silicon oxide film, and thus, an SOI substrate is produced.

The thickness of the transferred single crystal silicon film was measured at 10mm dots on the surface of the SOI wafer, and the average value of the thickness was 280nm and the deviation thereof was. + -. 10 nm. Further, the root mean square (R) obtained when the surface roughness of the single crystal silicon film was examined at 256X 256 measurement points in a region of 1 μm square and 50 μm square by an atomic force microscope_rms) The values were 9.4nm and 8.5nm, respectively.

A plurality of such SOI wafers, each having a silicon dioxide film (57) on the back surface thereof, are placed in a vertical type heat treatment furnace including a core tube (90) made of quartz (shown in fig. 22). Within the furnace, a downward flow of gas (94) is caused. As shown in fig. 22, the SOI wafers are horizontally placed on a boat (93) made of quartz such that the silicon oxide film (57) on the back surface of one SOI wafer is opposed to the front surface of the SOI layer (53) of the other SOI wafer at an interval of about 6mm, and the centers of the SOI wafers may coincide with the axis of the core tube (90). Next, on the entire surface thereof, a commercially available silicon wafer (95) formed with a silicon dioxide film (96) is arranged at the same interval above the uppermost SOI wafer. After the atmosphere in the heat treatment furnace was changed to hydrogen, the temperature in the furnace was raised to 1180 ℃ and maintained for 2 hours. Subsequently, the temperature is again lowered. The silicon wafer is taken out, and the thickness of the SOI wafer (53) is measured again. The average decrease in the thickness of the SOI wafer was 80.3nm, and the thickness of the SOI wafer (53) became 199.6 mm. Here, the number of COP contained in each SOI layer was measured, which was about 9/W.

Further, the surface roughness of the single crystal silicon film subjected to the heat treatment was measured with an atomic force microscope. Root mean square (R) of its roughness in the 1 micron square_rms) The value is 0.11nm, as seen at 50 μmThe square internal is 0.35 nm. That is, the single crystalline silicon film is smoothed, comparable to common commercially available silicon wafers. Also, the concentration of boron atoms in the single crystal silicon film after the heat treatment is measured by a Secondary Ion Mass Spectrometer (SIMS). Thus, it was found that the boron concentration in all the films was reduced to 5X 10¹⁵/cm³Hereinafter, low enough for manufacturing a semiconductor device.

Further, when the cross-sectional state of the SOI layer before and after the heat treatment in the hydrogen atmosphere was observed with a Transmission Electron Microscope (TEM), a group of dislocations near the surface of each SOI layer before the heat treatment was found, and were not found after the heat treatment. This phenomenon can be explained as follows: the local regions of the SOI layer contain dislocation defects that are removed by etching with the SOI layer regions by etching based on the heat treatment.

(example 15)

A1 st silicon single crystal substrate manufactured by a CZ method is prepared. And the 1 st substrate is subjected to thermal annealing to improve the quality of the surface layer thereof. For the heat treatment, in H₂Hydrogen annealing in gas atmosphere at 1200 deg.CFire for 1 hour.

Then, SiO with a thickness of 200nm was formed on the surface of the substrate by thermal oxidation₂And (3) a layer. In addition, at an acceleration voltage of 40KeV, the dose was 5X 10¹⁶/cm²By passing SiO through the surface₂Layer of (a) H⁺Ions are implanted into the substrate.

SiO to separately prepared 1 st substrate₂The surface of the layer and the surface of the silicon substrate (2 nd substrate) were treated with plasma and washed with water. Then, the 1 st and 2 nd substrates are placed on top and brought into contact with each other.The resulting substrate structure was heat-treated at 300 c for 1 hour to improve the bonding strength between the 1 st and 2 nd substrates. When water having a jet flow of 0.2mm in diameter is sprayed onto the bonded substrate structure, the bonded wafer structure is separated or divided into two wafers through the ion-implanted layer (formed by ion implantation). Since the ion-implanted layer is porous, the separated wafer surface is rough. Thus stirring a mixture of 49% hydrofluoric acid, 30% hydrogen peroxide and waterAnd selectively etching the surface of the No. 2 substrate side in the mixed solution. The single crystal silicon of the formed SOI layer is left without being etched, and the ion-implanted layer is selectively etched and completely removed with the single crystal silicon as an etching stopper material.

Subsequently, the SOI substrate was heat-treated at 1100 ℃ for 1 hour in hydrogen. Root mean square (R) in the 50um square region of the obtained SOI substrate when the surface roughness thereof was evaluated by an atomic force microscope_rms) Approximately 0.2nm, which is equivalent to that of a commercially available ordinary silicon wafer. When the COP number contained in the surface of the single-crystal silicon layer was measured, the COP number was about 7/W.

(example 16)

An SOI substrate is manufactured from a CZ-silicon wafer. The method comprises the following steps:

(1) first, the CZ-silicon wafer was prepared and heat-treated in hydrogen at 1200 ℃ for 1 hour, thereby forming a low-defect layer. Incidentally, a CZ-silicon wafer which had not undergone this step (in other words, had not been subjected to heat treatment in hydrogen) was also prepared as a comparative sample.

(2) Subjecting the respective silicon wafers to thermal oxidation to form 200nm oxide (SiO)₂) And (3) a layer.

(3) At a dose of 5X 10¹⁶/cm²H at an acceleration voltage of 40KeV⁺Ion implantation is performed on the 1 st silicon wafer to form a separation layer.

(4) The 1 st silicon wafer and the 2 nd substrate (here, silicon substrate) are bonded to each other with the oxide layer inside.

(5) The bonded wafer structure is subjected to a heat treatment at 600 c to be separated or separated at the ion-implanted layer (separation layer).

(6) With HF, H₂O₂And water, and selectively etching the ion-implanted layer remaining on the No. 2 substrate. The semiconductor layer (SOI layer) of the SOI substrate thus formed had a thickness of 200 nm. + -. 6 nm.

(7) The SOI substrate was heat-treated in hydrogen at 1100 deg.c for 4 hours.

(8) Each SOI substrate was immersed in a 49% HF solution for 15 minutes. And then observed with an optical microscope.

For itThe medium SOI layer is an SOI substrate in which a low-defect layer is formed by a hydrogen annealing step (1). Observing 20cm of the surface of the SOI layer²In the region, no point was found at which the buried oxide film was etched. Strictly speaking, the density of such spotsis less than 0.05/cm²In contrast, the SOI substrate using the silicon wafer of the comparative example in which the low-defect layer was not formed was used. The etched buried oxide film was found to have dots with a diameter of about 100 microns at a density of 3.2/cm². This is because COPs contained in the silicon wafer of comparative example which had not been subjected to hydrogen annealing continue to occur in the SOI layer, and the HF solution enters the SOI layer through the positions of these COPs, etching the buried oxide layer. The etched spots are free of silicon and the resulting semiconductor device becomes a defective device.

In addition, after defects are developed by SECCO etching, the SOI substrate is subjected to an optical microscopeAnd (6) observing. Thus, it was found that in the SOI substrate using the silicon wafer subjected to hydrogen annealing, the etching holes were such that the defect density of COP, FPD, OSF was 10²/cm². On the other hand, the SOI substrate using the comparative example silicon wafer which had not been subjected to hydrogen annealing had an etching hole density of 10⁴/cm²。

It can be seen that according to the present invention, one layer in which COP or the like is reduced by heat-treating a wafer in an atmosphere containing hydrogen can be transferred onto another substrate of a substrate structure bonded by separating (wafer and substrate) an ion-implanted layer. By performing annealing in a reducing atmosphere containing hydrogen, defects inherent in bulk silicon as described above within the SOI substrate can be eliminated or reduced, which can improve the yield of semiconductor devices.

Further, the separation layer can be formed by implanting ions into the low-defect layer while improving the thickness uniformity of the SOI layer.

Further, according to the present invention, even in the case of manufacturing a large-scale integrated circuit of an SOI structure, a manufacturing process of a semiconductor substrate which can replace expensive SOS or SIMOX can be proposed.

Further, according to the present invention, even in the case of mass-producing a plurality of semiconductor substrate members having a single-crystal silicon film on the surface thereof, the silicon film can be etched while controlling the removal amount of the single-crystal silicon film thickness. Therefore, when such a process operation is applied to an SOI substrate, it is possible to simultaneously achieve flattening of the surface of each single-crystal silicon film, reduction of the boron concentration thereof, and maintenance of uniformity of the film thickness.

Claims

1. A semiconductor substrate fabrication process, comprising:

a preparation step of a 1 st substrate, the 1 st substrate having one surface layer portion subjected to hydrogen annealing;

a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and rare gases from the surface layer portion into the first substrate to form a separation layer;

a bonding step of bonding the 1 st substrate and a 2 nd substrate to each other so that the surface layer portion may be inside, thereby forming a multilayer structure; and

a transfer step; separating the multilayer structure at the separation layer, such that at least part of the surface layer is partially transferred to the No. 2 substrate.

2. The semiconductor substrate manufacturing process according toclaim 1, wherein the hydrogen annealing is heat-treating the single-crystal silicon substrate in a reducing atmosphere containing hydrogen.

3. A process for manufacturing a semiconductor substrate according to claim 2, wherein said single crystal silicon substrate is a CZ silicon wafer.

4. A process for manufacturing a semiconductor substrate according to claim 2, wherein said single crystal silicon substrate is an MCZ silicon wafer.

5. A process for producing a semiconductor substrate according to claim 2, wherein said surface layer portion is a low-defect layer whose number of COPs (crystal originated particles), FPDs (flow defects) or OSFs (oxidation induced stacking faults) in the single-crystal silicon substrate is smaller than that in any other region of the same substrate.

6. A process for manufacturing a semiconductor substrate according to claim 2, wherein said hydrogen annealing is performed at a temperature of 800 ℃ to the melting point of said 1 st substrate.

7. A process for manufacturing a semiconductor substrate according to claim 2, wherein said hydrogen annealing is performed at a temperature of 900 ℃ to 1350 ℃.

8. The process for producing a semiconductor substrate according to claim 1, wherein a density of COP contained in said surface layer portion is 0/cm³To 5X 10⁶/cm³In the meantime.

9. The process for producing a semiconductor substrate according to claim 1, wherein a density of COP contained insaid surface layer portion is 0/cm³To 1X 10⁶/cm³In the meantime.

10. The process for producing a semiconductor substrate according to claim 1, wherein a density of COP contained in said surface layer portion is 0/cm³To 1X 10⁵/cm³In the meantime.

11. The process for producing a semiconductor substrate according to any one of claims 8 to 10, wherein said COP density is per unit volume in a depth region from an outermost surface of said surface layer portion to said separation layer(1cm³) The number of COPs.

12. A process for producing a semiconductor substrate according to claim 1, wherein the number of COPs per wafer in the surface of said surface layer portion is between 0 and 500.

13. A process for producing a semiconductor substrate according to claim 1, wherein the number of COPs per wafer in the surface of said surface layer portion is between 0 and 100.

14. A process for producing a semiconductor substrate according to claim 1, wherein the number of COPs per wafer in the surface of said surface layer portion is between 0 and 10.

15. The process for producing a semiconductor substrate according to claim 1, wherein the number of COP per unit area in the surface of said surface layer portion is 0/cm²To 1.6/cm²In the meantime.

16. The process for producing a semiconductor substrate according to claim 1, wherein the number of COP per unit area in the surface of said surface layer portion is 0/cm²To 0.5/cm²In the meantime.

17. The process for producing a semiconductor substrate according to claim 1, wherein the number of COP per unit area in the surface of said surface layer portion is 0/cm²To 0.05/cm²In the meantime.

18. The process for producing a semiconductor substrate according to claim 1, wherein the OSF number per unit area in the surface of said surface layer portion is 0/cm²To 10/cm²In the meantime.

19. The process for producing a semiconductor substrate according to claim 1, wherein the FPD number per unit area in the surface of said surface layer portion is 0/cm²To 5X 10²/cm²Preferably 0/cm, in the range of²To 1X 10²/cm²In the meantime.

20. The process for producing a semiconductor substrate according to claim 1, wherein the oxygen concentration in the surface of said surface layer portion is less than 5 x 10¹⁷Atom/cm³。

21. A semiconductor substrate manufacturing process according to claim 5, wherein said separation layer is formed in said low-defect layer.

22. A process for manufacturing a semiconductor substrate according to claim 1, wherein said separation layer forming step is carried out with an implantation dose in the range of 1.0 x 10¹⁶/cm²To 2.0X 10¹⁷/cm²In the meantime.

23. A process for manufacturing a semiconductor substrate according to claim 1, wherein said separation layer is a dense layer of microbubbles.

24. A process for manufacturing a semiconductor substrate according to claim 1, wherein said separation layer forming step is performed by a plasma ion implantation method.

25. A process for manufacturing a semiconductor substrate according to claim 1, wherein said separation layer forming step is performed by an ion implantation method after an insulating layer is formed on said surface layer portion.

26. A process for manufacturing a semiconductor substrate according to claim 1, wherein said bonding step is carried out by interposing an insulating layer between said 1 st substrate and said 2 nd substrate.

27. A process for producing a semiconductor substrate according to claim 25 or 26, wherein said insulating layer is a thermal oxide film formed by thermally oxidizing a surface of said surface layer portion.

28. A process for producing a semiconductor substrate according to claim 1, wherein said 2 nd substrate is selected from the group consisting of a single crystal silicon substrate, a quartz substrate, a glass substrate and a compound semiconductor substrate.

29. A process for manufacturing a semiconductor substrate according to claim 1, wherein said bonding step is carried out by a process step comprising a heat treatment at a temperature of between room temperature and 400 ℃.

30. A process for manufacturing a semiconductor substrate according to claim 1, wherein said transferring step is carried out by separating said multilayer structure at an interface between said separation layer and said surface layer portion, at an interface between said separation layer and said 1 st substrate, or at least a combination thereof, within said separation layer.

31. A process for manufacturing a semiconductor substrate according to claim 1, wherein said transferring step is carried out by heat-treating the multilayer structure at a temperature in the range of 400 ℃ to 1000 ℃.

32. A process for manufacturing a semiconductor substrate according to claim 1, wherein said transferring step is carried out by heat-treating said multilayer structure at a temperature of 400 ℃ to 600 ℃.

33. A process for manufacturing a semiconductor substrate according to claim 1, wherein said transferring step is performed by ejecting a fluid against a side surface of said multilayer structure.

34. A process for manufacturing a semiconductor substrate according to claim 33, wherein said fluid is selected from the group consisting of water, air, nitrogen, carbonic acid gas and rare gas.

35. A process for manufacturing a semiconductor substrate according to claim 1, wherein said transferring step is performed by applying a tensile force or a shear force to said multilayer structure.

36. A process for manufacturing a semiconductor substrate according to claim 1, further comprising the step of removing said separation layer remaining on said surface layer portion covering said 2 nd substrate after said transferring step.

37. The process for producing a semiconductor substrate according to claim 36, wherein said step of removing said separation layer is carried out by heat treatment in a reducing atmosphere containing hydrogen.

38. The process for manufacturing a semiconductor substrate according to claim 36, wherein said step of removing said separation layer is carried out by immersing said separation layer in a solvent selected from the group consisting of hydrofluoric acid, a mixture of hydrofluoric acid plus at least one of an alcohol or hydrogen peroxide, buffered hydrofluoric acid, and a mixture of buffered hydrofluoric acid plus at least one of an alcohol or hydrogen peroxide, whereby said separation layer is selectively subjected to electroless wet chemical etching and removed.

39. A process for manufacturing a semiconductor substrate according to claim 36, wherein said step of removing said separation layer is performed by polishing said separation layer remaining on said 2 nd substrate.

40. A process for manufacturing a semiconductor substrate according to claim 36, wherein said step of removing said separation layer is performed by mechanochemical polishing.

41. The process for producing a semiconductor substrate according to any one of claims 38, 39 and 40, wherein said surface layer portion of said 1 st substrate transferred onto said 2 nd substrate is heat-treated in a reducing atmosphere containing hydrogen after said step of removing said separation layer remaining on said 2 nd substrate by polishing or etching.

42. A process for producing a semiconductor substrate according to claim 1, wherein said surface layer portion of said 1 st substrate transferred onto said 2 nd substrate has a tendency that the number of COPs per unit wafer decreases as the depth of said surface layer portion increases as measured from the outer side surface.

43. A process for producing a semiconductor substrate according to claim 1, further comprising the step of heat-treating said surface layer portion of said 1 st substrate transferred onto said 2 nd substrate in a reducing atmosphere containing hydrogen after said transferring step.

44. A process for manufacturing a semiconductor substrate according to claim 43, wherein said heat treatment is carried out at a temperature of 800 ℃ to a melting point of said 1 st substrate.

45. A process for manufacturing a semiconductor substrate according to claim 43, wherein said heat treatment is carried out at a temperature of 900 ℃ to 1350 ℃.

46. The process for producing a semiconductor substrate according to claim 37 or 43, wherein said heat treatment is carried out by aligning a surface of said surface layer portion of said 1 st substrate transferred onto said 2 nd substrate with silicon oxide.

47. The process for producing a semiconductor substrate according to claim 1 or 43, wherein the number of COP contained per unit wafer in the surface of the surface layer portion after the transferring step is between 0 and 100.

48. The process for producing a semiconductor substrate according to claim 1 or 43, wherein the number of COP contained per unit wafer in the surface of said surface layer portion after said transferring step is between 0 and 10.

49. The process for producing a semiconductor substrate according to claim 1 or 43, wherein after said transferring step, in the surface of said surface layer portion, the number of COPs contained per unit area is 0/cm²To 0.5/cm²In the meantime.

50. The process for producing a semiconductor substrate according to claim 1 or 43, wherein after said transferring step, in the surface of said surface layer portion, the number of COPs contained per unit area is 0/cm²To 0.05/cm²In the meantime.

51. A semiconductor substrate fabrication process, comprising:

a step of preparing a 1 st silicon substrate, said 1 st silicon substrate having a surface layer portion subjected to hydrogen annealing;

a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas into said 1 st silicon substrate from the side of said surface layer portion to form a separation layer;

a bonding step of bonding the 1 st substrate and the 2 nd silicon substrate to each other to form a multilayer structure;

a heat treatment step of heat-treating the 1 st substrate and the 2 nd substrate at the 1 st temperature while the multilayer structure is being formed or after the multilayer structure is formed;

a transfer step of separating said multilayer structure by said separation layer, thereby transferring at least a portion of said surface layer portion to said 2 nd substrate; and

a step of heat-treating said surface layer portion transferred onto said 2 nd substrate at a 2 nd heat treatment temperature higher than the 1 st heat treatment temperature.

52. A process for manufacturing a semiconductor substrate according to claim 51, wherein said 1 st heat treatment temperature is from room temperature to 500 ℃ and said 2 nd heat treatment temperature is from 800 ℃ to the melting point temperature of silicon.

53. A process for semiconductor thin film fabrication, comprising:

a separation layer forming step of implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen and a rare gas into said 1 st silicon substrate from the side of said surface layer portion, thereby forming a separation layer; and

a separation step of separating at least a part of said surface layer portion at said separation layer.

54. The process for producing a semiconductor thin film according to claim 53, wherein said hydrogen annealing is a heat treatment of said surface layer portion in a reducing atmosphere containing hydrogen gas.

55. The process for producing a semiconductor thin film according to claim 54, wherein said heat treatment is carried out at a temperature ranging from 800 ℃ to the melting point of silicon.

56. The process for producing a semiconductor film according to claim 53, wherein after said separating step, in the surface of said surface layer portion, the number of COPs contained per unit wafer is between 0 and 100.

57. The process for producing a semiconductor film according to claim 53, wherein after said separating step, in the surface of said surface layer portion, the number of COPs contained per unit wafer is between 0 and 10.

58. The process for producing a semiconductor thin film according to claim 53, wherein after said separation step, in the surface of said surface layer portion, the number of COP contained per unit area is 0/cm²To 0.5/cm²In the meantime.

59. The process for producing a semiconductor thin film according to claim 53, wherein after said separation step, in the surface of said surface layer portion, the number of COP contained per unit area is 0/cm²To0.05/cm²In the meantime.

60. A semiconductor substrate fabrication process, comprising:

a step of heat-treating the silicon substrate in a reducing atmosphere containing hydrogen;

a step of forming a separation layer; implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas into the silicon substrate from the surface layer portion side, thereby forming a separation layer;

a bonding step of bonding the silicon substrate and a 2 nd substrate to each other, thereby forming a multilayer structure, an

A transfer step of separating said multilayer structure at said separation layer, thereby transferring at least a part of said surface layer portion to said 2 nd substrate.

61. A multilayer structure formed by bonding a 1 st silicon substrate and a 2 nd silicon substrate to each other, wherein

The 1 st silicon substrate. The method comprises the following steps:

a separation layer formed by implanting ions of at least one element selected from the group consisting of hydrogen, nitrogen, and a rare gas; and

a multilayer structure, wherein the surface of said 1 st silicon substrate includes a surface layer portion formed by hydrogen annealing.