CN110534417B - Silicon-based semiconductor and compound semiconductor heterogeneous integration method and heterogeneous integrated device - Google Patents
Silicon-based semiconductor and compound semiconductor heterogeneous integration method and heterogeneous integrated device Download PDFInfo
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- CN110534417B CN110534417B CN201910683606.2A CN201910683606A CN110534417B CN 110534417 B CN110534417 B CN 110534417B CN 201910683606 A CN201910683606 A CN 201910683606A CN 110534417 B CN110534417 B CN 110534417B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 150000001875 compounds Chemical class 0.000 title claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 35
- 239000010703 silicon Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000010354 integration Effects 0.000 title claims abstract description 14
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical group [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
- -1 oxygen ions Chemical class 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention relates to the field of semiconductor manufacturing, in particular to a heterogeneous integration method and a heterogeneous integrated device of a silicon-based semiconductor and a compound semiconductor, which comprise the following steps: depositing an aluminum oxide dielectric layer on the surface of the silicon-based semiconductor; depositing an aluminum layer on the surface of the aluminum oxide dielectric layer for later use; depositing an aluminum oxide dielectric layer on the surface of the compound semiconductor; performing oxygen ion implantation on the compound semiconductor deposited with the aluminum oxide dielectric layer for later use; the above-mentioned spare silicon-based semiconductor is bonded with a compound semiconductor. The invention realizes the good bonding of the silicon-based semiconductor and the compound semiconductor, avoids the influence of a metal layer existing in metal bonding on a semiconductor material, and greatly improves the bonding efficiency and the device quality.
Description
Technical Field
The invention relates to the field of semiconductor materials, in particular to a heterogeneous integration method and a heterogeneous integration device of a silicon-based semiconductor and a compound semiconductor.
Background
Modern integrated circuits based on silicon-based CMOS technology are continuously advancing in integration level, power consumption and device characteristics as the feature size of CMOS devices is continuously shrinking. On the other hand, compound semiconductor devices and integrated circuits have been developed in the fields of ultra-high-speed circuits, microwave circuits, terahertz circuits, optoelectronic integrated circuits, and the like. Because the silicon-based semiconductor CMOS chip and the compound semiconductor chip are difficult to produce in the same wafer factory and can not realize process compatibility, if the silicon-based semiconductor CMOS chip and the compound semiconductor chip are organically combined, the problems that the device selection is limited in the field of integrated circuit design and devices made of different materials can not be mixed and integrated are solved, and the design and the performance of the integrated circuit are certainly greatly improved.
In summary, it is an urgent need to provide a method for realizing heterogeneous integration of compound semiconductor materials on silicon-based semiconductors.
Disclosure of Invention
The first purpose of the invention is to provide a heterogeneous integration method of a silicon-based semiconductor and a compound semiconductor, which is characterized in that an aluminum oxide/aluminum oxide structure is prepared on the silicon-based semiconductor, an aluminum oxide layer containing oxygen ions is prepared on the compound semiconductor, and the silicon-based semiconductor and the compound semiconductor are well bonded by utilizing the mutual diffusion effect of the aluminum ions and the oxygen ions through a bonding method.
The second purpose of the invention is to provide a heterogeneous integrated device, which has high quality and greatly improved performance.
In order to achieve the above purpose, the invention provides the following technical scheme:
a silicon-based semiconductor and compound semiconductor heterogeneous integration method is characterized by comprising the following steps:
depositing an aluminum oxide dielectric layer on the surface of the silicon-based semiconductor;
depositing an aluminum layer on the surface of the aluminum oxide dielectric layer for later use;
depositing an aluminum oxide dielectric layer on the surface of the compound semiconductor;
performing oxygen ion implantation on the compound semiconductor deposited with the aluminum oxide dielectric layer for later use;
the above-mentioned spare silicon-based semiconductor is bonded with a compound semiconductor.
The method can achieve the following technical effects:
the method comprises the steps of preparing an aluminum oxide/aluminum structure on a silicon-based semiconductor, preparing an aluminum oxide layer containing oxygen ions on a compound semiconductor, and realizing good bonding of the silicon-based semiconductor and the compound semiconductor by using the mutual diffusion effect of the aluminum ions and the oxygen ions through a bonding method, thereby avoiding the influence of a metal layer existing in metal bonding on a semiconductor material, and greatly improving the bonding efficiency and the device quality.
In addition, the silicon-based semiconductor and compound semiconductor heterogeneous integration method according to the present invention may further have the following additional technical features:
preferably, the thickness of the aluminum oxide dielectric layer on the surface of the silicon-based semiconductor is 30-300 nanometers.
Preferably, the thickness of the alumina dielectric layer on the surface of the compound semiconductor is 30 to 300 nanometers.
Preferably, the thickness of the aluminum layer is 3-30 nanometers.
Preferably, the ion implantation step is performed to an implantation depth of 3 to 30 nm.
Preferably, the conditions of the bonding step are vacuum, the temperature is 250-500 ℃, and the bonding time is 12-15 hours.
Preferably, the compound semiconductor is indium phosphide or gallium arsenide.
In summary, compared with the prior art, the invention achieves the following technical effects:
(1) the bonding efficiency is high:
(2) the heterogeneous integrated device has few defects and high quality;
(3) the device tends to be thinner;
(4) the process is simple and can realize automatic operation.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
FIG. 1 is a flow chart of a preparation method provided in example 1 of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
Example 1
As shown in fig. 1, heterogeneous integration is performed on a certain silicon-based semiconductor and compound semiconductor indium phosphide sheet, and the method specifically comprises the following steps:
step 1, depositing an aluminum oxide dielectric layer on the surface of a silicon-based semiconductor, wherein the thickness of the aluminum oxide dielectric layer is 30 nanometers;
step 2, depositing an aluminum layer on the surface of the aluminum oxide dielectric layer, wherein the thickness of the aluminum layer is 3 nanometers for later use;
step 3, depositing an aluminum oxide dielectric layer on the surface of the compound semiconductor, wherein the thickness of the aluminum oxide dielectric layer is 30 nanometers;
step 4, performing oxygen ion implantation on the compound semiconductor deposited with the aluminum oxide dielectric layer, wherein the implantation depth is 3 nanometers for later use;
and 5, bonding the standby silicon-based semiconductor and the compound semiconductor together, wherein the bonding condition is vacuum, the temperature is 250 ℃, and the bonding time is 12 hours.
It should be noted that, after or at the same time as step 1, in this embodiment, an aluminum oxide dielectric layer may be directly deposited on the surface of the compound semiconductor, and then an aluminum layer may be deposited on the aluminum oxide dielectric layer of the silicon-based semiconductor.
Example 2
The heterogeneous integration is carried out on a certain silicon-based semiconductor and a compound semiconductor gallium arsenide chip, and the method specifically comprises the following steps:
step 1, depositing an aluminum oxide dielectric layer on the surface of a silicon-based semiconductor, wherein the thickness of the aluminum oxide dielectric layer is 150 nanometers;
step 2, depositing an aluminum layer on the surface of the aluminum oxide dielectric layer, wherein the thickness of the aluminum layer is 15 nanometers for later use;
step 3, depositing an aluminum oxide dielectric layer on the surface of the compound semiconductor, wherein the thickness of the aluminum oxide dielectric layer is 150 nanometers;
step 4, performing oxygen ion implantation on the compound semiconductor deposited with the aluminum oxide dielectric layer, wherein the implantation depth is 15 nanometers for later use;
and 5, bonding the standby silicon-based semiconductor and the compound semiconductor together, wherein the bonding condition is vacuum, the temperature is 400 ℃, and the bonding time is 14 hours.
Example 3
The heterogeneous integration is carried out on a certain silicon-based semiconductor and a compound semiconductor gallium arsenide chip, and the method specifically comprises the following steps:
step 1, depositing an aluminum oxide dielectric layer on the surface of a silicon-based semiconductor, wherein the thickness of the aluminum oxide dielectric layer is 300 nanometers;
step 2, depositing an aluminum layer on the surface of the aluminum oxide dielectric layer, wherein the thickness of the aluminum layer is 3 nanometers for later use;
step 3, depositing an aluminum oxide dielectric layer on the surface of the compound semiconductor, wherein the thickness of the aluminum oxide dielectric layer is 300 nanometers;
step 4, performing oxygen ion implantation on the compound semiconductor deposited with the aluminum oxide dielectric layer, wherein the implantation depth is 30 nanometers for later use;
and 5, bonding the standby silicon-based semiconductor and the compound semiconductor together, wherein the bonding condition is vacuum, the temperature is 500 ℃, and the bonding time is 15 hours.
Through detection, the heterogeneous integrated device prepared by the embodiment has better quality and greatly improved performance.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A silicon-based semiconductor and compound semiconductor heterogeneous integration method is characterized by comprising the following steps:
depositing an aluminum oxide dielectric layer on the surface of the silicon-based semiconductor;
depositing an aluminum layer on the surface of the aluminum oxide dielectric layer for later use;
depositing an aluminum oxide dielectric layer on the surface of the compound semiconductor;
performing oxygen ion implantation on the compound semiconductor deposited with the aluminum oxide dielectric layer for later use;
bonding the spare silicon-based semiconductor and the compound semiconductor together;
the bonding step is performed under vacuum.
2. The method of claim 1, wherein the thickness of the alumina dielectric layer on the surface of the silicon-based semiconductor is 30-300 nm.
3. The method according to claim 1, wherein the thickness of the alumina dielectric layer on the surface of the compound semiconductor is 30 to 300 nm.
4. The method of claim 1, wherein the aluminum layer has a thickness of 3-30 nanometers.
5. The method of claim 1, wherein the ion implantation step is performed to a depth of 3-30 nm.
6. The method as claimed in claim 1, wherein the temperature of the bonding step is 250-500 ℃ and the bonding time is 12-15 hours.
7. The method according to claim 1, wherein the compound semiconductor is indium phosphide or gallium arsenide.
8. A heterogeneous integrated device, characterized in that it is obtained by the method according to any one of claims 1 to 7.
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