CN102184882A - Method for forming composite functional material structure - Google Patents

Method for forming composite functional material structure Download PDF

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CN102184882A
CN102184882A CN201110086465XA CN201110086465A CN102184882A CN 102184882 A CN102184882 A CN 102184882A CN 201110086465X A CN201110086465X A CN 201110086465XA CN 201110086465 A CN201110086465 A CN 201110086465A CN 102184882 A CN102184882 A CN 102184882A
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wafer
functional material
composite functional
material structure
donor wafer
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张轩雄
杨帆
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention relates to the technical field of semiconductors, in particular to a method for forming a composite functional material structure. The method comprises the following steps: implanting atomic species to act on the donor wafer to form a fragile region around the ion implantation projection range; bonding the donor wafer and the substrate wafer; carrying out two-step annealing heat treatment on the bonded structure under low vacuum to enable the fragile area to be stripped from the donor wafer, and forming a thin-layer structure on the substrate wafer; and processing the stripped donor wafer and the substrate wafer containing the thin-layer structure to obtain the donor material with the required thickness and the required composite functional material structure. According to the invention, the annealing process is carried out in low vacuum, so that the pressure on the wafer outside can be reduced, and the resistance to growth and maturation of micro defects inside the wafer is reduced; but also reduces the thermal budget, is beneficial to forming a high-quality composite functional material structure and improves the stripping efficiency of implanted ions.

Description

A kind of method that forms the composite functional material structure
Technical field
The present invention relates to technical field of semiconductors, be specifically related to the method that a kind of formation contains the composite functional material structure of the laminate structure of peeling off from donor wafer.
Background technology
Integrated circuit fast development in the last few years, the common aspect silicon CMOS circuit shows certain drawback along with the continuous decline of circuit size, and negative effect is also more and more serious.And new structure such as SOI(Silicon On Insulator), GOI(Germanium On Insulator), SSOI(strain-Silicon On Insulator), SGOI(Silicon-Germanium On Insulator) appearance of semiconductor-on-insulator structure such as, can continue to continue the validity of Moore's Law, have multiple advantage with respect to common aspect silicon novel semi-conductor structure: can eliminate the CMOS latch-up; Can weaken ghost effect, parasitic capacitance etc. help improving circuit speed; Radiation resistance is good; Be beneficial to miniaturization, power ratio is lower or the like.Therefore, it is to have good prospect that this type of novel semiconductor material structure is construed to, and is counted as the excellent material structure of preparation integrated circuit of future generation.
The present invention be directed to the improvement that a kind of smart peeling technology of this area class is carried out, to improve the charge stripping efficiency that injects ion.Such lift-off technology also is called as Smart-Cut , Smart-Cut Technology is at first to be proposed and apply for a patent in 1991 by M.Bruel, and deliver academic article in nineteen ninety-five, just immediately become the research focus of complex function wafer material once report, be subjected to paying close attention to widely and studying in more than ten years recently, and be utilized commercial field rapidly, up to the present based on Smart-Cut The SOI product of technology has captured nearly 80% the market share.Smart-Cut Technology is mainly concerned with following consecutive steps: (a) the H ion is injected into the SiO that is coated with thermal oxide growth 2The wafer A of dielectric layer; (b) wafer A and wafer B are carried out bonding, before the two wafer bondings through the standard cleaning PROCESS FOR TREATMENT, wafer B or have dielectric layer or do not have; (c) handle through two Buwen's degree, the first step makes wafer A peel off, and second step is for strengthening the bond strength of A, B wafer; (d) polishing is carried out on the surface after separating, to reach satisfactory surface standard.Utilize Smart-Cut The SOI that technology is made, with respect to additive method: the Si film thickness homogeneity that covers on the insulator is good, and crystal mass is good, and layer with layer between interface quality good, the material structure performance is good.
Smart-Cut Technical development till now, not only be confined to the Si sheet, having become a kind of thin layer shifts, the current techique of structure preparation is particularly for not causing the complex function wafer material of high density of defects (because lattice constant does not match) to have very large advantage by epitaxy technology (as soi structure) or extension.At present,, expanded to Ge from the scope of research material, III-V compound etc., technological means has also had continuous change and progressive such as the ionic species that injects, and annealing in process process or the like has also had some variations.It is reported that people such as R.E.Hurley has utilized the H-He ion to unite to inject successful reduction peels off annealing temperature, having formed thickness for SOI at 280 ℃-300 ℃ is 460 nanometers (nm), root-mean-square value (RMS) is peeled off for 3-6 nanometer (nm's), formed 300 ℃ the time for GeOI and to have peeled off, its root-mean-square value (RMS) major part is 11 nanometers (nm), and about 20% zone is 27nm.The somebody mixes in wafer in advance as boron (B) impurity simultaneously, also can play the effect that reduces annealing temperature.Report is also arranged recently through long process annealing (≤150 ℃, 22 hours), the quick thermal annealing process of carrying out under 300 ℃ then 5 minutes also can reach the good effect of peeling off.
Unite injection for all as mixing, divide the method for the changes and improvements of step annealing or the like, one of them most important reason is Smart-Cut For the annealing heat treatment of peeling off when taking place strict thermal budget limitations is arranged.Especially for GOI, during the isostructural formation of SGOI, big (thermal coefficient of expansion is respectively Ge=5.8 * 10 because thermal coefficient of expansion differs -6-1, Si=2.8 * 10 -6-1), when annealing temperature is too high for as Ge-Si bonding, Ge-SiO 2Strain even fracture will take place in the situation of bonding etc. because degrees of expansion is different, make that the interface between bonding quality, crystal mass, layer and the layer becomes very poor, thereby influence architecture quality and performance.
Summary of the invention
The object of the present invention is to provide a kind of method that forms the composite functional material structure, the charge stripping efficiency that can improve the injection ion is to form the composite functional material structure.
In order to achieve the above object, the technical solution used in the present invention is: a kind of method that forms the composite functional material structure comprises the steps:
Step 1 is injected atomic species and is acted on donor wafer, and ion injects the degree of depth and is controlled in the needed projected range by injecting energy, forms vulnerable areas around ion injects projected range;
Step 2 is carried out the standard cleaning PROCESS FOR TREATMENT with described donor wafer and substrate wafer, and surface ion activates to be handled, and then described donor wafer and described substrate wafer is carried out bonding;
Step 3, the structure behind the para-linkage is carried out double annealing heat treatment: first step annealing in process is to strengthen bond strength; Second step annealing carries out under low vacuum, makes described vulnerable areas peel off from described donor wafer, forms laminate structure on described substrate wafer;
Step 4, for donor wafer after peeling off and the substrate wafer that contains laminate structure, remove because ion injects formed surface damage through chemical mechanical polish process on the surface, obtains donor material and composite functional material structure.
In the such scheme, the donor wafer material is Ge, III-V compounds of group, GaN, AlN, Al in the described step 1 2O 3, ZnO, SiC, BaTiO 3, LaAlO 3Or diamond.
In the such scheme, injecting atomic species in the described step 1 is that H injects separately, He injects separately, H-He unites injection or B-H unites injection.
In the such scheme, when described step 1 intermediate ion injects, adopt mask plate to hide donor wafer and carry out the selectivity injection, described mask pattern is rectangular array or polygon array.
In the such scheme, described step 1 intermediate ion implantation dosage is about 1 * 10 16~3 * 10 17Cm -2, the injection energy is 15-200KeV, control is injected the degree of depth at 100-1500nm.
In the such scheme, substrate wafer or donor wafer are provided with the intermediate layer in the described step 2, and described intermediate layer thickness is 80-200nm, adopt the growth of thermal oxidation or chemical vapor deposition and epitaxial method.
In the such scheme, first step annealing temperature described in the described step 3 is 100-350 ℃, and the second step annealing temperature is 150-400 ℃, and carries out under the low vacuum condition.
In the such scheme, double annealing is being carried out in same body of heater in the described step 3.
Compared with prior art, the beneficial effect that the technical solution used in the present invention produced is as follows:
The present invention is placed on annealing process in the low vacuum and carries out, outside pressure be can be reduced in, thereby the inner tiny flaw growth of wafer, ripe resistance reduced wafer, make inside just constantly can expand, extend to whole parallel wafer surface direction with a less pressure.In addition, when in low vacuum, carrying out annealing process, reduce heat budget, promptly just can reach the same effect of peeling off under the higher temperature with lower temperature range, short time, lower internal pressure, help forming high-quality composite functional material structure, and improved the charge stripping efficiency that injects ion.
Description of drawings
Fig. 1 is the flow chart of the method for formation composite functional material structure provided by the invention;
The flow chart of the method for the formation composite functional material structure that Fig. 2 a-Fig. 2 d provides for the embodiment of the invention;
The flow chart of the method for the formation composite functional material structure that Fig. 3 a-Fig. 3 d provides for another embodiment of the present invention;
The flow chart of the method for the formation composite functional material structure that Fig. 4 a-Fig. 4 d provides for another embodiment of the present invention;
The flow chart of the method for the formation composite functional material structure that Fig. 5 a-Fig. 5 d provides for another embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples technical solution of the present invention is described in detail.
As shown in Figure 1, the invention provides a kind of method that forms the composite functional material structure, comprise the steps:
Step 101, ion flows into donor wafer, is specially:
Inject atomic species and act on donor wafer, ion injects the degree of depth and is controlled in the needed projected range by injecting energy, forms vulnerable areas around ion injects projected range;
Wherein, the donor wafer material is Ge, III-V compounds of group, GaN, AlN, Al 2O 3, ZnO, SiC, BaTiO 3, LaAlO 3Or diamond; Injecting atomic species is that H injects separately, He injects separately, H-He unites injection or B-H unites injection; When ion injects, adopt mask plate to hide and carry out the selectivity injection, injecting figure is rectangular array or polygon array; Ion implantation dosage is about 1 * 10 16~3 * 10 17Cm -2, the injection energy is 15-200KeV, control is injected the degree of depth at 100-1500nm;
Step 201 is carried out bonding with donor wafer and substrate wafer, is specially:
Donor wafer and substrate wafer are handled, and cleaned and remove surface contaminant, then donor wafer and substrate wafer are carried out bonding;
Can also be provided with the intermediate layer between substrate wafer and the donor wafer, intermediate layer thickness is 80-200nm, adopts the growth of thermal oxidation or chemical vapor deposition and epitaxial method;
Step 301, the structure behind the para-linkage is carried out double annealing heat treatment, is specially:
First step annealing in process is to strengthen bond strength; Second step annealing carries out under low vacuum, makes vulnerable areas peel off from donor wafer, forms laminate structure on substrate wafer; Double annealing is being carried out in same body of heater, and wherein, first step annealing temperature is 100-350 ℃, and the second step annealing temperature is 150-400 ℃, and carries out under the low vacuum condition;
Step 401 is carried out surface treatment to the material after peeling off, and is specially:
For donor wafer after peeling off and the substrate wafer that contains laminate structure, remove because ion injects formed surface damage through chemical mechanical polish process on the surface, obtains the donor material and the needed composite functional material structure of institute's required thickness.
Embodiment 1:
A kind of method that forms the germanium on insulator structure comprises the steps:
Step 101:He ion injects and acts on donor wafer Ge sheet 102, and dosage is 1 * 10 16, energy is 20KeV, and the H ion injects and acts on the Ge wafer, and dosage is 3 * 10 16Cm -2, the injection energy is 15KeV, the control ion injects the degree of depth at 100nm, and forms vulnerable areas 20 around this projected range, shown in Fig. 2 a;
Step 201: on substrate wafer Si sheet 202 surfaces with thermal oxidation process growth one deck SiO 2Film 302, thickness is about 80nm, Si sheet and Ge sheet is activated through standard cleaning technology and ion surface, with two wafers Ge-SiO at normal temperatures 2Bonding is shown in Fig. 2 b;
Step 301: the structure heat treatment of annealing behind the para-linkage, first step annealing temperature is 150 ℃, annealing time is 60 hours, in order to strengthen bond strength, the second step annealing temperature is 300 ℃ carries out under low vacuum, and the time is 40 hours, makes Ge sheet 102 peel off, thickness is that the Ge thin layer 102 of 100nm is transferred on the Si sheet 202, shown in Fig. 2 c;
Step 401: for Ge after peeling off and the substrate Si wafer that contains the Ge laminate structure, remove because ion injects formed surface damage through chemical mechanical polish process on the surface, obtains desired germanium on insulator structure, shown in Fig. 2 d.
Embodiment 2:
LaAlO on a kind of formation insulator 3The method of laminate structure comprises the steps:
Step 101:H ion injects and acts on LaAlO 3Wafer 103, dosage are 2 * 10 17Cm -2, the injection energy is 120KeV, the control ion injects the degree of depth at 750nm, and forms vulnerable areas 30 around this projected range, shown in Fig. 3 a;
Step 201: with LaAlO 3Wafer 103 and glass (glass) 203 is through cleaning and the ion surface activation, with two wafer bondings, shown in Fig. 3 b;
Step 301: the structure heat treatment of annealing behind the para-linkage, first step annealing temperature is 350 ℃, and annealing time is 40 hours, and in order to strengthen bond strength, the second step annealing temperature is 400 ℃ carries out under low vacuum, and the time is 60 hours, makes LaAlO 3Sheet is peeled off, and thickness is the LaAlO of 750nm 3Thin layer is transferred to glass 203(glass) on the sheet, shown in Fig. 3 c;
Step 401: for the LaAlO after peeling off 3With contain LaAlO 3The substrate sheet glass of laminate structure, surface are removed because ion injects formed surface damage through chemical mechanical polish process, obtain desired structure, shown in Fig. 3 d.
Embodiment 3:
A kind of formation comprises the method for the laminate structure of InP rectangular array, comprises the steps:
Step 101: utilize Au(1.5 μ m)/Ti (25nm) alloy 20 sputters on the InP wafer 104 as mask, makes that injecting figure is rectangular array, is of a size of 50 * 50-1000 * 1000 μ m 2, the He ion injects and acts on InP wafer 104, and dosage is 1 * 10 17Cm -2, injecting energy is that 200KeV control ion injects the degree of depth at 1500nm, shown in Fig. 4 a;
Step 201: remove mask, substrate sapphire (Al 2O 3) wafer 204 and InP wafer process standard cleaning technology, the line unit of going forward side by side closes, shown in Fig. 4 b;
Step 301: the structure heat treatment of annealing behind the para-linkage, first step annealing temperature is 100 ℃, annealing time is 40 hours, in order to strengthen bond strength, the second step annealing temperature is 150 ℃ and carries out under low vacuum, time is 240 hours, makes InP wafer 401 selectivity peel off, thickness be 1500nm's and the thin layer that comprises the InP rectangular array transfer to substrate sapphire (Al 2O 3) on the wafer 204, shown in Fig. 4 c;
Step 401: for InP after peeling off and the substrate wafer that contains the InP laminate structure, remove because ion injects formed surface damage through handling on the surface, obtains InP rectangular array structure on the desired insulator, shown in Fig. 4 d.
Embodiment 4:
A kind of method that forms the GaN laminate structure comprises the steps:
Step 101:H ion injects and acts on donor wafer GaN wafer 105, and dosage is 3 * 10 17Cm -2, energy is 50KeV, the control ion injects the degree of depth at 100nm, and forms vulnerable areas 10 around this projected range, as Fig. 5 a;
Step 201: at donor wafer GaN wafer 105 surfaces epitaxial growth one deck Al 2O 3Film 504, thickness is about 150nm, at substrate wafer Si sheet 205 surface CVD(chemical vapor depositions) the grow SiO of a layer thickness 200nm of method 2305, activate through standard cleaning technology and ion surface, will carry out Al with donor wafer 2O 3-SiO 2Bonding is shown in Fig. 5 b;
Step 301: the structure heat treatment of annealing behind the para-linkage, first step annealing temperature is 200 ℃, annealing time is 60 hours, in order to strengthen bond strength, the second step annealing temperature is 250 ℃ carries out under low vacuum, and the time is 60 hours, makes GaN wafer 105 peel off, thickness is that the GaN thin layer of 100nm is transferred on the Si sheet 205, shown in Fig. 5 c;
Step 401: for GaN after peeling off and the substrate Si wafer that contains the GaN laminate structure, remove because ion injects formed surface damage through chemical mechanical polish process on the surface, obtains the structure of GaN on the desired insulator, shown in Fig. 5 d.
The present invention is placed on annealing process in the low vacuum and carries out, outside pressure be can be reduced in, thereby the inner tiny flaw growth of wafer, ripe resistance reduced wafer, make inside just constantly can expand, extend to whole parallel wafer surface direction with a less pressure.In addition, when in low vacuum, carrying out annealing process, reduce heat budget, promptly just can reach the same effect of peeling off under the higher temperature with lower temperature range, short time, lower internal pressure, help forming high-quality composite functional material structure, and improved the charge stripping efficiency that injects ion.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.For a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. a method that forms the composite functional material structure is characterized in that, comprises the steps:
Step 1 is injected atomic species and is acted on donor wafer, and ion injects the degree of depth and is controlled in the needed projected range by injecting energy, forms vulnerable areas around ion injects projected range;
Step 2 is carried out the standard cleaning PROCESS FOR TREATMENT with described donor wafer and substrate wafer, and surface ion activates to be handled, and then described donor wafer and described substrate wafer is carried out bonding;
Step 3, the structure behind the para-linkage is carried out double annealing heat treatment: first step annealing in process is to strengthen bond strength; Second step annealing carries out under low vacuum, makes described vulnerable areas peel off from described donor wafer, forms laminate structure on described substrate wafer;
Step 4, for donor wafer after peeling off and the substrate wafer that contains laminate structure, remove because ion injects formed surface damage through chemical mechanical polish process on the surface, obtains donor material and composite functional material structure.
2. the method for formation composite functional material structure as claimed in claim 1 is characterized in that: the donor wafer material is Ge, III-V compounds of group, GaN, AlN, Al in the described step 1 2O 3, ZnO, SiC, BaTiO 3, LaAlO 3Or diamond.
3. the method for formation composite functional material structure as claimed in claim 1 is characterized in that: injecting atomic species in the described step 1 is that H injects separately, He injects separately, H-He unites injection or B-H unites injection.
4. the method for formation composite functional material structure as claimed in claim 1 is characterized in that: when described step 1 intermediate ion injects, adopt mask plate to hide donor wafer and carry out the selectivity injection, described mask plate figure is rectangular array or polygon array.
5. the method for formation composite functional material structure as claimed in claim 1 is characterized in that: described step 1 intermediate ion implantation dosage is about 1 * 10 16~3 * 10 17Cm -2, the injection energy is 15-200KeV, control is injected the degree of depth at 100-1500nm.
6. the method for formation composite functional material structure as claimed in claim 1, it is characterized in that: be provided with the intermediate layer between substrate wafer and the donor wafer in the described step 2, described intermediate layer thickness is 80-200nm, adopts the growth of thermal oxidation or chemical vapor deposition and epitaxial method.
7. the method for formation composite functional material structure as claimed in claim 1 is characterized in that: first step annealing temperature described in the described step 3 is 100-350 ℃, and the second step annealing temperature is 150-400 ℃, and carries out under the low vacuum condition.
8. the method for formation composite functional material structure as claimed in claim 1 is characterized in that: double annealing is being carried out in same body of heater in the described step 3.
CN201110086465XA 2011-04-07 2011-04-07 Method for forming composite functional material structure Pending CN102184882A (en)

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Cited By (12)

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CN102347219A (en) * 2011-09-23 2012-02-08 中国科学院微电子研究所 Method for forming composite functional material structure
CN104238262A (en) * 2013-06-14 2014-12-24 深圳市力振半导体有限公司 Mask prepared by semiconductor wafer
CN104867814A (en) * 2015-04-24 2015-08-26 厦门大学 Method for bonding preparation of Ge-on-insulator (GOI) through Ge film
CN105374664A (en) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 Preparation method of InP film composite substrate
CN105632894A (en) * 2015-12-30 2016-06-01 东莞市青麦田数码科技有限公司 Method for bonding compound semiconductor and silicon-based semiconductor
CN110534417A (en) * 2019-07-26 2019-12-03 中国科学院微电子研究所 Silicon-based semiconductor and compound semiconductor Manufacturing resource method and Manufacturing resource device
WO2020211089A1 (en) * 2019-04-19 2020-10-22 福建晶安光电有限公司 Method for preparing optoelectronic semiconductor chip and bonding wafer used therein
CN112259678A (en) * 2020-10-19 2021-01-22 济南晶正电子科技有限公司 Method for improving burst of thin film layer and thin film material
CN112420512A (en) * 2020-11-23 2021-02-26 上海新微科技集团有限公司 Method for separating thin film wafer from residual wafer in bonding structure
CN113013033A (en) * 2020-12-21 2021-06-22 上海大学 Ion beam etching method of metal thick film and application thereof
CN113078047A (en) * 2021-03-30 2021-07-06 芜湖启迪半导体有限公司 Bonded Si substrate, preparation method thereof, and method for preparing Si/3C-SiC heterostructure and 3C-SiC film
CN113097352A (en) * 2021-04-02 2021-07-09 中国科学院上海微系统与信息技术研究所 Gallium nitride semiconductor structure, Micro LED device and preparation method

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CN102347219A (en) * 2011-09-23 2012-02-08 中国科学院微电子研究所 Method for forming composite functional material structure
CN104238262A (en) * 2013-06-14 2014-12-24 深圳市力振半导体有限公司 Mask prepared by semiconductor wafer
CN104867814A (en) * 2015-04-24 2015-08-26 厦门大学 Method for bonding preparation of Ge-on-insulator (GOI) through Ge film
CN105374664A (en) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 Preparation method of InP film composite substrate
CN105632894A (en) * 2015-12-30 2016-06-01 东莞市青麦田数码科技有限公司 Method for bonding compound semiconductor and silicon-based semiconductor
WO2020211089A1 (en) * 2019-04-19 2020-10-22 福建晶安光电有限公司 Method for preparing optoelectronic semiconductor chip and bonding wafer used therein
CN110534417A (en) * 2019-07-26 2019-12-03 中国科学院微电子研究所 Silicon-based semiconductor and compound semiconductor Manufacturing resource method and Manufacturing resource device
CN110534417B (en) * 2019-07-26 2021-12-21 中国科学院微电子研究所 Silicon-based semiconductor and compound semiconductor heterogeneous integration method and heterogeneous integrated device
CN112259678A (en) * 2020-10-19 2021-01-22 济南晶正电子科技有限公司 Method for improving burst of thin film layer and thin film material
CN112259678B (en) * 2020-10-19 2022-07-19 济南晶正电子科技有限公司 Method for improving burst of thin film layer and thin film material
CN112420512A (en) * 2020-11-23 2021-02-26 上海新微科技集团有限公司 Method for separating thin film wafer from residual wafer in bonding structure
CN112420512B (en) * 2020-11-23 2024-07-05 上海新硅聚合半导体有限公司 Separation method of thin film wafer and residual wafer in bonding structure
CN113013033A (en) * 2020-12-21 2021-06-22 上海大学 Ion beam etching method of metal thick film and application thereof
CN113078047A (en) * 2021-03-30 2021-07-06 芜湖启迪半导体有限公司 Bonded Si substrate, preparation method thereof, and method for preparing Si/3C-SiC heterostructure and 3C-SiC film
CN113097352A (en) * 2021-04-02 2021-07-09 中国科学院上海微系统与信息技术研究所 Gallium nitride semiconductor structure, Micro LED device and preparation method

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Application publication date: 20110914