CN1315155C - Upper silicon structure of insulation layer and its prepn. method - Google Patents
Upper silicon structure of insulation layer and its prepn. method Download PDFInfo
- Publication number
- CN1315155C CN1315155C CN 200410017080 CN200410017080A CN1315155C CN 1315155 C CN1315155 C CN 1315155C CN 200410017080 CN200410017080 CN 200410017080 CN 200410017080 A CN200410017080 A CN 200410017080A CN 1315155 C CN1315155 C CN 1315155C
- Authority
- CN
- China
- Prior art keywords
- silicon
- monocrystalline silicon
- layer
- bonding
- aluminium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to a silicon on insulator structure and a preparation method thereof, which belongs to the field of microelectronic technology. The silicon on insulator structure is characterized in that an SOI structure substrate material which uses two or a plurality of composite layers of aluminium nitride or aluminum oxide or AlN, Al2O3, Si3N4 or SiO2 as a buried layer through the technology successively, such as Al film deposition, bonding, ion implantation, heat treatment combination, etc., namely to deposit an Al film on the surface of a silicon chip firstly; then, layer transferring is realized by boning technology, and a required buried layer material is formed by N or O ion implantation finally. The prepared silicon on insulator structure is composed of three layers, wherein the top layer is a single crystal silicon layer of which the thickness is 20 to 2000 nm, the middle layer is an insulating buried layer of which the thickness is 50 to 500 nm, and the bottom layer is a silicon substrate. The obtained SOI substrate material has the favorable heat conduction performance and is suitable for the requirements for SOI circuits with high temperature, high power or irradiation environment.
Description
Technical field
The present invention relates to (SOI) structure of silicon on a kind of insulating barrier and preparation method, relate to a kind of or rather with AlN or Al
2O
3Or AlN, Al
2O
3, Si
3N
4Or SiO
2Two or more composite beds are silicon substrate material and preparation method on the insulating barrier of buried regions, belong to the manufacturing process of semi-conducting material in the microelectronics.
Background technology
Silicon on the insulator is that SOI (Silicon on Insulator) circuit has advantages such as good high speed, low-power consumption, anti-irradiation, is used widely in military fields such as Aero-Space in early days.In recent years, fast development along with computer, communications industry, the technical advantage of SOI further obtains embodying, thereby gradually by successfully commercialization, and be considered to silicon integrated circuit technology (J.P.Collige, Silicon on Insulator Technology, the Materials to VLSI of 21st century, Kluwer AcademicPublishers, 1991).
Traditional SOI material is generally with SiO
2As insulating buried layer.Because SiO
2Thermal conductivity very poor (thermal conductivity only is 0.014W/ (cm.K)), limited the application of SOI device in high temperature and high-power circuit greatly.AlN, Al
2O
3As the insulating material of two kinds of function admirables, can form thermodynamically stable the contact with silicon, and AlN/Si, Al
2O
3/ Si interface has lower interface state density, leakage current, simultaneously AlN, Al
2O
3Also has high thermal (AlN:3.2W/ (cm.K); Al
2O
3: 0.3W/ (cm.K)), and good anti-radiation performance (Z.Y.Fan, G.Rong, J.Browning, N.Newman, Mater.Sci.Eng.B67 (1999) 90; K.H.Zaininger and A.S.Waxman, IEEE Trans.ElectronDevices ED-16, (1969) 333).With AlN, Al
2O
3Replace SiO
2The insulating buried layer of making SOI obviously can improve the application of SOI device in fields such as high temperature, high-power and radiation environments.
In recent years, with AlN, Al
2O
3Replace SiO
2The insulating buried layer technology of making SOI respectively by Lin Chenglu (Lin Chenglu etc.; " with aluminium nitride (AlN) is the SOI material preparation method of insulating buried layer " 98122067), (Wan Qing etc., " being the backing material and preparation method thereof of the insulating barrier silicon-on of buried regions with the alundum (Al " people such as (application numbers: 01126315)) proposes ten thousand green grass or young crops (application number:.Yet these existing technology prepare the insulating buried layer thin-film material (as AlN, Al at silicon chip surface earlier often
2O
3) carry out bonding technology then.This technology has two significant disadvantages: the one, be difficult to prepare high-purity buried regions material at silicon chip surface, especially AlN material, because the specific activity N of O is strong, be subjected to the restriction of present vacuum technique, the AlN film for preparing often contains a lot of oxygen (C.Lin, J.A.Kilner, R.J.Chater, J.Li, A.Nejim, J.P.Zhang and P.L.F.Hemment, NuclearInstruments and Methods in Physics Research Secon B:BeamInteractions with Materials and Atoms, vol.80/81 (1993) 323); The 2nd, in order to carry out follow-up bonding technology, the film surface that requirement prepares is very smooth, and this is difficult to reach under present film preparing technology.
Summary of the invention
The object of the present invention is to provide a kind of preparation with AlN or Al
2O
3Or AlN, Al
2O
3, Si
3N
4Or SiO
2In two or more composite bed be the SOI backing material and the preparation method of buried regions.
Preparation method characteristic provided by the invention is to adopt the Al thin film deposition to reduce the requirement of bonding technology to the combination interface surface smoothness in conjunction with the high temperature bonding, and utilize ion implantation technique to form insulating buried layer and improve the buried regions quality, overcome the past in the big shortcoming of surface formation insulating buried layer material surface roughness.Specifically, at first at silicon chip surface deposit Al film, at high temperature quick then bonding is because the fusing point of Al (or AlSi alloy) is very low, can combine with another silicon chip at an easy rate, can reduce the dependence of bonding greatly like this surperficial microroughness.Behind the bonding, by thinning techniques such as thinning back side, oxidation attenuates, perhaps by in the bonding silicon chip, introducing earlier porous silicon, epitaxial monocrystalline silicon on porous silicon behind Al/Si sheet bonding, utilizes stress then, split at the interface at extension/epitaxial silicon, obtain thin layer single crystalline Si/Al/Si substrat structure.Inject N or O ion by the ion injection toward the Al thin layer under the thin single crystal Si layer then, at high temperature the Al film is changed into AlN or Al
2O
3Film, thus required New type of S OI structure obtained.Because the existence of single crystalline Si thin layer, outside atmosphere is obviously reduced the influence of buried regions forming process, and buried regions purity is improved.Technology of the present invention is simple, and cost is low, and the potentiality of extensive industrialization are arranged.
In sum, the present invention relates to the preparation method of soi structure, it is characterized in that in available following two kinds of methods any one prepares:
First kind of preparation method:
(a) adopt sputter or vacuum evaporation method on monocrystalline silicon piece, to plate the layer of aluminum thin layer;
(b) face of silicon chip that another monocrystalline silicon piece and surface are coated with the Al thin layer is at 100-700 ℃ of temperature bonding, and the face etching from the nonbonding of monocrystalline silicon piece is thinned to wherein only surplus tens nanometers of a slice-hundreds of nanometer then;
(c) inject oxonium ion or nitrogen ion or nitrogen, two kinds of ions of oxygen in the bonding pad, the peak value that ion injects just in time is in the middle of the aluminium thin layer;
(d) bonding pad after step (c) is injected is annealed under 400-600 ℃ of temperature and protective atmosphere again, makes the nitrogen of injection or oxonium ion etc. form amorphous Al N or Al with the Al that is bonded in the inside
2O
3Buried regions.
Second kind of preparation method:
(a) adopt sputter or vacuum evaporation method on monocrystalline silicon piece, to plate the layer of aluminum thin layer;
(b) introduce porous silicon in another monocrystalline silicon piece, epitaxial monocrystalline silicon on porous silicon then is with the aluminize wafer bonding of thin layer of step (a);
(c) split at the epitaxial monocrystalline silicon place behind the bonding, obtain single crystalline Si/Al/Si substrat structure;
(d) use ion injection method then, inject nitrogen or oxonium ion in the Al thin layer under the monocrystalline silicon layer;
(e) under the 400-600 ℃ of temperature He under the nitrogen atmosphere Al thin layer is being changed into AlN or Al again
2O
3Buried regions;
Described preparation method characteristic is:
(1) the layer of aluminum layer thickness in the monocrystalline silicon sheet surface deposit is the 5-100 nanometer before the bonding, two silicon chips of bonding or common polishing monocrystalline silicon piece, or a slice is the polishing monocrystalline silicon piece, another sheet be on the porous silicon chip extension silicon chip of monocrystalline silicon thin film.
(2) before monocrystalline silicon piece forms sediment layer aluminium thin layer, at monocrystalline silicon sheet surface elder generation growth silicon nitride or silicon oxide film layer.
When (3) using first kind of preparation method, comprise etching, grinding, oxidation, etch stop or finishing method from thinning back side behind the bonding.
This shows that resulting insulation silicon-on constitutes by three layers, top layer is a monocrystalline silicon layer, and thickness is 20-2000nm, and the centre is an insulating buried layer, and thickness is 50-500nm, and bottom is silicon materials.
The insulating barrier silicon-on of made is characterized in that insulating buried layer, or aln layer, or alumina layer, or two or more are composited in aluminium nitride, silicon nitride, aluminium oxide or the silica.
Description of drawings
Fig. 1, the 2nd, being respectively two kinds of preparation methods provided by the invention is the technological process of the soi structure of buried regions with aluminium nitride, aluminium oxide.Wherein: 1 is a monocrystalline silicon piece, 101 is the monocrystalline silicon thin layer that 1 monocrystalline silicon piece obtains behind thinning back side, 2 is another monocrystalline silicon piece, 3 is the Al film, 301 are the Al thin layer behind injection nitrogen or the oxonium ion, form non-crystalline aluminum nitride or alumina insulation buried regions after the high-temperature process, 4 is porous silicon layer, and 5 is the epitaxy single-crystal silicon layer on the porous silicon 4.
Embodiment
To help to understand the present invention below in conjunction with the concrete illustrated embodiments of accompanying drawing, but the present invention never only is limited to embodiment.
Embodiment 1: as shown in Figure 1, behind deposit Al film on the monocrystalline silicon piece 2 with monocrystalline silicon piece 1 quick high-temp bonding, obtain monocrystalline silicon thin layer 10I from No. 1 silicon chip back side by burn into oxidation attenuate etc. then, in bonding pad, inject nitrogen or oxonium ion with certain energy and dosage then, form required soi structure after the high-temperature process.Concrete process conditions are to adopt the vacuum electron beam evaporation technique, preparation thickness is the Al thin layer of 5 nanometers on monocrystalline substrate, with another wafer bonding, corrode extremely wherein only surplus about 5 micron thickness of a slice then from the back side, corrode further attenuate by oxidation, HF again, carry out repeatedly reaching about 300 nanometer thickness until thin Si layer thickness.Energy with 200keV injects 5 * 10 in the Al thin layer
17/ cm
2It is the soi structure of buried regions that the nitrogen ion of dosage, high-temperature process obtain with AlN.
Embodiment 2: as shown in Figure 2, at first prepare porous silicon layer 4 on monocrystalline silicon piece 1 surface, then at 4 surperficial epitaxy single-crystal silicon thin layers; Monocrystalline silicon piece 2 surface deposition Al thin layers afterwards with monocrystalline silicon piece 1 quick high-temp bonding, and are handled and to be split from porous silicon layer, inject nitrogen or oxonium ion with certain energy and dosage in bonding pad then, form required soi structure in conjunction with high-temperature process.Concrete implementation process is to adopt sputtering method to prepare the Al thin layer that thickness is 8 nanometers on monocrystalline substrate; Another silicon chip earlier by anode oxidation method at surface preparation one deck porous silicon layer, adopt the monocrystalline silicon layer of molecular beam epitaxy technique extension 200 nanometers on porous silicon then, with epitaxial wafer and Al thin film deposition silicon chip high temperature bonding, and processing is split from porous silicon layer.The bonding pad surface finish of adopting chemico-mechanical polishing to split.In bonding pad, inject 1 * 10 with 150keV
18/ cm
2The oxonium ion of dosage, high-temperature process obtains with Al
2O
3Soi structure for buried regions.
Embodiment 3: embodiment 1 is before monocrystalline silicon piece deposit Al thin layer, elder generation's growth one deck silicon nitride or silica, and then carry out bonding by embodiment 1, ion injects and high-temperature process again, to form the buried regions of compound composition, then form silicon nitride, aluminium nitride or silica, aluminium nitride as independent injecting nitrogen ion, then form silicon nitride, aluminium oxide or silica, the compound composition of aluminium oxide as independent injection oxonium ion; Inject altogether as two kinds of ions of N, O, then form Si
3N
4, AlN, Al
2O
3Form composite construction, or SiO
2, AlN, Al
2O
3Composite construction.
Embodiment 4: embodiment 2 is before monocrystalline silicon piece deposit Al thin layer, elder generation's growth one deck silicon nitride or silica, and then carry out bonding by embodiment 1, ion injects and high-temperature process again, to form the buried regions of compound composition, then form silicon nitride, aluminium nitride or silica, aluminium nitride as independent injecting nitrogen ion, then form silicon nitride, aluminium oxide or silica, the compound composition of aluminium oxide as independent injection oxonium ion; Inject simultaneously as two kinds of ions of N, O, then form Si
3N
4, AlN, Al
2O
3Form composite construction, or SiO
2, AlN, Al
2O
3Composite construction.
Claims (4)
1. the preparation method of an insulating barrier silicon-on is characterized in that adopting in following two kinds of methods any one to prepare:
First kind of preparation method:
(a) on monocrystalline silicon piece, plate the layer of aluminum thin layer with sputter or vacuum evaporation method;
(b) another monocrystalline silicon piece and surface are coated with the monocrystalline silicon of aluminium thin layer unilateral under 100-700 ℃ of temperature bonding, form bonding pad and be thinned to wherein only surplus tens nanometers of a slice-hundreds of nanometer from the face etching of the nonbonding of monocrystalline silicon piece then;
(c) inject oxonium ion or nitrogen ion or nitrogen, two kinds of ions of oxygen in the bonding pad that makes toward step (b), the peak value that ion injects just in time is in the middle of the aluminium thin layer;
(d) bonding pad after step (c) is injected is annealed under 400-600 ℃ of temperature and protective atmosphere again, make the nitrogen or the oxonium ion of injection be bonded in inside aluminium form non-crystalline aluminum nitride or aluminium oxide buried regions;
Second kind of preparation method:
(a) adopt sputter or vacuum evaporation method on monocrystalline silicon piece, to plate the layer of aluminum thin layer;
(b) in another monocrystalline silicon piece, introduce porous silicon, and on porous silicon epitaxial monocrystalline silicon, plated the monocrystalline silicon piece bonding of aluminium thin layer then with step (a);
(c) split at the epitaxial monocrystalline silicon place behind the bonding, obtain monocrystalline silicon/aluminium/silicon substrate structure;
(d) use ion injection method then, inject nitrogen or oxonium ion in the aluminium thin layer under the monocrystalline silicon layer;
(e) under the 400-600 ℃ of temperature He under the protective atmosphere aluminium thin layer is being changed into aluminium nitride or aluminium oxide buried regions again.
2. by the described preparation method of claim 1, it is characterized in that bonding is the 5-100 nanometer at the layer of aluminum thickness of thin layer of monocrystalline silicon sheet surface deposit before, two silicon chips of bonding are the polishing monocrystalline silicon piece among first kind of preparation method, among second kind of preparation method, two silicon chip a slices of bonding for the polishing monocrystalline silicon piece, another sheet be on the porous silicon chip extension silicon chip of monocrystalline silicon thin film.
3. by claim 1 or 2 described preparation methods, it is characterized in that before monocrystalline silicon piece deposit aluminium thin layer, at monocrystalline silicon sheet surface elder generation growth silicon nitride or silicon oxide film layer.
4. by the described preparation method of claim 1, realize from the face attenuate of the nonbonding of monocrystalline silicon piece from passing through etching, grinding, oxidation, etch stop or finishing method behind the bonding when it is characterized in that using first kind of preparation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410017080 CN1315155C (en) | 2004-03-19 | 2004-03-19 | Upper silicon structure of insulation layer and its prepn. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410017080 CN1315155C (en) | 2004-03-19 | 2004-03-19 | Upper silicon structure of insulation layer and its prepn. method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1564308A CN1564308A (en) | 2005-01-12 |
| CN1315155C true CN1315155C (en) | 2007-05-09 |
Family
ID=34478765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410017080 Expired - Fee Related CN1315155C (en) | 2004-03-19 | 2004-03-19 | Upper silicon structure of insulation layer and its prepn. method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1315155C (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294645C (en) * | 2005-02-16 | 2007-01-10 | 中国电子科技集团公司第二十四研究所 | Method for making high-voltage high-power low differential pressure linear integrated regulated power supply circuit |
| CN100578736C (en) * | 2007-03-01 | 2010-01-06 | 中国科学院金属研究所 | Method of epitaxial directional growing nitrifier nano slice graticule with etch substrate method |
| FR2914493B1 (en) * | 2007-03-28 | 2009-08-07 | Soitec Silicon On Insulator | DEMONTABLE SUBSTRATE. |
| US20090115060A1 (en) | 2007-11-01 | 2009-05-07 | Infineon Technologies Ag | Integrated circuit device and method |
| CN101532179B (en) * | 2009-02-27 | 2011-04-20 | 中国电子科技集团公司第四十八研究所 | Method for manufacturing silicon wafer on insulator |
| CN102054666B (en) * | 2009-10-29 | 2012-11-28 | 华映视讯（吴江）有限公司 | Manufacturing method of semiconductor components |
| CN102214562A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102477537B (en) * | 2010-11-26 | 2014-08-20 | 鸿富锦精密工业（深圳）有限公司 | Casing and preparation method thereof |
| CN103035655B (en) * | 2012-12-29 | 2016-04-13 | 黄志强 | A kind of reinforced insulation silicon composite and preparation method thereof |
| CN104124133B (en) | 2013-04-24 | 2017-10-10 | 上海和辉光电有限公司 | A kind of method that cushion is manufactured in LTPS products |
| CN103579109B (en) * | 2013-11-01 | 2016-06-08 | 电子科技大学 | A kind of manufacture method of integrated optoelectronic circuit |
| WO2015109456A1 (en) * | 2014-01-22 | 2015-07-30 | 华为技术有限公司 | Soi substrate manufacturing method and soi substrate |
| CN105097732A (en) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | SOI high-voltage structure for reducing self-heating effect |
| CN105047752B (en) * | 2015-06-10 | 2017-08-11 | 上海新傲科技股份有限公司 | The surface modifying method of silicon substrate |
| CN107680901B (en) * | 2017-09-27 | 2020-07-07 | 闽南师范大学 | Flexible composite substrate for semiconductor epitaxy and manufacturing method |
| CN108847384A (en) * | 2018-06-11 | 2018-11-20 | 重庆伟特森电子科技有限公司 | A method of in silicon carbide-based on piece growth of oxygen layer |
| CN109773426A (en) * | 2019-01-26 | 2019-05-21 | 东莞市奕东电子有限公司 | A kind of novel new energy resource power battery bonding machining process |
| CN110534417B (en) * | 2019-07-26 | 2021-12-21 | 中国科学院微电子研究所 | Silicon-based semiconductor and compound semiconductor heterogeneous integration method and heterogeneous integrated device |
| CN114628229A (en) * | 2020-12-11 | 2022-06-14 | 中国科学院微电子研究所 | Multilayer semiconductor material structure and preparation method |
-
2004
- 2004-03-19 CN CN 200410017080 patent/CN1315155C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1564308A (en) | 2005-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1315155C (en) | Upper silicon structure of insulation layer and its prepn. method | |
| US9142448B2 (en) | Method of producing a silicon-on-insulator article | |
| JP7324197B2 (en) | Power and RF devices realized using engineered substrate structures | |
| JPH10265948A (en) | Substrate for semiconductor device and manufacture of the same | |
| TWI398019B (en) | Gallium nitride semiconductor device on soi and process for making same | |
| WO2006060466A2 (en) | Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate | |
| CN1385906A (en) | Generalized semiconductor film material on isolator and preparation method thereof | |
| CN1184692C (en) | Multilayer silicon gallide material on insulating layer and its prepn | |
| CN1153283C (en) | Substrate of silicon structure on insulating layer using alumina as buried layer and its preparing process | |
| JPH01161881A (en) | Josephson element and its manufacture | |
| CN101162626A (en) | Double face high-temperature superconducting film multi-layer structures and method for producing the same | |
| WO2020086998A1 (en) | Highly-textured thin films | |
| CN110854062B (en) | Gallium oxide semiconductor structure, MOSFET device and preparation method | |
| CN111226314B (en) | Multilayer composite substrate structure and preparation method thereof | |
| Annavarapu et al. | Progress towards a low-cost coated conductor technology | |
| CN112530855B (en) | Composite heterogeneous integrated semiconductor structure, semiconductor device and preparation method | |
| CN116013961B (en) | Preparation method of gallium nitride spin injection junction with self-oxidized surface | |
| JP3216089B2 (en) | Superconducting device manufacturing method and superconducting transistor using the same | |
| CN114823714A (en) | Monolithic heterogeneous integrated structure and preparation method | |
| CN115966462A (en) | Composite engineering substrate and preparation method thereof | |
| JP2006237384A (en) | STACKED WHOLE MgB2SIS BONDING AND METHOD THEREOF | |
| JPH07245409A (en) | Semiconductor device | |
| JP4104323B2 (en) | Method for fabricating Josephson junction | |
| JPH01211983A (en) | Josephson element | |
| CN116454124A (en) | Bipolar transistor with two-dimensional material and gallium nitride combined and preparation process thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070509 Termination date: 20110319 |