CN1184692C - Multilayer silicon gallide material on insulating layer and its prepn - Google Patents

Multilayer silicon gallide material on insulating layer and its prepn Download PDF

Info

Publication number
CN1184692C
CN1184692C CN 01126543 CN01126543A CN1184692C CN 1184692 C CN1184692 C CN 1184692C CN 01126543 CN01126543 CN 01126543 CN 01126543 A CN01126543 A CN 01126543A CN 1184692 C CN1184692 C CN 1184692C
Authority
CN
China
Prior art keywords
sige
layer
material
growth
sandwich construction
Prior art date
Application number
CN 01126543
Other languages
Chinese (zh)
Other versions
CN1332478A (en
Inventor
张苗
安正华
林成鲁
沈勤我
刘卫丽
Original Assignee
中国科学院上海冶金研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院上海冶金研究所 filed Critical 中国科学院上海冶金研究所
Priority to CN 01126543 priority Critical patent/CN1184692C/en
Publication of CN1332478A publication Critical patent/CN1332478A/en
Application granted granted Critical
Publication of CN1184692C publication Critical patent/CN1184692C/en

Links

Abstract

The present invention relates to a multilayer silicon gallium material on an insulating layer and a preparation method, which is characterized in that material is an SiGe layer or an SiO2 burying layer; a Si substrate is the SiGe layer or the SiO2 burying layer or a buffering layer; the Si substrate has a multilayer structure; the Ge component of the SiGe layer in a front material structure is smaller than 30%; the thickness is on a nano magnitude or is smaller; the Ge component of the SiGe layer in a back structure is any value from 0 to 100%. The preparation method comprises that an epitaxial SiGe single crystal film on an epitaxial single crystal silicon substrate or a single crystal silicon substrate grown with the buffering layer is adopted for forming a heterojunction structure; then, the SiO2 burying layer is formed under an epitaxial SiGe layer through oxygen ion injection and respective high temperature annealing thermal treatment for realizing the electric isolation of the SiGe film of a surface layer and the substrate material.

Description

Germanium material and preparation method on a kind of sandwich construction insulating barrier

Technical field

The present invention a kind ofly forms SiGe on the insulating barrier (SiGe-On-Insulator) sandwich construction novel microelectronic material and preparation method with extension and ion implantation technology, belongs to microelectronic.

Background technology

SiGe, SOI (silicon-on-insulator) are the advanced materials of current microelectronic.The SOI circuit has advantages such as high speed, low pressure, low-power consumption, anti-irradiation, has important application at aspects such as portable communications system, anti-irradiation devices.Because the existence of silicon dioxide buried regions in the SOI material, so utilize the device of surface silicon manufacturing and substrate to realize dielectric isolation, ghost effect is little, and device performance especially speed ability obviously improves.But traditional SOI material top layer film still is the Si material, utilizes the device or the silicon device of this made, and its performance such as speed still are subjected to the characteristic limitations of silicon materials itself.

The appearance of SiGe material and device makes silica-base material that the possibility that is applied to the high frequency field arranged, and the SiGe device is being beaten and got involved originally the application that GaAs class device only just is fit to usefulness.Company such as IBM, Motorola successfully develops the SiGe RF circuit that is applied to the portable communications system.SiGe material on silicon substrate can be by the component of control Ge, strain that growth thickness is controlled SiGe, band structure, crystal mass or the like.Utilizing no strain SiGe layer to obtain tensile strain Si thin layer is one of developing direction with very tempting application prospect of SiGe material.For obtaining strainless high-quality SiGe material, traditional method is the Ge component graded buffer layer of several microns of growths on silicon substrate earlier, the SiGe layer that regrowth Ge component is fixing.This method is extension cost height not only, the more important thing is that the higher SiGe resilient coating of defect concentration will influence device performance.

Summary of the invention

The present invention proposes SiGe and SOI technology are combined together to form SiGe-On-Insulator new material and preparation method.Promptly at first in monocrystalline substrate or contain epitaxy Si Ge material on the silicon substrate of high-quality resilient coating, to be met the high-quality SiGe material that the device manufacturing needs, inject and high-temperature annealing process by oxonium ion again, below the SiGe layer, form buried oxide, the SiGe layer that will be used to make device separates with substrate and buffering layer material, not only eliminated of the influence of the resilient coating of high defect concentration to device, also can realize the electric isolation of device and substrate, have the advantage of SiGe and two kinds of advanced materials of SOI concurrently.In addition, also propose the SiGe of the direct thickness that growth Ge composition is fixed on silicon substrate among the present invention, utilize then, can reduce SiGe extension cost greatly annotating the method formation SiGe-On-Insulator material that oxygen is isolated less than the strain critical value.

The SiGe material is provided on the sandwich construction insulating barrier that provides or is SiGe layer/SiO 2The structure of buried regions/resilient coating/Si substrate; On the Si substrate, form the SiGe layer and the SiO of a plurality of repetitions 2Layer, or on the resilient coating of Si substrate, form a plurality of SiGe layers and SiO 2Layer.It is the SiGe backing material that utilizes comparatively ripe epitaxy technique of development and ion implantation technology to obtain having isolation structure, have the advantage of SiGe and SOI concurrently, realize the electric isolation of device active region and backing material, reduce ghost effect, improve the high frequency performance of device, reduce power consumption, thereby satisfy the market demand of optoelectronic areas, field of wireless communication.Device technology and ripe silicon integrated circuit process compatible.With the SiGe-on-insulator material is substrate, can prepare the various devices with twin shaft tensile strain Si layer.On the other hand, SiGe/SiO 2The high reflectance at interface and the excellent optical property of SiGe material itself be that the extensive use of this material aspect photoelectron laid a good foundation.

A kind of concrete preparation method who utilizes extension and oxonium ion injection technology to form the SiGe-On-Insulator sandwich is:

1. at first choose monocrystalline p-or n-Si (100) sheet as substrate, after the custom integrated circuit technology of strictness is cleaned, after removing surperficial natural oxidizing layer, utilize molecular beam epitaxy (MBE) or high vacuum chemical vapor deposition film growth method epitaxy Si Ge layers on silicon chip such as (UHVCVD), form the SiGe/Si heterojunction, the one deck of also can growing earlier approaches the Si layer, the thickness of thin single crystal silicon layer is the 5-20 nanometer, and then growth SiGe layer, thickness is specifically decided on parameters such as Ge components in hundred nanometer scale or thinner.During growth SiGe layer, can be on silicon the direct growth component constant, less than the SiGe film of critical thickness, the Ge component is less than 30%; The SiGe resilient coating that the Ge component of also can growing earlier increases gradually, thickness be at the 0.5-5 micron, the fixing SiGe layer of last regrowth component, and the Ge component can be the arbitrary value between the 0-100%, specifically needs decide on SiGe buffer layer thickness and device application.Can carry out certain doping during growth.Growth temperature is 450 ℃~800 ℃.Buffer layer thickness 1.5-3 micron.

2. utilize bundle formula or plasma implanter to carry out oxonium ion and inject, the injection energy is 50~200keV, and specifically the injection degree of depth by needs decides.Implantation dosage is 10 17/ cm 2~10 18/ cm 2, the temperature when underlayer temperature is grown a little less than SiGe is as 400 ℃-750 ℃.

3. before the high annealing, can select growth one deck Si, SiO on SiGe earlier 2, Si 3N 4Perhaps other sandwich construction films are as the Annealing Protection layer.Then at 1200 ℃-1350 ℃, N 2, Ar or other have under the atmosphere of Annealing Protection performance and heat-treat, and can select to add a small amount of O in the annealing atmosphere 2As 0.5%-5% (volume ratio).Annealing time is not wait to 8 hours in 30 minutes.The purpose of annealing is to recover the damage of ion injection to top layer SiGe, regulates the strain regime of SiGe simultaneously, and makes the oxonium ion of injection assemble formation silicon dioxide buried regions.

4. the last Annealing Protection layer of removing the surface.Can handle the surface when needing, improve surface smoothness etc., to satisfy the needs that device level is used.

5. only need repeat above-mentioned technical process, until the multilayer (SiGe layer/SiO that needing to obtain 2Layer)/Si substrate or multilayer (SiGe layer/SiO 2Layer)/resilient coating/Si substrat structure.

Process chart is as shown in Figure 1:

What left side (1-1) was represented is: the fixing SiGe layer of the component of direct extension on silicon, and about 100 nanometers of the critical thickness of thickness SiGe (concrete numerical value is by Ge component and growth technique decision), oxonium ion can be injected into the top of SiGe layer bottom or silicon substrate.That form is SiGe/SiO 2/ Si structure.

What right side (1-2) was represented is: the SiGe resilient coating of elder generation's extension alternation Ge component on silicon substrate, and then the fixing SiGe layer of growth Ge component, thickness can thicker (as 1 micron), and oxonium ion can be injected in the fixing SiGe layer of component or the top of resilient coating.That form is SiGe/SiO 2/ resilient coating/Si structure.

Utilize the microelectronic component of the various strained heterostructure of SiGe material preparation on a kind of sandwich construction insulating barrier provided by the invention such as SiGe heterostructure, MOSFET, MODFET etc., have good device performance, especially have broad application prospects at inferior hundred nano-scale device, low-power consumption CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device, high-frequency element, photoelectricity integration field.

Description of drawings

Fig. 1 is the process flow diagram of SiGe material on the preparation sandwich construction insulating barrier provided by the invention.

Left side (Fig. 1-1) is the fixing SiGe layer of direct extension component on silicon substrate, and the formation structure is SiGe/SiO 2The New type of S OI material technology flow process of/Si; Right side (Fig. 1-2) is the SiGe resilient coating of elder generation's extension alternation Ge component on silicon substrate, and the Ge component of growing then is the SiGe layer fixedly, and the formation structure is SiGe/SiO 2The technological process of/resilient coating/Si.

Among the figure:

1-silicon substrate 2-epitaxy Si Ge layer

The SiGe resilient coating 4-Annealing Protection layer of 3-extension alternation Ge component

The 5-SiO2 buried regions.

Embodiment

Below by embodiment feasibility of the present invention is described, but do not limit content of the present invention.

Embodiment 1

Adopting molecular beam epitaxy (MBE) extension one thickness on n-(100) monocrystalline silicon is the monocrystalline silicon thin film of 10 nanometers, then epitaxial thickness less than 100 nanometers, Ge component constant be 15% SiGe layer, growth temperature is 650 ℃, is 4E17/cm with energy implantation dosage in silicon substrate of 60KeV 2Oxonium ion, make oxygen distribution interface and silicon substrate top under SiGe/Si of injection, underlayer temperature remains 550 ℃ during injection.Utilizing LPCVD to deposit a layer thickness on the SiGe/Si disk is the SiO of 100 nanometers 2Protective layer.At 1280 ℃, at Ar+1%O 2Annealing is 3 hours in the atmosphere.At last, with rare HF with top layer SiO 2Layer is removed, and obtaining structure is SiGe/SiO 2The SOI material of/Si.Can be used for making, anti-irradiation, at a high speed, the Low-Power CMOS circuit.

Embodiment 2

Adopt the at first SiGe resilient coating of growth Ge composition from 0 to 20 gradual change on p-(100) monocrystalline substrate of UHVCVD, thickness is 2 microns, and the Ge component of growing then is 20%, thickness is the SiGe layer of 500 nanometers, and whole SiGe growth temperature is 600 ℃.With implantation dosage among the energy SiGe of 160KeV is 7E17/cm 2Oxonium ion, the oxygen distribution of injection is in the SiGe layer, underlayer temperature remains 550 ℃ during injection.At 1350 ℃, Ar+0.5%O 2Annealing is 5 hours in (volume ratio) atmosphere.Obtaining concrete structure is SiGe/SiO 2The New type of S OI material of/SiGe/Si.Can be used as the advanced backing material of fiber waveguide and photo-detector.

Embodiment 3

Adopt on n-(100) monocrystalline silicon high vacuum chemical vapor deposition (UHVCVD) epitaxial thickness less than 50 nanometers, Ge component constant be 25% SiGe layer, growth temperature is 550 ℃, is 2.5E17/cm with energy implantation dosage in silicon substrate of 30KeV 2Oxonium ion, make oxygen distribution interface and silicon substrate top under SiGe/Si of injection, underlayer temperature remains 500 ℃ during injection.Utilizing LPCVD to deposit a layer thickness on the SiGe/Si disk is the SiO of 10 nanometers 2Protective layer, the Si of deposit 200 nanometers again 3N 4Form the Annealing Protection layer of composite construction.At 1300 ℃, annealing is 6 hours in Ar atmosphere.At last, with removing top layer Si 3N 4And SiO 2Remove, obtaining structure is SiGe/SiO 2The SOI material of/Si.

Embodiment 4

Adopting molecular beam epitaxy (MBE) extension epitaxial thickness 100 nanometers, Ge component constant on p-(100) monocrystalline silicon is 10% SiGe layer, and growth temperature is 600 ℃, is 3.5E17/cm with energy implantation dosage in silicon substrate of 50KeV 2Oxonium ion, make oxygen distribution interface and silicon substrate top under SiGe/Si of injection, underlayer temperature remains 450 ℃ during injection.At 1180 ℃, at Ar+0.5%O 2Annealing is 2 hours in the atmosphere.At last, with rare HF with a small amount of SiO in top layer 2Layer is removed, and obtaining structure is SiGe/SiO 2The SOI material of/Si.

Embodiment 5

Adopting high vacuum chemical vapor deposition (UHVCVD) extension one thickness on n-(100) monocrystalline silicon is that 2.5 microns Ge component increases the film of (from 0 to 40%) gradually, epitaxial thickness 200 nanometers, Ge component are constant then is 45% SiGe layer, growth temperature is 450 ℃, is 1E18/cm with energy implantation dosage in the SiGe layer of 100KeV 2Oxonium ion, underlayer temperature remains 400 ℃ during injection.At 1250 ℃, at Ar+1%O 2Annealing is 3 hours in the atmosphere.At last, with rare HF with top layer SiO 2Layer is removed, and adopts chemico-mechanical polishing (CMP) technical finesse surface, and obtaining structure is SiGe/SiO 2/ Si structure.Repeat extension, oxonium ion injection and heat treatment process then, obtain SiGe/SiO 2/ SiGe/SiO 2/ Si structure continues repetition until the number of plies that needing to obtain, and promptly forms SiGe/SiO 2/ ... / SiGe/SiO 2The novel multi-layer SOI material of/Si.The optical reflection performance is improved at the available multilayer interface that utilizes, thus optics such as manufacturing detector.

Claims (8)

1, SiGe material on a kind of sandwich construction insulating barrier comprises silicon substrate, it is characterized in that material or is SiGe layer/SiO 2The structure of buried regions/resilient coating/Si substrate, or the SiGe layer and the SiO of a plurality of repetitions of formation on the Si substrate 2Layer, or on the resilient coating of Si substrate, form a plurality of SiGe layers and SiO 2Layer.
2, by SiGe material on the described sandwich construction insulating barrier of claim 1, it is characterized in that SiGe layer/SiO 2Buried regions/resilient coating/Si substrat structure mesexine SiGe layer Ge component is fixed, for the arbitrary value between 0-100%, is specifically decided on resilient coating.
3, by SiGe preparation methods on the insulating barrier of the described sandwich construction of claim 1, it is characterized in that adopting extension that epitaxial growth SiGe monocrystal thin films on the monocrystalline substrate of resilient coating is arranged in monocrystalline substrate or growth, form heterostructure, under extension SiGe layer, form a silicon dioxide buried regions through oxonium ion injection and high annealing heat treatment then, realize the electric isolation of top layer SiGe film and backing material.
4, by SiGe preparation methods on the described sandwich construction insulating barrier of claim 3, it is characterized in that on the silicon substrate before the epitaxial growth SiGe, the monocrystalline silicon membrane that the one deck of can growing earlier is thin, thickness is the 5-20 nanometer.
5, by SiGe preparation methods on the described sandwich construction insulating barrier of claim 3, it is characterized in that epitaxy Si Ge layer on the described monocrystalline silicon, or the fixing SiGe thin layer of direct growth component, or the SiGe resilient coating that increases gradually of growth Ge component, the fixing SiGe layer of last growth components; Buffer layer thickness is between the 1.5-3 micron, and the fixing SiGe thickness of the component of generation is hundred nanometer scale; Growth temperature is 450 ℃-800 ℃.
6, by SiGe preparation methods on the described sandwich construction insulating barrier of claim 3, the energy that it is characterized in that oxonium ion is 50-200keV, and dosage is 10 17/ cm 2-10 18/ cm 2, the temperature when underlayer temperature is lower than the SiGe growth during injection is 400 ℃-750 ℃.
7, by SiGe preparation methods on the described sandwich construction insulating barrier of claim 3; it is characterized in that high annealing heat treatment is at 1200-1350 ℃; under nitrogen, argon gas or other protective atmosphere, and can add minor amounts of oxygen, annealing time is 0.5-8 hour.
8, by SiGe preparation methods on the described sandwich construction insulating barrier of claim 3; it is characterized in that before annealing heat treatment SiGe top layer silicon growth layer, silicon dioxide or the silicon nitride single thin film after oxonium ion injects as the Annealing Protection layer, or with the film of sandwich construction as the Annealing Protection layer.
CN 01126543 2001-08-24 2001-08-24 Multilayer silicon gallide material on insulating layer and its prepn CN1184692C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 01126543 CN1184692C (en) 2001-08-24 2001-08-24 Multilayer silicon gallide material on insulating layer and its prepn

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 01126543 CN1184692C (en) 2001-08-24 2001-08-24 Multilayer silicon gallide material on insulating layer and its prepn

Publications (2)

Publication Number Publication Date
CN1332478A CN1332478A (en) 2002-01-23
CN1184692C true CN1184692C (en) 2005-01-12

Family

ID=4666557

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 01126543 CN1184692C (en) 2001-08-24 2001-08-24 Multilayer silicon gallide material on insulating layer and its prepn

Country Status (1)

Country Link
CN (1) CN1184692C (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004001857A1 (en) * 2002-06-19 2003-12-31 Massachusetts Institute Of Technology Ge photodetectors
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
US7169226B2 (en) 2003-07-01 2007-01-30 International Business Machines Corporation Defect reduction by oxidation of silicon
EP1708254A4 (en) * 2004-01-15 2010-11-24 Japan Science & Tech Agency Process for producing monocrystal thin film and monocrystal thin film device
CN100373531C (en) * 2004-04-09 2008-03-05 电子科技大学 Preparation of nano-junction
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
CN100336171C (en) * 2004-09-24 2007-09-05 上海新傲科技有限公司 Germanium silicon material on insulator based on injection oxygen isolation technology and its preparing method
CN100345935C (en) * 2005-03-22 2007-10-31 电子科技大学 Method for preparing nano zinc oxide luminescent materials in monocrystal alpha-Al201
CN100595928C (en) * 2007-12-28 2010-03-24 上海新傲科技股份有限公司 Semiconductor substrate, preparing technique and application in advanced three-dimensional electronic packaging
CN104003346B (en) * 2013-02-25 2019-05-17 中芯国际集成电路制造(上海)有限公司 A kind of membrane structure, pressure sensor and electronic device
CN106409649B (en) * 2015-07-30 2019-03-15 沈阳硅基科技有限公司 A kind of multilayer SOI material and preparation method thereof
CN108010840A (en) * 2016-11-02 2018-05-08 株洲中车时代电气股份有限公司 The preparation method and semiconductor devices of doped semiconductor device

Also Published As

Publication number Publication date
CN1332478A (en) 2002-01-23

Similar Documents

Publication Publication Date Title
US10510581B2 (en) Methods of forming strained-semiconductor-on-insulator device structures
US20160225609A1 (en) Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods
JP2020074418A (en) High resistivity SOI wafer and method of manufacturing the same
US7405142B2 (en) Semiconductor substrate and field-effect transistor, and manufacturing method for same
TWI331777B (en) Method for fabricating sige-on-insulator (sgoi) and ge-on-insulator (goi) substrates
KR100690421B1 (en) Strained si based layer made by uhv-cvd, and devices therein
US7855127B2 (en) Method for manufacturing semiconductor substrate
US7786468B2 (en) Layer transfer of low defect SiGe using an etch-back process
JP4269541B2 (en) Semiconductor substrate, field effect transistor, method of forming SiGe layer, method of forming strained Si layer using the same, and method of manufacturing field effect transistor
KR950006967B1 (en) Method of producing a thin silicon-on-insulator layer
EP1709671B1 (en) Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density
US7288430B2 (en) Method of fabricating heteroepitaxial microstructures
CN100456424C (en) Method of creating defect free high Ge content (25%) SIGE-on-insulator (SGOI) substrates using wafer bonding techniques
US7265030B2 (en) Method of fabricating silicon on glass via layer transfer
JP4949628B2 (en) Method for protecting a strained semiconductor substrate layer during a CMOS process
KR100392166B1 (en) Semiconductor device and method for manufacturing the same
US6768175B1 (en) Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
JP4722823B2 (en) Method for manufacturing composite substrate with improved electrical characteristics
JP3352340B2 (en) Semiconductor substrate and method of manufacturing the same
US7238622B2 (en) Wafer bonded virtual substrate and method for forming the same
TWI225283B (en) Strained semiconductor on insulator substrate and method of forming the same
US5882987A (en) Smart-cut process for the production of thin semiconductor material films
DE69728355T2 (en) Method of manufacturing a semiconductor article
CN1311546C (en) Method for producing SiGe substrate material on insulator and substrate material
US7341927B2 (en) Wafer bonded epitaxial templates for silicon heterostructures

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
PB01 Publication
C06 Publication
GR01 Patent grant
C14 Grant of patent or utility model
CP03 Change of name, title or address

Address after: No. 865, Changning Road, Shanghai, Changning District

Patentee after: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences

Address before: No. 865, Changning Road, Shanghai, Changning District

Patentee before: Shanghai Metallurgical Inst. of C.A.S

ASS Succession or assignment of patent right

Owner name: PROUD OF THE NEW SHANGHAI TECHNOLOGY CO.

Free format text: FORMER OWNER: SHANGHAI INST. OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCI

Effective date: 20090703

C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee

Owner name: SHANGHAI INST. OF MICROSYSTEM AND INFORMATION TECH

Free format text: FORMER NAME: SHANGHAI METALLURGY INST., CHINESE ACADEMY OF SCIENCES

TR01 Transfer of patent right

Effective date of registration: 20090703

Address after: No. 200, Pratt & Whitney Road, Shanghai, Jiading District

Patentee after: Shanghai Xin'ao Science and Technology Co., Ltd.

Address before: No. 865, Changning Road, Shanghai, Changning District

Patentee before: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences

CP01 Change in the name or title of a patent holder

Address after: 201821 Shanghai, Jiading District Pratt & Whitney Road, No. 200

Patentee after: Shanghai Simgui Technology Co., Ltd.

Address before: 201821 Shanghai, Jiading District Pratt & Whitney Road, No. 200

Patentee before: Shanghai Xin'ao Science and Technology Co., Ltd.

C56 Change in the name or address of the patentee

Owner name: SHANGHAI SIMGUI SCIENCE AND TECHNOLOGY CO., LTD.

Free format text: FORMER NAME: PROUD OF THE NEW SHANGHAI TECHNOLOGY CO.

EXPY Termination of patent right or utility model
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050112

Termination date: 20140824