CN106409649B - A kind of multilayer SOI material and preparation method thereof - Google Patents

A kind of multilayer SOI material and preparation method thereof Download PDF

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Publication number
CN106409649B
CN106409649B CN201510460906.6A CN201510460906A CN106409649B CN 106409649 B CN106409649 B CN 106409649B CN 201510460906 A CN201510460906 A CN 201510460906A CN 106409649 B CN106409649 B CN 106409649B
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soi
multilayer
silicon wafer
step
surface
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CN201510460906.6A
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CN106409649A (en
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陈学斌
柳清超
毛俭
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沈阳硅基科技有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments

Abstract

The invention discloses a kind of multilayer SOI materials and preparation method thereof, belong to technical field of semiconductor material preparation.The material is multilayer SOI stacked structure, and the topsheet surface and bottom surface of the stacked structure are silicon wafer, and middle section is that silicon wafer and BOX layer are arranged alternately mode.In preparation process, by the stress of the method removal oxidation piece of CMP, stack the bonding of multilayer SOI up.Surface be aoxidize piece carries out 1-5min surface treatment with HF, and plasma-activated processing;Surface is silicon wafer with dense H2SO4Carry out 1-5min surface treatment.It has handled in this way and has carried out normal temperature bonding again, the temperature low-temperature annealing less than 500 DEG C can have been used, and obtain extraordinary bonding quality, edge loses in subsequent thinning process can be less than 0.5mm.Entire bonding process is completed in low temperature, and defect will not be generated by so that the device layer of multilayer SOI is not passed through high temperature.

Description

A kind of multilayer SOI material and preparation method thereof

Technical field

The present invention relates to technical field of semiconductor material preparation, and in particular to a kind of multilayer SOI material and preparation method thereof.

Background technique

SOI (Silicon On Insulator, the silicon on insulating layer) technology is introduced between top layer silicon and backing bottom One layer of buries oxide layer (BOX layer), its manufacturing process complexity and it is at high cost etc. due to, technology is always by external a small number of states Family is monopolized, and application remains high on the high-end products such as military, space and tip electric appliance always.In recent years, with SOI system The progress of technology, the reduction of cost are made, insulating layer silicon SOI starts gradually to move towards the business application stage, commercial market is opened up, Have become base material necessary to IT industry new product.21st century is entered particularly into, silicon SOI material accounts for world's silicon half on insulating layer Conductor material market share gradually increases, and large-scale application soi wafer is to have arrived in the epoch of electronics manufacturing mainstay material.

Nowadays, consumer electronics market leads the market MEMS rapid growth, therefore is performance driving, cost driving and ruler now The epoch of very little driving.For MEMS manufacture, soi wafer is a kind of promising material.When CMOS size constantly reduces, surpass More the new device structure of CMOS technology and system architecture continue to bring out, and use the SOI continuous development of " tradition " by now SOI with cavity, developing deeply are the SOI with cavity, channel isolation and through silicon via.MEMS structure design becomes increasingly complex, Requirement to soi layer number and quality is higher and higher.

Increase integrated level to reduce package dimension, the demand to soi layer number is also increasing.And the manufacture of traditional SOI Technology is needed by multiple high temp, and more mostly the quality of every layer of silicon wafer will be poorer for the high temperature number of process.With the increasing of the number of plies Add the stress inside SOI also to will increase, is very restricted the stacking of the number of plies.And general bonding can not make silicon wafer side Edge bonding it is fine, need to do chamfer angle technique just and can be carried out thinned, the diameter that top layer silicon wafer afterwards is thinned will reduce 3-6mm, this Area workable for the more top layers of the number of plies that sample stacks is with regard to smaller.How quality good device silicon layer is obtained, and edge damages Losing less multilayer SOI is a very important research topic.

Summary of the invention

The purpose of the present invention is to provide a kind of multilayer SOI material and preparation method thereof, the device silicon layer of high quality and compared with The preparation method of N layer (3 < N < 15) SOI of small edge penalty.Stress removal is carried out to soi layer by using the method for CMP, And use dense H2SO4Silicon chip surface and DHF processing oxidation piece surface are handled, then by using plasma-activated technology, makes room temperature Under can be carried out being bonded, and annealing temperature is less than 500 DEG C.Ratio can be obtained by carrying out multilayer SOI stacking in this way Preferable device layer quality, it is several layers of that the number of plies of stacking can achieve ten, and does not need to do edge chamfer, is bonded edge damage every time Mistake can be less than 0.5mm.

To achieve the above object, the technical solution adopted by the present invention is that:

A kind of multilayer SOI material, the material are multilayer SOI stacked structure, in which: the topsheet surface of the stacked structure and bottom Layer surface is silicon wafer, and middle section is that silicon wafer and BOX layer (buried oxide) are arranged alternately mode.The crystal orientation selection of silicon wafer used can To be<100>or<111>, resistivity selection, which can be, is heavily doped to high resistant.

The BOX layer is silica.

The BOX layer is with a thickness of 20nm~2 μm, and multilayer SOI is with a thickness of 1 μm~500 μm.

Soi layer number is 3~15 in the material.

Above-mentioned multilayer SOI material is prepared in accordance with the following steps:

(1) 6 cun or 8 cun of silicon wafer is chosen, resistivity and crystal orientation select according to actual needs, it is thinned to required thickness, Then it is aoxidized on the side of the silicon wafer or double-sided surface, obtaining the silicon wafer with oxide layer, (silica is as SOI's BOX layer), oxidation can use common process;

(2) silicon wafer with oxide layer prepared by step (1) is first subjected to CMP destressing processing, then carries out 1- with DHF 5min surface treatment, then carry out plasma-activated processing;

(3) prepare a SOI piece, the resistivity and crystal orientation of top layer silicon and substrate silicon are chosen according to demand, and BOX layer can also To select according to demand;SOI piece can be prepared using common process, can also be bought according to demand;

(4) to the dense H of SOI piece in step (3)2SO4It is surface-treated (in 120 DEG C of progress 1-5min processing);

(5) it is bonded: by step (2) silicon wafer that treated with oxide layer and step (4) treated SOI piece in room temperature Lower bonding (oxide layer of silicon wafer and the top layer silicon of SOI piece fit), then carries out low-temperature annealing, and 300 DEG C -500 of annealing temperature DEG C, that is, obtain the SOI material of 2 layers of structure.

(6) two layers of SOI material (3 layers of silicon layer, intermediate 2 layers of BOX layer) after bonding is carried out thinned, thinned thickness can be with It is customized according to demand;With dense H after being thinned2SO4In 120 DEG C of progress 1-5min surface treatments;The SOI piece in step (3) is taken to carry out Oxidation, prepares oxide layer (BOX layer as SOI) on the surface thereof, then first carries out CMP destressing to the oxide layer of the preparation Processing, then carries out 1-5min surface treatment with DHF, then carry out plasma-activated processing;By two layers of SOI material with prepare it is aerobic The SOI piece for changing layer is bonded at normal temperature, then carries out low-temperature annealing, and 300 DEG C -500 DEG C of annealing temperature;

(7) technical process of step (6) is repeated, until the SOI material of the number of plies needed for obtaining.

In above-mentioned steps, dense H2SO4The temperature being surface-treated is 120 DEG C, time 1-5min;At plasma-activated Manage technological parameter are as follows: use N2, gas pressure 0.1-1.0mbar, activationary time 1-10s, radio-frequency power 55-120W.

Design principle of the invention is as follows:

During the present invention prepares multilayer SOI material, pass through the method removal oxidation piece of CMP (chemically mechanical polishing) The stress of (there is oxide layer on surface) stacks the bonding of multilayer SOI up.Surface is oxidation piece at CMP destressing 1-5min surface treatment is carried out with HF after reason, and plasma-activated is handled;Surface is silicon wafer with dense H2SO4Carry out 1-5min Surface treatment, but handled without plasma-activated.It has handled in this way and has carried out normal temperature bonding again, it can be with less than 500 DEG C Temperature low-temperature annealing, and extraordinary bonding quality is obtained, edge loses in subsequent thinning process can be less than 0.5mm.It is whole A bonding process is completed in low temperature, and defect will not be generated by so that the device layer of multilayer SOI is not passed through high temperature.

It advantages of the present invention and has the beneficial effect that:

1. the present invention can manufacture N layers of SOI material (3 < N < 15), every layer of device layer silicon wafer can to, resistivity and thickness With customized according to demand, oxidated layer thickness can be customized according to demand in each soi layer.

2. multilayer SOI device silicon layer of the present invention does not pass through the process of high temperature, defect will not be generated.

3. edge penalty is small, can retain the device layer of large area in multilayer SOI material preparation process of the present invention.

Detailed description of the invention

Fig. 1 is 1 process flow chart of embodiment.

Fig. 2 is multilayer SOI material photo prepared by embodiment 1.

Fig. 3 is multilayer SOI material SAM photo prepared by embodiment 1.

Fig. 4 is multilayer SOI material SAM photo prepared by comparative example 1.

Fig. 5 is the edge photo of the SOI piece after step (4) are thinned in embodiment 1.

Fig. 6 is the edge photo of the SOI piece after step (4) are thinned in comparative example 3.

Specific embodiment

The present invention is described in detail with reference to the accompanying drawings and embodiments.

Embodiment 1:

The present embodiment is the preparation of 6 cun of 3 layers of SOI materials, and process is following (Fig. 1):

(1) a piece of 6 cun, N-type, resistivity 4-7ohm.cm, crystal orientation<100>silicon wafer are taken, is thinned to 400 μm.Then oxygen is carried out Change, 0.5 μm of oxide layer.

(2) select a piece of 6 cun of SOI: top layer silicon thickness is 10 μm, N-type, resistivity 8-12ohm.cm, crystal orientation<100>;In Between oxide layer silica be 0.5 μm;Substrate silicon thickness is 675 μm, N-type, resistivity 8-12ohm.cm, crystal orientation<100>.

(3) CMP destressing processing (the processing time 180 seconds, polishing pressure are first carried out to the oxide layer on silicon wafer in step (1) Power 20KPa), 3min surface treatment then is carried out with DHF, then carry out plasma-activated (using N2, gas pressure 0.3mbar, swash Live time 5s, radio-frequency power 75W).To the SOI piece of step (2) with dense H2SO4In 120 DEG C of processing 3min, swash without plasma It is living;Again by silicon wafer and SOI piece progress normal temperature bonding with oxide layer;Carry out low-temperature annealing after bonding, 350 DEG C of annealing temperature, Obtain two layers of compound SOI piece.

(4) 2 layers of SOI (3 layers of silicon layer, intermediate 2 layers of BOX layer) after step (3) bonding are carried out thinned, top layer is thinned to 10 μm。

(5) a piece of 6 cun of oxidation pieces (silicon wafer that there is oxide layer on surface) are selected, oxidated layer thickness is 0.5 μm, silicon wafer p-type, resistance Rate 15-25ohm.cm, crystal orientation<100>.

(6) destressing processing (the processing time 180 seconds, polish pressure are carried out by CMP method to the oxidation piece of step (5) 20KPa), 5min surface treatment then is carried out with DHF, then carries out plasma-activated processing (using N2, gas pressure 0.3mbar, Activationary time 5s, radio-frequency power 75W).Two layers of the SOI piece obtained to step (4) is with dense H2SO4In 120 DEG C of processing 5min;Again will It aoxidizes piece and two layers of SOI piece carries out normal temperature bonding.Low-temperature annealing is carried out, 400 DEG C of annealing temperature, obtains three layers of SOI piece.

(7) 3 layers of SOI (4 layers of silicon layer, intermediate 3 layers of BOX layer) after step (6) bonding are carried out thinned, top layer is thinned to 10 μm。

It is manufactured that a piece of 6 cun of 3 layers of SOI through the above steps, Fig. 2 is the multilayer photo after finishing SEM, and Fig. 3 is final SAM photo after bonding.

Comparative example 1

Difference from Example 1 is: in step (3), is handled without CMP destressing oxidation piece.

As a result: since stress is bigger after final bonding, bonding effect is not very well, to have many cavities, such as Fig. 4 institute Show.

Comparative example 2

Difference from Example 1 is: in step (3), to oxidation piece progress CMP destressing processing, the processing time is 400 seconds.

As a result: oxidation piece handles overlong time, larger to oxide layer damage, can not be bonded.

Comparative example 3

Difference from Example 1 is: using in step (3), before bonding to the oxide layer on silicon wafer, SOI piece conventional Hydrophilic treatment method, i.e. elder generation SC1 processing, then SC2 processing.

As a result: it is not very regular that back edge, which is thinned, by step (4), it is necessary to can just obtain relatively good edge by chamfering Quality, edge penalty is in 1.5-2mm.Fig. 5 is the edge photo of example 1, and Fig. 6 is the edge photo of comparative example 3.

Claims (7)

1. a kind of preparation method of multilayer SOI material, it is characterised in that: the material is multilayer SOI stacked structure, in which: the heap The topsheet surface and bottom surface of stack structure are silicon wafer, and middle section is that silicon wafer and BOX layer are arranged alternately mode;The multilayer The preparation method of SOI material, includes the following steps:
(1) silicon wafer for choosing 6 cun or 8 cun, after being thinned to required thickness, is aoxidized on one side or double-sided surface, is prepared Silicon wafer with silica oxide layer;
(2) silicon wafer with oxide layer prepared by step (1) is first subjected to CMP destressing processing, then carries out 1-5min with DHF Surface treatment, then carry out plasma-activated processing;
(3) prepare a SOI piece, the resistivity and crystal orientation of top layer silicon and substrate silicon are chosen according to demand, and BOX layer is according to demand Selection;
(4) to the dense H of SOI piece in step (3)2SO4It is surface-treated;
(5) it is bonded: by step (2) silicon wafer that treated with oxide layer and step (4) treated SOI piece key at normal temperature It closes, anneals under the conditions of then carrying out 300 DEG C -500 DEG C, that is, obtain the SOI material of 2 layers of structure;
(6) two layers of SOI material after bonding is carried out it is thinned, with dense H after being thinned2SO4It is surface-treated;It takes in step (3) SOI piece is aoxidized, and prepares silica oxide layer on the surface thereof, and CMP destressing processing is then first carried out to the oxide layer, Then 1-5min surface treatment is carried out with DHF, then carries out plasma-activated processing;By dense H2SO4Treated two layers of SOI material It is bonded at normal temperature with the SOI piece for being prepared with oxide layer, low-temperature annealing under the conditions of then carrying out 300 DEG C -500 DEG C;
(7) technical process of step (6) is repeated, until the SOI material of the number of plies needed for obtaining.
2. the preparation method of multilayer SOI material according to claim 1, it is characterised in that: the crystal orientation of the silicon wafer selects For<100>or<111>, resistivity, which is selected as, is heavily doped to high resistant.
3. the preparation method of multilayer SOI material according to claim 1, it is characterised in that: the BOX layer is titanium dioxide Silicon.
4. the preparation method of multilayer SOI material according to claim 1 or 3, it is characterised in that: the BOX layer with a thickness of 20nm~2 μm, multilayer SOI is with a thickness of 1 μm~500 μm.
5. the preparation method of multilayer SOI material according to claim 1, it is characterised in that: soi layer number is in the material 3~15.
6. the preparation method of multilayer SOI material according to claim 1, it is characterised in that: in step (2) and step (6), The CMP destressing treatment process parameter are as follows: the processing time -200 seconds 150 seconds, pressure 10KPa-35KPa.
7. the preparation method of multilayer SOI material according to claim 1, it is characterised in that: in step (4) and step (6), Dense H2SO4The temperature being surface-treated is 120 DEG C, time 1-5min;Plasma-activated treatment process parameter are as follows: use N2, Gas pressure 0.1-1.0mbar, activationary time 1-10s, radio-frequency power 55-120W.
CN201510460906.6A 2015-07-30 2015-07-30 A kind of multilayer SOI material and preparation method thereof CN106409649B (en)

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CN110085510A (en) 2018-01-26 2019-08-02 沈阳硅基科技有限公司 A kind of preparation method of multilayer monocrystalline silicon thin film

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1241803A (en) * 1998-05-15 2000-01-19 佳能株式会社 Process for manufacturing semiconductor substrate as well as semiconductor thin film and multilayer structure
CN1269599A (en) * 1999-03-26 2000-10-11 佳能株式会社 Method for producing semiconductor device
CN1332478A (en) * 2001-08-24 2002-01-23 中国科学院上海冶金研究所 Multilayer silicon gallide material on insulating layer and its prepn
CN101110428A (en) * 2007-07-11 2008-01-23 中国科学院上海微系统与信息技术研究所 Multi-layer insulator silicon material used for MEMS and method thereof
JP5124931B2 (en) * 2005-10-14 2013-01-23 信越半導体株式会社 Multilayer SOI wafer manufacturing method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173568A (en) * 2004-12-14 2006-06-29 Korea Electronics Telecommun Method of manufacturing soi substrate
US9768056B2 (en) * 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1241803A (en) * 1998-05-15 2000-01-19 佳能株式会社 Process for manufacturing semiconductor substrate as well as semiconductor thin film and multilayer structure
CN1269599A (en) * 1999-03-26 2000-10-11 佳能株式会社 Method for producing semiconductor device
CN1332478A (en) * 2001-08-24 2002-01-23 中国科学院上海冶金研究所 Multilayer silicon gallide material on insulating layer and its prepn
JP5124931B2 (en) * 2005-10-14 2013-01-23 信越半導体株式会社 Multilayer SOI wafer manufacturing method
CN101110428A (en) * 2007-07-11 2008-01-23 中国科学院上海微系统与信息技术研究所 Multi-layer insulator silicon material used for MEMS and method thereof

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