CN113793833A - Preparation process of silicon-on-insulator substrate with cavity - Google Patents
Preparation process of silicon-on-insulator substrate with cavity Download PDFInfo
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- CN113793833A CN113793833A CN202110923649.0A CN202110923649A CN113793833A CN 113793833 A CN113793833 A CN 113793833A CN 202110923649 A CN202110923649 A CN 202110923649A CN 113793833 A CN113793833 A CN 113793833A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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Abstract
The invention relates to a preparation process of a silicon substrate on an insulator with a cavity, which comprises the steps of preparing a silicon epitaxial wafer as a silicon substrate of a device layer, preparing a silicon oxide wafer with a patterned cavity as a supporting silicon substrate, respectively carrying out plasma surface activation treatment, carrying out low-temperature annealing after bonding in a vacuum environment, removing most of the silicon substrate of the device layer by adopting a mechanical grinding thinning mode, removing the silicon substrate with the thickness of 20-50 um reserved after mechanical grinding by utilizing selective acid corrosion, carrying out CMP polishing treatment to reach target roughness, then carrying out high-temperature oxidation thinning treatment, and finally removing silicon oxide grown by high-temperature oxidation by diluted hydrofluoric acid corrosion to achieve the purpose of accurately adjusting the thickness of the target device layer. The invention obtains the silicon-on-insulator substrate material with the cavity, which has relatively thin device layer thickness (<10um) and excellent uniformity on the premise of maintaining the integrity of the device silicon layer on the cavity structure.
Description
Technical Field
The invention relates to a preparation method of an integrated circuit material, in particular to a preparation process of a silicon-on-insulator substrate with a cavity.
Background
Silicon-On-Insulator (SOI) is a buried oxide layer introduced as an insulating layer between the top device Silicon and the supporting substrate. Silicon-on-insulator materials have incomparable advantages over bulk silicon: the device can realize the physical complete isolation of the elements in the integrated circuit, and thoroughly eliminate the parasitic latch-up effect in a bulk silicon CMOS circuit; the parasitic capacitance is reduced, and the method has obvious advantages in the aspects of power consumption, operation speed, radiation resistance and device integration level.
The application of SOI material in MEMS (micro electro mechanical system) is also more and more extensive; with the development of the MEMS technology, the silicon-on-insulator substrate material with cavity patterned cavities is increasingly applied to MEMS devices such as pressure sensors, gyroscopes, microphones, ultrasonic probes, and the like. When a BESOI bonding thinning technology is adopted to prepare a silicon-on-insulator SOI material with a cavity, a photoetching and etching process is carried out on a substrate silicon wafer used as a support before bonding, and some graphical structural cavities are formed on the surface of the support silicon, the sizes of the cavities are different from several micrometers to hundreds of micrometers, and the depths of the cavities are also different from several micrometers to hundreds of micrometers. Because of the existence of the cavities, the contact area between the support substrate and the device silicon substrate is greatly reduced in the process of preparing the silicon-on-insulator substrate, and the device silicon on the upper part of the cavity area is in a suspended state only by bonding some side wall silicon of the non-pattern cavity area and the device silicon substrate together. When thinning is carried out after bonding, the device silicon in a suspension state is easily damaged by the stress in the mechanical grinding process, and the sensor pressure rod for monitoring the thickness in real time in the grinding equipment is damaged under pressing, so that the damage cannot be repaired, and the device silicon layer and the whole silicon wafer are seriously and directly abraded. These damages are all the more severe as the device layer thickness is thinner during the thinning process by mechanical grinding. Generally, when the thickness of a device silicon layer is less than 10um, the device layer is very easily damaged by mechanical grinding, so that when a silicon-on-insulator substrate with a cavity is prepared by a conventional BESOI bonding thinning process, the limitation of 10 μm of the device layer is difficult to break through, and due to the inherent limitation of polishing process capability, the good uniformity of the thickness of the device layer cannot be ensured; therefore, for silicon-on-insulator substrates with cavities of some thin-film device layers, a new preparation process is required. Meanwhile, if the bonding process is carried out under normal pressure, air can be wrapped in the cavity, and in the subsequent high-temperature heat treatment process, the air can expand and stretch the bonding interface to influence the bonding strength, so that the device layer silicon on the upper part of the cavity is damaged more seriously, and the device fails.
Aiming at a silicon-on-insulator substrate with a cavity, a preparation process of a silicon-on-insulator material of a thin film device layer with the cavity suitable for a support is developed based on an epitaxial process and a vacuum bonding process and combined with a selective corrosion and polishing and oxidation thinning process, and the requirement that the thickness of the device layer is smaller than 10 microns can be met.
Disclosure of Invention
The invention aims to provide a preparation process of a silicon-on-insulator substrate with a cavity, which is characterized in that on the basis of a conventional BESOI bonding thinning process, aiming at a special structure of a support substrate with a graphical cavity, through plasma activation treatment before bonding and two-step heat treatment after bonding, the first-step low-temperature annealing can ensure that the silicon substrate subjected to plasma surface activation treatment has enough bonding strength to cope with the subsequent thinning process, and the second-step high-temperature oxidation treatment after thinning is carried out not only improves the bonding strength, but also can realize accurate thickness control; reserving enough thickness in the thinning process of mechanical grinding to prevent the damage of device layer silicon on the cavity structure, and then carrying out surface treatment by combining CMP polishing and high-temperature oxidation thinning process; thus, an epitaxial layer as a device layer is transferred onto a support substrate with a patterned cavity in a layer transfer manner, and a silicon-on-insulator substrate material with a cavity, which has a relatively thin (<10um) device layer, is obtained.
The invention realizes the purpose through the following technical scheme: a preparation process of a silicon substrate with an insulating buried layer comprises the following steps:
s101, providing a monocrystalline silicon substrate, wherein the front surface is a polished surface;
s102, growing a layer of lightly doped monocrystalline epitaxial silicon layer on the surface of the monocrystalline silicon substrate;
s103, providing the monocrystalline silicon substrate with the patterned cavity as a support substrate;
s104, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s105, respectively carrying out plasma surface activation treatment on the surface of the epitaxial layer of the monocrystalline silicon substrate and the surface of the support substrate with the patterned cavity as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together in a vacuum environment at normal temperature to form a bonded substrate;
s106, placing the bonded substrate into a furnace tube for low-temperature annealing;
s107, removing most of substrate monocrystalline silicon by thinning the bonded substrate in a mechanical grinding mode, and removing the rest substrate monocrystalline silicon through a subsequent process;
s108, performing acid corrosion on the thinned bonding substrate, spraying a mixed corrosion solution of hydrofluoric acid, nitric acid and acetic acid on the rotating bonding substrate, preferentially corroding the monocrystalline substrate silicon, and stopping on an epitaxial interface, so as to ensure that the monocrystalline substrate reserved after mechanical grinding is completely removed;
s109, carrying out chemical mechanical polishing on the corroded bonded substrate to obtain the required surface roughness;
s110, performing high-temperature thermal oxidation on the polished bonding substrate to further improve the bonding strength;
and S111, carrying out chemical corrosion of single-wafer type rotary spraying hydrofluoric acid on the oxidized bonding substrate, and removing the surface silicon dioxide layer.
Further, the S101 monocrystalline silicon substrate is a Czochralski CZ monocrystalline polished silicon wafer, the front surface of the silicon substrate is a polished surface, and the resistivity is less than 0.01ohm.
Further, a layer of lightly doped monocrystalline epitaxial silicon layer grows on the surface of the monocrystalline silicon substrate in the S102 mode, and the resistivity is larger than 1 ohm.cm; the epitaxial thickness is greater than 2 um.
Further, the step S103 provides a support substrate with a patterned cavity, and the patterned cavity structure is completed through a photolithography and etching process.
Further, the S104 supporting substrate is subjected to thermal oxidation, silicon dioxide is grown to serve as an insulating layer, and the thickness of the silicon dioxide is larger than 0.1 um;
further, in the step S105, after plasma surface activation processing is respectively performed on the epitaxial layer surface of the monocrystalline silicon substrate and the surface of the supporting substrate surface having the patterned cavity, the monocrystalline silicon substrate and the supporting substrate are bonded together in a vacuum environment at normal temperature to form a bonded substrate, mixed gas of N2, O2 or N2/O2 is used for plasma surface activation, the bonding temperature is normal temperature, the bonding chamber is in a vacuum environment, and the vacuum pressure is less than 10 mBar;
further, the low-temperature annealing temperature of S106 is not more than 400 ℃, and the annealing time is more than 1 hour.
Furthermore, the mechanical grinding thinning mode of S107 is a combination mode of coarse grinding (the number of grinding wheels is less than 800#) and fine grinding (the number of grinding wheels is greater than 3000#), the grinding process is monitored by adopting a non-contact thickness test, and the thickness of the top silicon reserved after grinding is 20-50 um.
Further, the acid etching of S108 is selective etching of a single-wafer spin-on etching solution, and etching a mixed solution of HF, HNO3 and acetic acid; the corrosion rate is 2-5 um/min;
further, the CMP polishing removal amount in S109 is less than 2 um.
Further, in the step S110, the high-temperature thermal oxidation is performed, wherein the process temperature is greater than 1000 ℃, and the time is greater than 2 hours.
Further, the chemical etching of S111 adopts rotary single-chip etching, the concentration of HF solution is less than 10%, and the over etching amount is not more than 30%.
Compared with the prior art, the invention has the beneficial effects that: the limitation that the conventional bonding and thinning process can only prepare the silicon-on-insulator substrate material with the cavity, the thickness of which is more than 10um, of the device layer is larger than 10um is broken through, the plasma surface activation treatment and the low-temperature annealing process are comprehensively applied to ensure the bonding strength to deal with the subsequent thinning process, the thinning process combines the mode that mechanical grinding is used for carrying out large-removal-amount thinning and selective chemical corrosion is used for stopping at the interface between the epitaxial layer and the substrate silicon, the epitaxial layer with the thinner thickness is transferred to the supporting substrate with the patterned cavity, finally, the bonding strength is improved through the high-temperature oxidation process, and the thickness of the silicon layer of the top device is accurately controlled in the mode of oxidation thinning, so that the silicon-on-insulator substrate material with the cavity, the thickness of the device layer is smaller than 10um, is prepared.
Drawings
FIG. 1 is a flow chart of the steps performed in accordance with an embodiment of the present invention.
Fig. 2 is a schematic diagram of the product state of step S101 and step S102.
Fig. 3 is a schematic diagram of the product state of step S103 and step S104.
Fig. 4 is a schematic diagram of the product status of step S105 and step 106.
Fig. 5 is a schematic diagram of the product status in step S107.
Fig. 6 is a schematic diagram of the product status of step S108.
Fig. 7 is a schematic diagram of the product state in step S109.
Fig. 8 is a schematic diagram of the product status of step S110.
Fig. 9 is a schematic diagram of the product state of step S111.
Detailed Description
The following describes in detail a specific embodiment of a method for manufacturing a silicon substrate with a buried insulating layer according to the present invention with reference to the accompanying drawings.
Fig. 1 is a flowchart illustrating implementation steps of this embodiment, and a process for manufacturing a silicon substrate with a buried insulating layer includes the following steps:
s101, providing a monocrystalline silicon substrate, wherein the front surface is a polished surface;
s102, growing a layer of lightly doped monocrystalline epitaxial silicon layer on the surface of the monocrystalline silicon substrate;
s103, providing a support substrate with a patterned cavity;
s104, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s105, respectively carrying out plasma surface activation treatment on the surface of the epitaxial layer of the monocrystalline silicon substrate and the surface of the support substrate with the patterned cavity as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together in a vacuum environment at normal temperature to form a bonded substrate;
s106, placing the bonded substrate into a furnace tube for low-temperature annealing;
s107, the bonded substrate is thinned by mechanical grinding, non-contact thickness monitoring is adopted by thinning process equipment, most of substrate monocrystalline silicon is removed, and the rest of substrate monocrystalline silicon is removed by a subsequent process;
s108, performing acid corrosion on the thinned bonding substrate, spraying a mixed corrosion solution of hydrofluoric acid, nitric acid and acetic acid on the rotating bonding substrate, preferentially corroding the monocrystalline substrate silicon, and stopping on an epitaxial interface, so as to ensure that the monocrystalline substrate reserved after mechanical grinding is completely removed;
s109, carrying out chemical mechanical polishing on the corroded bonded substrate to obtain the required surface roughness;
s110, performing high-temperature thermal oxidation on the polished bonding substrate to further improve the bonding strength;
and S111, carrying out chemical corrosion of single-wafer type rotary spraying hydrofluoric acid on the oxidized bonding substrate, and removing the surface silicon dioxide layer.
Referring to step S101 and step S102, as shown in fig. 2, a single crystal silicon substrate 100 is provided, wherein a resistivity R1 of the single crystal silicon substrate 100 is less than 0.01 ohm-cm, and a single crystal silicon epitaxial layer 110 is epitaxially grown, wherein the resistivity R2 is greater than 1 ohm-cm.
As shown in fig. 3, referring to steps S103 and S104, providing a monocrystalline silicon support substrate 200, where the front surface of the support substrate 200 is a polished surface, and forming a patterned structure with a cavity through photolithography and etching processes; thermal oxidation is then performed to form a thermal oxide layer 210 on the surface of the supporting substrate, which will serve as an insulating layer for the final bonded substrate material. The thickness of the silicon dioxide is preferably 0.5-1 um.
As shown in fig. 4, referring to steps S105 and S106, plasma surface activation is performed on the surface of the insulating layer 210 of the supporting substrate and the surface of the single crystal substrate silicon layer 100, respectively, and then the two surfaces are bonded together at normal temperature to complete bonding, forming a bonded substrate. Preferably, the plasma treatment is performed in a vacuum chamber using N2 as a gas source.
Because the surface before bonding has been subjected to plasma activation in step S105, a sufficiently strong bonding strength can be achieved only by one low-temperature annealing; the annealing atmosphere may be nitrogen, oxygen, or other inert gas. The annealing time is more than 2 hours. The annealing temperature is lower than 400 ℃, so that the requirement of the subsequent thinning process on the bonding strength can be met. The annealing temperature is preferably 300 ℃ and the annealing time is preferably 3 hours.
Referring to step S107 in fig. 5, the thickness of the single crystal substrate 100 is thinned to a reserved thickness of 20-50 um by using a mechanical grinding thinning method; the preferred reserved thickness is 20-30 um.
Fig. 6 shows that, with reference to step S108, the bonded substrate slice after mechanical grinding is subjected to acid etching to remove the single crystal substrate 100 reserved in the mechanical grinding process by using a rotary single-wafer etching process; the acid etch will automatically stop at the epitaxial layer interface, leaving the epitaxial layer 110.
Referring to step S109 in fig. 7, CMP polishing is performed on the etched bonded substrate, and the removal amount by polishing is not more than 2um, which not only meets the requirement of completely removing the transition region of the epitaxial layer, but also meets the requirements of surface roughness and flatness. The removal amount is preferably 1-1.5 um.
Referring to step S110 in fig. 8, a high-temperature oxidation process is performed on the polished bonded substrate, the temperature of the oxidation process is not lower than 1000 ℃, and the annealing time is not lower than 2 hours, in this step, the bonding strength can be further improved, and a part of device layer silicon can be converted into silicon oxide by oxidation to be removed, so that the thickness of the device layer silicon can be indirectly precisely adjusted. The high-temperature oxidation temperature is preferably 1150 ℃, and the oxidation process time is preferably 2 hours.
Fig. 9 referring to step S111, the bonded substrate after the high temperature oxidation is subjected to a rotary single-wafer HF etching to remove the oxide layer on the surface without affecting the thickness of the back oxide layer. The preferred HF concentration is 5% to 10%.
The invention breaks the limitation that the prior conventional bonding and thinning process can only prepare the silicon substrate material on the insulator with the cavity, the device layer of which is more than 10um, by means of layer transfer, plasma surface activation treatment and low-temperature annealing process are comprehensively applied to ensure bonding strength to deal with the subsequent thinning process, the thinning process firstly adopts mechanical grinding to thin with large removal amount, meanwhile, enough thickness is reserved to prevent the top silicon device layer from being damaged in the grinding process, then, the epitaxial layer with thinner thickness is transferred to the supporting substrate with the patterned cavity in a mode of stopping the interface between the epitaxial layer and the substrate silicon by selective chemical etching, finally, the bonding strength is improved by a high-temperature oxidation process, the thickness of the top device silicon layer is accurately controlled in an oxidation thinning mode, thereby preparing the silicon-on-insulator substrate material with the cavity, the thickness of the device layer of which is less than 10 um. .
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and adjustments can be made without departing from the principle of the present invention, and these modifications and adjustments should also be regarded as the protection scope of the present invention.
Claims (10)
1. A preparation process of a silicon-on-insulator substrate with a cavity is characterized by comprising the following steps:
s101, providing a monocrystalline silicon substrate, wherein the front surface is a polished surface;
s102, growing a layer of lightly doped monocrystalline epitaxial silicon layer on the surface of the monocrystalline silicon substrate;
s103, providing the monocrystalline silicon substrate with the patterned cavity as a support substrate;
s104, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s105, respectively carrying out plasma surface activation treatment on the surface of the epitaxial layer of the monocrystalline silicon substrate and the surface of the support substrate with the patterned cavity as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together in a vacuum environment at normal temperature to form a bonded substrate;
s106, placing the bonded substrate into a furnace tube for low-temperature annealing;
s107, the bonded substrate is thinned by mechanical grinding, non-contact thickness monitoring is adopted by thinning process equipment, most of substrate monocrystalline silicon is removed, and the rest of substrate monocrystalline silicon is removed by a subsequent process;
s108, performing acid corrosion on the thinned bonding substrate, spraying a mixed corrosion solution of hydrofluoric acid, nitric acid and acetic acid on the rotating bonding substrate, preferentially corroding the monocrystalline substrate silicon, and stopping on an epitaxial interface, so as to ensure that the monocrystalline substrate reserved after mechanical grinding is completely removed;
s109, carrying out chemical mechanical polishing on the corroded bonded substrate to obtain the required surface roughness;
s110, performing high-temperature thermal oxidation on the polished bonding substrate to further improve the bonding strength;
and S111, carrying out chemical corrosion of single-wafer type rotary spraying hydrofluoric acid on the oxidized bonding substrate, and removing the surface silicon dioxide layer.
2. The process for preparing a silicon substrate on a thin film device layer insulator with a cavity according to claim 1, wherein: the S101 monocrystalline silicon substrate is a heavily doped substrate and has the resistivity of R1.
3. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: the S102 epitaxial silicon layer and the monocrystalline silicon substrate have the same doping type, the resistivity of the epitaxial silicon layer is R2, and R2/R1> 500.
4. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: the thickness of the silicon dioxide of the S104 is 0.1-2 um.
5. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: the annealing temperature of S106 is not more than 400 ℃, and the annealing time is more than 1 hour.
6. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: and the reserved thickness of the silicon substrate in the S107 is 20-50 um.
7. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: and in the S108, single-chip rotary corrosion is adopted, the corrosion removal rate is 2-5 um/min, and the excessive corrosion amount is not more than 30%.
8. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: the polishing removal amount in S109 is not more than 2 um.
9. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: and in the S110, the oxidation temperature is not lower than 1000 ℃, and the oxidation time is not lower than 2 hours.
10. The process for preparing a silicon-on-insulator substrate with a cavity according to claim 1, wherein: in S111, single-chip rotary HF chemical etching is adopted, the concentration of HF is not more than 10%, and the removal amount of HF etching silicon oxide is not more than 30%.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024083267A1 (en) * | 2022-10-21 | 2024-04-25 | 广州乐仪投资有限公司 | Preparation method for semiconductor structure, semiconductor structure, and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521807A (en) * | 2003-02-11 | 2004-08-18 | 厦门大学 | Silicon-silicon vacuum bonding apparatus and method thereof |
| CN103400797A (en) * | 2013-08-15 | 2013-11-20 | 上海新傲科技股份有限公司 | Preparation method of semiconductor substrate with cavity |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521807A (en) * | 2003-02-11 | 2004-08-18 | 厦门大学 | Silicon-silicon vacuum bonding apparatus and method thereof |
| CN103400797A (en) * | 2013-08-15 | 2013-11-20 | 上海新傲科技股份有限公司 | Preparation method of semiconductor substrate with cavity |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024083267A1 (en) * | 2022-10-21 | 2024-04-25 | 广州乐仪投资有限公司 | Preparation method for semiconductor structure, semiconductor structure, and electronic device |
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Application publication date: 20211214 |