JP3584945B2 - Method for manufacturing SOI substrate - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a method for manufacturing an SOI ( Silicon-On-Insulator ) substrate in which two silicon wafers are bonded via an insulating layer to form a silicon layer (hereinafter referred to as an SOI layer) on the insulating layer. .
[0002]
[Prior art]
In recent years, highly integrated CMOS (Complementary Metal Oxide Semiconductor), ICs, high withstand voltage elements, and the like have been manufactured using an SOI substrate. An SOI substrate in which a single-crystal silicon layer used as a device fabrication region is formed on an insulating layer prevents latch-up (abnormal oscillation phenomenon due to a parasitic circuit) in the case of a highly integrated CMOS, and in the case of a high breakdown voltage element. Are effective for insulating and separating from the base substrate. This SOI substrate manufacturing method includes a method in which silicon wafers are bonded to each other via a silicon dioxide layer (hereinafter, referred to as a silicon oxide layer), that is, an insulating layer, on an insulating substrate or a substrate having an insulating thin film on its surface. First, a polycrystalline silicon thin film is deposited by a CVD (Chemical Vapor Deposition) method, then a single crystal is formed by laser annealing, a ZMR method is performed, high-concentration oxygen ions are implanted into a silicon substrate, and annealing is performed at a high temperature. There is a SIMOX method in which a buried silicon oxide layer (insulating layer) is formed in a region at a predetermined depth from the substrate surface, and the silicon layer on the surface side is used as an active region. Among these methods, an SOI substrate manufactured by a bonding method is promising because the SOI layer has extremely good crystallinity.
[0003]
Specifically, this silicon wafer bonding method involves bonding two silicon wafers each having a thickness of about 600 μm via an insulating layer made of a silicon oxide layer, and performing a heat treatment at 1100 ° C. for 2 hours in an oxygen atmosphere. The surface of one of the silicon wafers is ground with a grindstone and further polished with a polishing cloth so that the thickness of the silicon wafer is in the range of about 1 to 10 μm, and the thickness of the polished side is about 1 to 10 μm Are used as SOI layers for device formation.
[0004]
[Problems to be solved by the invention]
However, in the conventional method, when heat treatment is performed at 1100 ° C. for 2 hours, stress is applied to the bonding interface due to a difference in thermal expansion coefficient of the order of one digit between the silicon wafer (Si) and the silicon oxide layer (SiO ₂ ). Is concentrated. When unbonded portions (voids) between wafers are formed at the bonding interface, dislocations (slips) penetrating from the voids to the SOI layer surface or the interface with the buried SiO ₂ film from the voids in the SOI layer due to the stress concentration. Easily occur. Since the density of the conventional slip line is as large as about 5.0 × 10 ⁷ cm / cm ^{3, in the} SOI layer having such a high slip line density, these dislocations directly affect the electrical characteristics of the device after the device is formed. Or it could have a large effect indirectly.
An object of the present invention has a small density of slip lines in the SOI layer on an insulator layer made by bonding two silicon wafers, a manufacturing method of the SOI base plate that does not adversely affect the electrical characteristics of the device due to slippage Is to provide.
[0005]
[Means for Solving the Problems]
[0006]
As shown in FIGS. 1A to 1E, the present invention provides a step of bonding a first silicon wafer 11 and a second silicon wafer 12 via an insulating layer 13, and a method of bonding the first and second silicon wafers. a step of Ru bonding by heat-treating silicon wafers 11 and 12, the steps of the SOI layer 12a of the device formed by grinding and polishing the first silicon wafer 11 and the second silicon wafer 12 to a predetermined thickness, the grinding After polishing, a heat treatment again in a dry oxygen atmosphere or a nitrogen atmosphere in a temperature range of 1200 to 1300 ° C., preferably at 1250 ° C. for at least 10 hours , wherein each step is continuously performed. This is a method for manufacturing an SOI substrate.
[0007]
The first and second silicon wafers of the present invention are manufactured from a silicon single crystal rod obtained by the same method using a CZ method, an FZ method or the like. The insulating layer is formed on one or both of the first silicon wafer and the second silicon wafer. In order to improve the bonding, the insulating layer is preferably formed on one surface of one of the silicon wafers. As shown in FIG. 1A, an insulating layer 13 is formed on one surface of a second silicon wafer 12 in the figure. As the interface between the insulating layer and the SOI layer after the bonding, the interface between the two silicon wafers (the interface with the silicon wafer 11 in FIG. 1) and the interface between the silicon wafer on which the insulating layer was formed before the bonding (FIG. 1 has an interface with the silicon wafer 12).
It is preferable that the interface between the SOI layer 12a and the insulating layer 13 of the present invention be the interface with the wafer on which the insulating layer is formed, rather than the former bonding interface, because the interface is more excellent in continuity. That is, as shown in FIG. 1E, it is preferable that the silicon wafer 12 on which the SOI layer 12a is formed be used as a silicon substrate for the SOI layer and another silicon wafer 11 be used as its supporting substrate.
[0008]
The thickness of the insulating layer is in the range of about 0.5 to 1.0 μm, and the insulating layer is a silicon oxide layer (SiO ₂ layer), which is obtained by thermally oxidizing a silicon wafer or by CVD. Formed. Before bonding the two silicon wafers via the insulating layer as shown in FIG. 1B, it is preferable to clean the silicon wafers with a predetermined cleaning liquid in order to activate the surface to be bonded. As shown in FIG. 1C, the heat treatment after the bonding is performed at a temperature of 1100 ° C. in a dry oxygen (dry O ₂ ) atmosphere or a nitrogen (N ₂ ) atmosphere in a state where the two silicon wafers 11 and 12 are bonded. , 1 to 3 hours, preferably about 2 hours. As a result, covalent bonding of silicon occurs at the bonding interface, and the two silicon wafers 11 and 12 are bonded to each other, and the crystal lattices of the two are integrated.
As shown in FIG. 1 (d), after the two integrated silicon wafers 11 and 12 are allowed to cool to room temperature, the second silicon wafer 12 serving as the silicon substrate is ground with a grindstone and then with a polishing cloth. It is polished and processed into a thin film having a thickness of about 1 to 10 μm. As a result, an SOI layer 12 a for device formation having a thickness of about 1 to 10 μm is obtained on the insulating layer 13. After grinding and polishing as shown in FIG. 1 (e), at a temperature range of 1200 to 1300 ° C., preferably at a temperature of 1250 ° C. for at least 10 hours in a dry oxygen (dry O ₂ ) atmosphere or a nitrogen (N ₂ ) atmosphere. Performs a reheat treatment for about 10 to 15 hours. If the reheat treatment is performed at less than 1200 ° C. or for less than 10 hours, the disappearance of the slip is not so remarkable. If the reheat treatment is performed at more than 1300 ° C., adverse effects such as deformation of the core tube of the heat treatment furnace occur.
[0009]
[Action]
As described above, when heat treatment is performed at 1100 ° C. for 2 hours in FIG. 1C, the heat expansion is caused by a difference of about one digit between the silicon wafer (Si) 12 and the silicon oxide layer (SiO ₂ ) 13. When stress is concentrated at the bonding interface and an unbonded portion (void) between wafers is formed at the bonding interface, the stress concentration causes the SOI layer surface or the buried SiO 2 starting from the void in the SOI layer 12a. _It is presently believed that dislocations (slips) penetrate to the interface with the _two films. It is generally thought that this slip is formed as a result of the dislocations (mainly edge dislocations) formed by the above-mentioned stress concentration moving or growing on the {111} slip plane in the silicon single crystal with the progress of plastic deformation. This dislocation line is called a slip line.
In the present invention, as a mechanism of dislocation annihilation, when the SOI substrate obtained by grinding and polishing is heat-treated again in a temperature range of 1200 to 1300 ° C. for at least 10 hours , a large amount of atomic vacancies are generated with time with respect to the edge dislocation. Is supplied, a "jog", which is a phenomenon in which dislocation lines gradually move to an adjacent slip surface, occurs, and dislocations move to the surface of the SOI layer 12a or the interface with the embedded SiO ₂ film, and eventually. A model that disappears is conceivable.
[0010]
【Example】
Next, embodiments of the present invention will be described in detail with reference to the drawings.
<Example 1>
As shown in FIG. 1A, a first silicon wafer 11 and a second silicon wafer 12 each having a diameter of 5 inches and a thickness of 625 μm made from a silicon single crystal rod pulled by the CZ method were prepared. On one side of the second silicon wafer 12, this wafer was heat-treated at 1000 ° C. for 3 hours in a wet oxygen (wetO ₂ ) atmosphere to form an insulating layer 13 made of a 0.5 μm thick silicon oxide layer. The two silicon wafers 11 and 12 were prepared by mixing H ₂ O and an aqueous solution of H ₂ O ₂ having a specific gravity of 1.1 and an aqueous solution of NH ₄ OH having a specific gravity of 0.9 by H ₂ O: H ₂ O ₂ : NH ₄ OH = 7. : The cleaning solution of SC1 (Standard Cleaning 1) was prepared by mixing at a volume ratio of 2: 1, and the surfaces of the two silicon wafers were activated.
[0011]
As shown in FIG. 1B, two silicon wafers 11 and 12 were overlapped and joined via an insulating layer 13. Then, as shown in FIG. 1 (c), it is inserted at a rate of 10 to 15 cm / min into a heat treatment furnace set at a temperature from room temperature to 800 ° C., and a rate of 800 to 10 ° C./min in a nitrogen (N ₂ ) atmosphere. At 1100 ° C., and maintained for 2 hours. Then, the temperature was lowered at a rate of 4 ° C./min, cooled to 800 ° C., and then taken out of the furnace at room temperature at a rate of 10 to 15 cm / min. Subsequently, as shown in FIG. 1D, the surface of the silicon wafer 12 was ground with a grindstone and then polished with a soft polishing cloth to form an SOI layer 12a having a thickness of 1 to 10 μm on the insulating layer 13. Further, as shown in FIG. 1 (e), it is inserted into a heat treatment furnace set at a temperature of from room temperature to 900 ° C. at a rate of 10 to 15 cm / min, and in a dry oxygen (dryO ₂ ) atmosphere, from 900 ° C. to 10 ° C./min. When the temperature reaches 1250 ° C., the temperature is maintained for 10 hours, then the temperature is lowered at a rate of 4 ° C./min, cooled to 900 ° C., and taken out of the furnace at a rate of 10 to 15 cm / min to room temperature. Was.
[0012]
<Example 2>
Using a silicon wafer of the same lot as in Example 1, an SOI substrate was obtained by performing a reheat treatment in the same manner as in Example 1 except that the atmosphere of the reheat treatment shown in FIG. 1E was changed to a nitrogen (N ₂ ) atmosphere. Was.
[0013]
<Comparative Example 1>
Using silicon wafers of the same lot as in Example 1, an SOI substrate was obtained in the same manner as in Example 1, except that the reheat treatment shown in FIG. 1E was omitted.
[0014]
<Evaluation>
First, the SOI substrates of Example 1, Example 2, and Comparative Example 1 were washed with dilute hydrofluoric acid having a volume ratio of H ₂ O: HF = 10: 1, and the washed SOI substrates were washed with an HF solution: 0.15 mol. The SOI layer was selectively etched by dipping in an etchant of K ₂ Cr ₂ O ₇ aqueous solution = 2: 1 for 90 seconds. The SOI substrate was pulled up from the etchant, washed with pure water and dried.
In order to examine the slip state before the reheat treatment, the SOI substrate of Comparative Example 1 was observed and photographed by X-ray topography. The result is shown in FIG. As is clear from FIG. 2, a number of slip lines were found around the upper left edge of the SOI substrate.
[0015]
Further, in order to examine the dislocation generation state of the sample after the reheat treatment, the SOI layer of the SOI substrate of Example 1, Example 2, and Comparative Example 1, which was washed with pure water and dried, was observed with an optical microscope and photographed. The results are shown in FIGS. As is clear from the figure, a remarkable slip line appeared in the SOI layer of the SOI substrate of Comparative Example 1 (FIG. 3), but the slip line was found in the SOI layers of the SOI substrates of Example 1 and Example 2. Has disappeared (FIGS. 4 and 5). In particular, most of the slip lines disappeared in the SOI layer of the SOI substrate of Example 2 which was heat-treated in a nitrogen atmosphere (FIG. 5). The reason that the slip line disappears more remarkably in the second embodiment than in the first embodiment is that in the heat treatment in the oxygen atmosphere of the first embodiment, a large amount of interstitial silicon atoms are simultaneously supplied to the dislocations due to the oxidation reaction. On the other hand, in the heat treatment in the nitrogen atmosphere of the second embodiment, only the vacancies are supplied to the dislocations. Therefore, it is considered that the heat treatment of the second embodiment is more effective in forming the jog. Can be
Further, the density of the slip line was measured by observation with an optical microscope. FIG. 6 shows the result. The slip line density of the SOI layer of Comparative Example 1 was about 5.3 × 10 ⁷ cm / cm ³ , whereas the slip line density of Example 1 was about 2.3 × 10 ⁷ cm / cm ³ . Yes, the slip line density of Example 2 was about 1.0 × 10 ⁷ cm / cm ³ . For these reasons, the slip line densities of Examples 1 and 2 were less than half that of Comparative Example 1.
[0016]
【The invention's effect】
As described above, according to the method for manufacturing an SOI substrate of the present invention, two silicon wafers are bonded by heat treatment, and ground and polished, and then heat-treated again at 1200 to 1300 ° C. for at least 10 hours. The edge dislocations (slip) of the SOI layer generated during the heat treatment are eliminated, and the slip line density of the SOI layer can be reduced to 2.5 × 10 ⁷ cm / cm ³ or less. An SOI substrate that does not adversely affect electric characteristics can be obtained.
[Brief description of the drawings]
FIG. 1 is a partial sectional view illustrating a method for manufacturing an SOI substrate according to an embodiment of the present invention.
FIG. 2 is an X-ray topography photograph of an SOI layer portion formed on a substrate of Comparative Example 1.
FIG. 3 is an optical microscope photograph of an SOI layer formed on a substrate of Comparative Example 1.
FIG. 4 is an optical micrograph of an SOI layer formed on the substrate of Example 1.
FIG. 5 is an optical micrograph of an SOI layer formed on the substrate of Example 2.
FIG. 6 is a diagram showing slip line densities of Comparative Example 1, Examples 1 and 2.
[Explanation of symbols]
11 first silicon wafer 12 second silicon wafer 12a SOI layer 13 insulating layer (silicon oxide layer)

Claims (1)

Bonding the first silicon wafer (11) and the second silicon wafer (12) via an insulating layer (13) ;
And Ru bonding step by heat-treating the first and second silicon wafers that the joint (11, 12),
Grinding and polishing the first silicon wafer (11) or the second silicon wafer (12) to a predetermined thickness to form an SOI layer (12a) for device formation ;
After the grinding and polishing, heat-treating again in a dry oxygen atmosphere or a nitrogen atmosphere in a temperature range of 1200 to 1300 ° C. for at least 10 hours ;
Including
A method for manufacturing an SOI substrate, wherein each of the steps is performed continuously .

Images