CN113421848B - Preparation process of silicon substrate on power insulator - Google Patents

Preparation process of silicon substrate on power insulator Download PDF

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CN113421848B
CN113421848B CN202110565302.3A CN202110565302A CN113421848B CN 113421848 B CN113421848 B CN 113421848B CN 202110565302 A CN202110565302 A CN 202110565302A CN 113421848 B CN113421848 B CN 113421848B
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substrate
silicon
temperature
corrosion
bonding
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CN113421848A (en
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马乾志
孙晨光
王彦君
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Zhonghuan Leading Semiconductor Technology Co ltd
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Zhonghuan Advanced Semiconductor Materials Co Ltd
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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Abstract

The invention relates to a preparation process of a silicon substrate on a power insulator, which comprises the steps of preparing a silicon epitaxial wafer as a silicon substrate of a device layer, preparing a silicon oxide wafer as a supporting silicon substrate, carrying out plasma surface activation treatment, carrying out normal-temperature bonding, carrying out low-temperature annealing, adopting a mechanical grinding thinning mode, removing a substrate silicon single crystal by utilizing two-step selective acid corrosion of fast corrosion and slow corrosion, carrying out CMP polishing treatment, then carrying out high-temperature oxidation thinning treatment, and finally removing silicon oxide grown by high-temperature oxidation through diluted hydrofluoric acid corrosion; the low-temperature annealing temperature after bonding is not more than 400 ℃; and the polishing removal amount of the bonding sheet is not more than 1um, the temperature of high-temperature oxidation annealing is not lower than 900 ℃, and finally, the required silicon-on-insulator substrate is obtained after the surface oxide layer is removed through a wet cleaning process. The invention accurately controls the thickness and uniformity of the silicon substrate device layer on the power insulator by selective corrosion and a thinning mode of CMP polishing and high-temperature thermal oxidation.

Description

Preparation process of silicon substrate on power insulator
Technical Field
The invention relates to a preparation method of an integrated circuit material, in particular to a preparation method of a silicon substrate on a power insulator.
Background
Semiconductor devices based on silicon-on-insulator (SOI) substrates are receiving much attention because of their significant advantages in power consumption, operating speed, radiation resistance, and device integration. In recent years, with the continuous progress of process technology, the preparation of SOI materials has been developed rapidly. The SOI material can be divided into two main products of a thin film SOI (top silicon is usually smaller than 1 μm) and a thick film SOI (top silicon is usually larger than 1 μm) according to the thickness of a top silicon layer, and the corresponding SOI product application can be divided into the categories of radio frequency SOI, power SOI, image SOI, MEMS micro-electro-mechanical system SOI and the like; the major driving force in the thin film SOI market is from the application of high speed, low power products such as microprocessors, and rf front end devices. The thick film SOI market is primarily focused on applications such as power devices and micro-electromechanical devices.
Power SOI, also known as power silicon-on-insulator technology, is another large area of application for SOI technology beyond RFSOI. In a conventional bulk silicon power integrated circuit with PN junction as isolation, carriers injected into a substrate are often collected by device cells adjacent to the carrier, causing unwanted crosstalk and latch-up. The power device based on the SOI technology can realize the real physical longitudinal Isolation longitudinally through a Buried Oxide Layer (BOX), can realize the transverse Isolation transversely through a Deep Trench Oxide Layer (DTI), and can respectively manufacture components on different Isolation islands, thereby reducing or eliminating the common electric leakage and latch-up effect in the bulk silicon power device and improving the integration density of the circuit. Meanwhile, the SOI technology has lower leakage current than bulk silicon devices, so that the SOI device can work at higher voltage and higher temperature.
At present, the preparation technology of the silicon substrate material on the power insulator mainly comprises a Smart-cut technology and a BESOI bonding thinning technology. BESOI technology has the characteristics of simple process, low cost and the like, and the BESOI silicon chip has the crystal defect density and the surface quality which are similar to those of bulk silicon and can be adjusted in a large range. However, due to the thinning process, the thickness uniformity of the top device silicon layer is difficult to control accurately.
Disclosure of Invention
The invention aims to provide a preparation process of a silicon substrate on a power insulator, which can accurately control the thickness and uniformity of a silicon substrate device layer on the power insulator through a thinning mode of selective corrosion, CMP (chemical mechanical polishing) and high-temperature thermal oxidation.
The invention realizes the purpose through the following technical scheme: a process for preparing a silicon-on-insulator substrate for power applications, comprising the steps of:
s101, providing a monocrystalline silicon substrate;
s102, growing a layer of lightly doped monocrystalline epitaxial silicon layer on the surface of the monocrystalline silicon substrate;
s103, providing a support substrate, wherein the front surface of the support substrate is a polishing surface;
s104, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s105, respectively carrying out plasma surface activation treatment on the surface of the epitaxial layer of the monocrystalline silicon substrate and the surface of the support substrate with the insulating layer as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together at normal temperature to form a bonded substrate;
s106, placing the bonded substrate into a furnace tube for low-temperature annealing, wherein the annealing temperature is not higher than 400 ℃;
s107, removing most of substrate monocrystalline silicon by thinning the bonded substrate in a mechanical grinding mode, and reserving the substrate monocrystalline silicon smaller than 80um for removing through subsequent processes;
s108, performing acid corrosion on the thinned bonding substrate, spraying a mixed corrosion solution of hydrofluoric acid, nitric acid and acetic acid on the rotating bonding substrate, and automatically stopping chemical corrosion on the interface of the epitaxial layer and the single crystal substrate through fast corrosion and slow corrosion under two solutions with different proportions to ensure that the single crystal silicon substrate reserved after mechanical grinding is completely removed;
s109, carrying out CMP polishing on the corroded bonded substrate to obtain the required surface roughness;
s110, performing high-temperature thermal oxidation on the polished bonding substrate to further improve the bonding strength;
and S111, carrying out chemical corrosion of hydrofluoric acid on the oxidized bonding substrate to remove the surface silicon dioxide layer, and simultaneously carrying out wet cleaning of SC1 and SC2 to remove surface particles and surface metal contamination.
Further, the S101 monocrystalline silicon substrate is a heavily doped substrate and has resistivity R1.
Further, the S102 epitaxial silicon layer and the monocrystalline silicon substrate have the same doping type, the resistivity of the epitaxial silicon layer is R2, and R2/R1> 100.
Further, the thickness of the silicon dioxide of the S104 is 0.5-1 um.
Further, the annealing time of the S106 is more than 2 hours.
Further, the reserved thickness in S107 is 20-50 um.
Further, the removal amount of the first-step rapid corrosion in S108 is 30-50 um, and the removal amount of the second-step slow corrosion is 5-10 um.
Further, the polishing removal amount in S109 is not more than 2 um.
Further, in the step S110, the oxidation temperature is not lower than 900 ℃, and the oxidation time is not lower than 2 hours.
Further, in S2, ultrasonic irradiation is adopted, the wavelength of the ultraviolet light is 254nm, and the power is 600 w.
Compared with the prior art, the preparation process of the silicon substrate on the power insulator has the beneficial effects that: on the basis of the process of preparing the silicon-on-insulator substrate material by the conventional bonding and thinning process, selective acid corrosion, polishing and high-temperature oxidation are comprehensively used as thinning process means to realize the transfer of an epitaxial layer onto a support substrate, so that the silicon-on-insulator substrate material applied to a power device is prepared; before bonding, the epitaxial wafer and the supporting substrate silicon wafer are subjected to plasma surface activation treatment, and are matched with low-temperature annealing, so that the stronger bonding strength can be realized to meet the requirements of the subsequent thinning process on the premise of not influencing the width of an epitaxial transition region; by adopting a single-chip rotary etching process with nitrogen back seal, on the premise of protecting the back surface, the thinning and etching self-stop of the epitaxial single crystal substrate are realized on the front surface of the ground bonding sheet through a two-step acid etching process, so that the epitaxial single crystal substrate is completely etched and removed, meanwhile, the epitaxial layer is not etched basically, and the uniformity of the thickness of the epitaxial layer is maintained; the polishing after the acid etching only needs a small removal amount to improve the surface roughness, and the removal amount is less than 1um, so that the uniformity of the thickness of the epitaxial layer can be ensured not to be influenced; the high-temperature oxidation treatment after polishing adopts conventional thermal oxidation higher than 900 ℃, so that a bonding interface can be further reinforced, and the target thickness can be further thinned and corrected in a thinning mode of oxidizing consumed silicon to achieve the final target thickness.
Drawings
FIG. 1 is a flow chart of the steps performed in accordance with an embodiment of the present invention.
Fig. 2 is a schematic diagram of the product state of step S101 and step S102.
Fig. 3 is a schematic diagram of the product state of step S103 and step S104.
Fig. 4 is a schematic diagram of the product status of step S105 and step S106.
Fig. 5 is a schematic diagram of the product status in step S107.
Fig. 6 is a schematic diagram of the product state of step S108 and step S109.
Fig. 7 is a schematic diagram of the product status in step S110.
Fig. 8 is a schematic diagram of the product state of step S111 and step S102.
Detailed Description
The following describes in detail a specific embodiment of a method for manufacturing a silicon-on-insulator substrate according to the present invention with reference to the accompanying drawings.
Fig. 1 is a flowchart illustrating implementation steps of the present embodiment, and a process for manufacturing a silicon-on-insulator substrate includes the following steps:
step S101, providing a monocrystalline silicon substrate, wherein the monocrystalline silicon substrate is a heavily doped substrate and has a resistivity of R1;
step S102, growing a layer of lightly doped monocrystalline epitaxial silicon layer on the surface of the monocrystalline silicon substrate, wherein the epitaxial silicon layer and the monocrystalline silicon substrate have the same doping type, and the resistivity of the epitaxial silicon layer is R2;
step S103, providing a support substrate, wherein the front surface of the support substrate is a polishing surface;
step S104, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
step S105, respectively carrying out plasma surface activation treatment on the surface of the epitaxial layer of the monocrystalline silicon substrate and the surface of the supporting substrate with the insulating layer as bonding surfaces, and bonding the monocrystalline silicon substrate and the supporting substrate together at normal temperature to form a bonded substrate;
step S106, placing the bonded substrate into a furnace tube for low-temperature annealing, wherein the annealing temperature is not higher than 400 ℃;
step S107, removing most of substrate monocrystalline silicon by thinning the bonded substrate through mechanical grinding, and reserving 20-50 um substrate monocrystalline silicon for removing through subsequent processes;
step S108, performing acid corrosion on the thinned bonding substrate, spraying a mixed corrosion solution of hydrofluoric acid, nitric acid and acetic acid on the rotating bonding substrate, and automatically stopping chemical corrosion on an interface between the epitaxial layer and the single crystal substrate through fast corrosion and slow corrosion under two solutions with different proportions to ensure that the single crystal substrate of 20-30 microns reserved after mechanical grinding is completely removed;
step S109, performing CMP polishing on the corroded bonded substrate to obtain the required surface roughness;
step S110, performing high-temperature thermal oxidation on the polished bonding substrate to further improve the bonding strength;
and step S111, carrying out chemical corrosion of hydrofluoric acid on the oxidized bonded substrate to remove the surface silicon dioxide layer, and simultaneously carrying out wet cleaning of SC1 and SC2 to remove surface particles and surface metal contamination.
Referring to step S101 and step S102, as shown in fig. 2, a single crystal silicon substrate 100 is provided, wherein the single crystal silicon substrate 100 has a dopant of boron and a resistivity of R1. Growing a lightly doped single crystal epitaxial silicon layer 110 on the surface of a single crystal silicon substrate 100, wherein the doping substance of the lightly doped single crystal epitaxial silicon layer 110 is boron, the resistivity of the epitaxial silicon layer is R2, and R2/R1 is more than 100; preferably, R1 is 0.003-0.008 ohm.cm; and R2 is 3-20 ohm.
Referring to steps S103 and S104, as shown in fig. 3, a monocrystalline silicon supporting substrate 200 is provided, the front surface of the supporting substrate 200 is a polished surface, and then thermal oxidation is performed to form a front surface oxide layer and a back surface oxide layer 220 on the front surface and the back surface of the supporting substrate, respectively, wherein the front surface oxide layer is to be used as an insulating layer 210. The thickness of the silicon dioxide is preferably 0.5-1 um.
Referring to step S105, as shown in fig. 4, plasma surface activation is performed on the surface of the insulating layer 210 of the supporting substrate and the surface of the epitaxial silicon layer 110, respectively, and then the two surfaces are bonded together at normal temperature to complete bonding, thereby forming a bonded substrate. Plasma treatment is preferably performed in a vacuum chamber using N2 and O2 as gas sources.
Referring to step S106, the bonded substrate is subjected to low temperature annealing at a temperature not higher than 400 ℃.
Because the surface before bonding has been subjected to plasma activation in step S105, a sufficiently strong bonding strength can be achieved only by one low-temperature annealing; the annealing atmosphere may be nitrogen, oxygen, or other inert gas. The annealing time is more than 2 hours. The annealing temperature is lower than 400 ℃, which can avoid hot carrier effect and can also avoid doping elements in the monocrystalline silicon substrate 100 from diffusing into the epitaxial layer 110 to influence the width of the transition region. The original resistivity gradient can be kept, and a premise is provided for subsequent selective corrosion based on the resistivity gradient. The annealing temperature is preferably 350 ℃ and the annealing time is preferably 3 hours.
Fig. 5 refers to step S107, and the thickness of the single crystal substrate 100 is thinned to a reserved thickness of <80um by using a mechanical grinding thinning manner; preferably, the reserved thickness is 20-50 um;
fig. 6 shows that, with reference to step S108, the bonded substrate after mechanical grinding and thinning is selectively etched to remove the remaining single crystal substrate silicon after mechanical grinding by using a two-step acid etching process of fast etching and slow etching; the back of the supporting substrate 200 is always protected by nitrogen in the corrosion process, so that the back is not influenced by corrosion; the first step adopts acid etching liquid with relatively fast etching rate to remove most of the reserved monocrystalline substrate silicon, and the second step adopts acid etching liquid with relatively slow etching rate to remove the part of the monocrystalline substrate silicon close to the epitaxial layer interface until the lightly doped epitaxial layer is etched to the transition region, so that the etching process is stopped automatically because the lightly doped epitaxial layer is not etched basically. Preferably, the removal amount of the first-step rapid corrosion is 30-50 um, and the removal amount of the second-step slow corrosion is 5-10 um;
referring to step S109, CMP polishing is performed on the bonded substrate after acid etching, and the removal amount of polishing is not more than 2um, so that the requirement of surface roughness is met, and the problem of uniformity deterioration caused by polishing can be reduced to the greatest extent. The removal amount is preferably 0.5-1 um.
Referring to step S110 in fig. 7, the polished bonded substrate is subjected to high-temperature thermal oxidation at an oxidation temperature of not less than 900 ℃ for an oxidation time of not less than 2 hours. The oxidizing atmosphere in this step may be a dry oxygen atmosphere or a wet oxygen atmosphere, and the silicon dioxide layer 120 is formed on the surface. According to the final target thickness of the top silicon of the device, the oxidation atmosphere can be regulated, and the thickness of the top silicon can be indirectly regulated in a silicon consumption oxidation mode. Meanwhile, the heat treatment at the temperature of more than 900 ℃ can further promote the polymerization reaction of the bonding interface to form covalent bonds with higher density, thereby improving the bonding strength. The thermal oxidation temperature is 1100 ℃ and the thermal oxidation time is 4 hours.
Fig. 8 referring to step S111, the bonded substrate after the thermal oxidation is subjected to wet etching with hydrofluoric acid to remove the surface silicon dioxide layer 120, and at the same time, the SC1 plus SC2 is cleaned to remove surface particles and surface metal contaminants, thereby completing the preparation of the silicon-on-insulator substrate wafer. Preferably, 5-10% HF solution is adopted to remove the surface silicon dioxide.
On the basis of the process for preparing the silicon-on-insulator substrate material by the conventional bonding and thinning process, selective acid corrosion, polishing and high-temperature oxidation are comprehensively used as thinning process means to realize the transfer of an epitaxial layer onto a support substrate, so that the silicon-on-insulator substrate material applied to a power device is prepared; before bonding, the epitaxial wafer and the supporting substrate silicon wafer are subjected to plasma surface activation treatment, and are matched with low-temperature annealing, so that the stronger bonding strength can be realized to meet the requirements of the subsequent thinning process on the premise of not influencing the width of an epitaxial transition region; by adopting a single-chip rotary etching process with nitrogen back seal, the thinning and etching self-stop of the epitaxial single-crystal substrate are realized on the front side of the ground bonding piece through a two-step acid etching process on the premise of protecting the back side, so that the epitaxial single-crystal substrate is completely etched and removed, the epitaxial layer is basically not etched, and the thickness uniformity of the epitaxial layer is kept; the polishing after the acid etching only needs a small removal amount to improve the surface roughness, and the removal amount is less than 1um, so that the uniformity of the thickness of the epitaxial layer can be ensured not to be influenced; the high-temperature oxidation treatment after polishing adopts conventional thermal oxidation higher than 900 ℃, so that a bonding interface can be further reinforced, and the target thickness can be further thinned and corrected in a thinning mode of oxidizing consumed silicon to achieve the final target thickness.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and adjustments can be made without departing from the principle of the present invention, and these modifications and adjustments should also be regarded as the protection scope of the present invention.

Claims (7)

1. A process for preparing a silicon-on-insulator substrate for power applications, comprising the steps of:
s101, providing a monocrystalline silicon substrate;
s102, growing a layer of lightly doped monocrystalline epitaxial silicon layer on the surface of the monocrystalline silicon substrate;
s103, providing a support substrate, wherein the front surface of the support substrate is a polishing surface;
s104, carrying out thermal oxidation on the support substrate, and growing silicon dioxide as an insulating layer;
s105, respectively carrying out plasma surface activation treatment on the surface of the epitaxial layer of the monocrystalline silicon substrate and the surface of the support substrate with the insulating layer as bonding surfaces, and bonding the monocrystalline silicon substrate and the support substrate together at normal temperature to form a bonded substrate;
s106, placing the bonded substrate into a furnace tube for low-temperature annealing, wherein the annealing temperature is not higher than 400 ℃; the annealing time is more than 2 hours;
s107, removing most of substrate monocrystalline silicon by thinning the bonded substrate in a mechanical grinding mode, and reserving the substrate monocrystalline silicon smaller than 80um for removing through subsequent processes;
s108, performing acid corrosion on the thinned bonding substrate, spraying a mixed corrosion solution of hydrofluoric acid, nitric acid and acetic acid on the rotating bonding substrate, and automatically stopping at the interface of the epitaxial layer and the single crystal substrate through chemical corrosion under two solutions with different proportions of fast corrosion and slow corrosion to ensure that the single crystal silicon substrate reserved after mechanical grinding is completely removed;
s109, carrying out CMP polishing on the corroded bonded substrate to obtain the required surface roughness;
s110, performing high-temperature thermal oxidation on the polished bonding substrate to further improve the bonding strength; the oxidation temperature is not lower than 900 ℃, and the oxidation time is not lower than 2 hours;
and S111, carrying out chemical corrosion of hydrofluoric acid on the oxidized bonding substrate to remove the surface silicon dioxide layer, and simultaneously carrying out wet cleaning of SC1 and SC2 to remove surface particles and surface metal contamination.
2. The process for preparing a silicon-on-insulator substrate for power as claimed in claim 1, wherein: the S101 monocrystalline silicon substrate is a heavily doped substrate and has the resistivity of R1.
3. The process for preparing a silicon-on-insulator substrate for power as claimed in claim 2, wherein: the S102 epitaxial silicon layer and the monocrystalline silicon substrate have the same doping type, the resistivity of the epitaxial silicon layer is R2, and R2/R1> 100.
4. The process for preparing a silicon-on-insulator substrate for power as claimed in claim 1, wherein: the thickness of the silicon dioxide of the S104 is 0.5-1 um.
5. The process for preparing a silicon-on-insulator substrate for power as claimed in claim 1, wherein: and the reserved thickness in the S107 is 20-50 um.
6. The process for preparing a silicon-on-insulator substrate for power as claimed in claim 1, wherein: in S108, the removal amount of the first-step rapid corrosion is 30-50 um, and the removal amount of the second-step slow corrosion is 5-10 um.
7. The process for preparing a silicon-on-insulator substrate for power as claimed in claim 1, wherein: the polishing removal amount in the step S109 is not more than 2 um.
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