JP2010278160A - Method for manufacturing soi wafer, and soi wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SOI wafer having a high interface level density (Dit) for trapping carriers at an interface between a BOX layer (buried oxide film) and a base wafer without complicating manufacturing process itself of the SOI wafer, and to provide a method for manufacturing the SOI wafer. <P>SOLUTION: A method for manufacturing an SOI wafer includes at least the steps of: forming a silicon oxide film on a surface of a base wafer made of a silicon single crystal; bonding the base wafer with a bond wafer made of a silicon single crystal via the silicon oxide film; and thinning the bond wafer to form an SOI layer. In the method, a wafer having a resistivity of 100 Ω-cm or more and a surface roughness (Ra) at the surface to which the bond wafer is to be bonded of 0.1 μm or more is used as the base wafer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an SOI (Silicon On Insulator) wafer manufactured by bonding a silicon single crystal wafer through a silicon oxide film, and more specifically, a high resistance having a resistivity of 100 Ω · cm or more to a base wafer. The present invention relates to an SOI wafer using a high rate wafer and a manufacturing method thereof.

  With the widespread use of mobile terminals, RF (Radio Frequency) devices mainly intended for communication interfaces have attracted attention and are expected to develop rapidly in the future.

For example, in the case of a portable terminal, when an SOI wafer is used, there is a merit that power consumption is reduced due to reduction of leakage current. Further, it is considered to incorporate an RF device by System on a Chip (SoC) or the like, but there is an advantage of reducing crosstalk between devices by using an SOI wafer in terms of the characteristics of the RF transistor.
Here, the crosstalk is an undesired propagation of an electric signal between devices and indicates that a signal is exchanged through a capacitor between device wirings or a wafer. The higher the resistivity of the wafer, the less the crosstalk. However, in reality, the wafer resistivity of the device forming portion cannot be extremely increased.
However, when an SOI wafer is used, crosstalk can be reduced because a buried oxide film layer (BOX layer) exists between the SOI layer and the base wafer.

  In addition, since no device is formed on the base wafer that is the base of the BOX layer, a high resistivity wafer can be used without being restricted in device formation, thereby improving RF characteristics.

  As described above, when an SOI wafer is used for an RF device, RF characteristics are improved when a high resistivity wafer is used as a base wafer. However, when a high resistivity base wafer is used, there is a case where an inversion layer is generated at the interface between the BOX layer and the base wafer. In such a case, the effect of using the high resistivity wafer is reduced.

As a countermeasure, a technique is disclosed in which the interface state density (Dit) at the interface between the BOX layer and the base wafer is increased, and carriers are trapped in the level to prevent characteristic deterioration due to the inversion layer.
As such a technique, for example, an intermediate layer such as a polysilicon layer or a nitride oxide is introduced at the interface between the BOX layer and the base wafer, so that an inversion layer is not formed, so that an SOI wafer having good RF characteristics can be obtained. Techniques that can be obtained are known (see, for example, Patent Documents 1 and 2).

  However, such a technique has a demerit that not only the manufacturing process of the SOI wafer is complicated, but defects at the bonding interface such as voids and blisters are likely to occur.

Special table 2007-507093 Special table 2007-507100 gazette

  Therefore, the present invention does not complicate the SOI wafer fabrication process itself, and an SOI wafer having a high interface state density (Dit) for trapping carriers at the interface between the BOX layer (embedded oxide film) and the base wafer, and its manufacture. It aims to provide a method.

  In order to solve the above problems, in the present invention, at least a silicon oxide film is formed on the surface of a base wafer made of a silicon single crystal, and the base wafer and a bond wafer made of a silicon single crystal are formed through the silicon oxide film. In the method for manufacturing an SOI wafer in which the bond wafer is thinned to form an SOI layer by bonding, the base wafer has a resistivity of 100 Ω · cm or more and a surface on the surface to be bonded to the bond wafer Provided is a method for manufacturing an SOI wafer characterized by using one having a roughness (Ra) of 0.1 μm or more.

The interface state density (Dit) at the interface between the wafer and the oxide film depends on the interface, that is, the surface roughness of the wafer surface during oxide film growth. That is, when the surface roughness of the wafer surface is poor, the number of interface states increases. Accordingly, a silicon single crystal wafer having a surface with a resistivity of 100 Ω · cm or more and a surface roughness on the bonding surface side of 0.1 μm or more is used as a base wafer, and a silicon oxide film is applied to the base wafer. By forming the SOI wafer, an SOI wafer having a high interface state density (Dit) at the interface between the silicon oxide film and the base wafer can be manufactured.
Also, the method should be a low-cost and high-quality SOI wafer manufacturing method compared to a SOI wafer manufacturing method in which an intermediate layer such as a polysilicon layer or a nitrided oxide is introduced at the interface between the BOX layer and the base wafer. Can do.

Here, it is preferable to use a CW wafer (chemical etching wafer) as the base wafer.
As described above, the interface state density (Dit) at the interface between the wafer and the oxide film depends on the interface, that is, the surface roughness of the wafer surface during oxide film growth. In the middle of the wafer fabrication, there is a stage where the wafer surface roughness is poor. Therefore, by performing oxide film growth on a CW wafer instead of a polished PW wafer completed by mirror polishing, an SOI wafer at an oxide film interface having a high interface state density (Dit) A silicon single crystal wafer having a large surface roughness can be obtained without adding an additional step for increasing the roughness, and the manufacturing cost can be reduced.

Moreover, it is preferable that after forming a silicon oxide film on the surface of the base wafer, the surface of the silicon oxide film on the side to be bonded to the bond wafer is polished.
Here, if the surface roughness on the side of the base wafer to be bonded is poor, the surface roughness of the oxide film surface may be deteriorated accordingly. In the case of a bonded SOI wafer, the deterioration of the surface roughness of the bonded surface may cause deterioration of the bonding strength and may hinder the production of the SOI wafer.
However, by polishing the surface of the silicon oxide film on the side to be bonded, the surface roughness of the bonded surface can be improved to the extent that the state after bonding is very good. Manufacture is possible.
Even in this case, the order of final polishing after forming the oxide film is reversed by reversing the procedure of final polishing and growing the oxide film from the middle stage of normal silicon single crystal wafer fabrication. Thus, it is possible to provide an SOI wafer having a high interface state density (Dit) without increasing the number of processes and without complicating the SOI wafer manufacturing process itself.

  The present invention is also an SOI wafer comprising at least an SOI layer, a silicon oxide film, and a base wafer, wherein the base wafer is made of a silicon single crystal having a resistivity of 100 Ω · cm or more, and the base wafer. The SOI wafer is characterized in that the surface roughness (Ra) of the interface between the silicon oxide film and the silicon oxide film is 0.1 μm or more.

As described above, by using a base wafer having a resistivity of 100 Ω · cm or more and making the surface roughness (Ra) of the interface between the base wafer and the silicon oxide film 0.1 μm or more, the base wafer is obtained. It is possible to obtain an SOI wafer particularly suitable for manufacturing an RF device that has a high interface state density (Dit) at the interface between the silicon oxide film and the silicon oxide film and easily traps carriers.
In addition, since an intermediate layer such as a polysilicon layer or a nitride oxide is not provided at the interface between the BOX layer and the base wafer, the structure is simple and easy to manufacture, and the SOI wafer is a high-quality SOI wafer at a low cost.

Here, it is preferable that a CW wafer (chemical etching wafer) is used as the base wafer.
In this case, silicon subjected to an additional process for increasing the surface roughness of a mirror-polished wafer (PW wafer) completed after the production process of a silicon single crystal wafer including ingot production, slicing, lapping, etching, and polishing is performed. Since an SOI wafer manufactured using a CW wafer after etching as a base wafer instead of a single crystal wafer can be used as a base wafer, the manufacturing process itself is not complicated and is very simple, yet it has an interface state. A low-cost SOI wafer having a high density (Dit) can be provided.

The silicon oxide film is preferably formed on the surface of the base wafer, and the surface to be bonded to the bond wafer is preferably polished.
As described above, the silicon oxide film is formed on the surface of the base wafer, and the surface on the side bonded to the bond wafer is a polished SOI wafer, so that the adhesion at the interface with the bond wafer is increased. It is possible to obtain an SOI wafer having a high bonding strength, that is, a high bonding strength.

  Thus, according to the present invention, for example, a silicon single crystal wafer having a high resistivity (100 Ω · cm or more) obtained by growing an oxide film on a wafer having a surface roughness as large as 0.1 μm or more during the wafer fabrication process. As a base wafer, an SOI wafer having a high interface state density (Dit) at the interface between the BOX layer and the base wafer and a method for manufacturing the same can be provided without complicating the SOI manufacturing process itself. .

It is the schematic which showed an example of the structure of the SOI wafer of this invention. It is the process flow which showed an example of the manufacturing process of the SOI wafer of this invention. It is the process flow which showed the manufacturing process of the SOI wafer for evaluation of an Example and a comparative example.

Hereinafter, the present invention will be described more specifically.
As described above, an SOI wafer having a high interface state density (Dit) for trapping carriers at the interface between the BOX layer (embedded oxide film) and the base wafer without complicating the manufacturing process of the SOI wafer itself, and a manufacturing method thereof The development of was awaited.

  Accordingly, the present inventors have made extensive studies on the structure of a SOI wafer and its manufacturing method capable of increasing the interface state density (Dit) without forming an intermediate layer at the interface between the BOX layer and the base wafer. .

  As a result, the inventors of the present invention have a surface roughness (Ra) of 0.1 μm or more on the surface to be bonded to the base wafer through the silicon oxide film and a resistivity of 100 Ω · cm. By using the above silicon single crystal wafer and forming a silicon oxide film on the surface of the base wafer, an SOI wafer having a high interface state density (Dit) at the interface between the BOX layer and the base wafer is manufactured in substantially the same manufacturing process as before. Thus, the present invention was completed.

  Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto. FIG. 1 is a schematic view showing an example of the structure of an SOI wafer according to the present invention.

As shown in FIG. 1, the SOI wafer 9 of the present invention includes at least an SOI layer 7, a BOX layer 3 that is a silicon oxide film, and a base wafer 2.
The base wafer 2 is made of a silicon single crystal having a resistivity of 100 Ω · cm or more, and the surface roughness (Ra) of the interface between the base wafer 2 and the BOX layer 3 is 0.1 μm or more. .
In FIG. 1, the silicon oxide film 3 covers the entire surface of the base wafer 2. However, the present invention is not limited to this, and it is sufficient that the silicon oxide film 3 exists at least between the SOI layer 7 and the base wafer 2.

Thus, if the surface roughness (Ra) of the interface between the base wafer and the silicon oxide film is 0.1 μm or more and the base wafer is a silicon single crystal wafer having a resistivity of 100 Ω · cm or more, the BOX layer and An SOI wafer having a high interface state density (Dit) for reducing the influence of the inversion layer generated at the interface with the base wafer can be obtained. That is, it is easy to trap carriers, and thus it is possible to suppress the deterioration of the RF characteristics caused by the formation of the inversion layer, that is, the SOI wafer has good RF characteristics.
In addition, since it is composed of a silicon single crystal wafer and an oxide film, the crystallinity is good and the structure itself is not complicated and is the same as a normal SOI wafer. This is an SOI wafer that can be manufactured at a low cost and high yield.

Here, a CW wafer (chemical etching wafer) can be used as the base wafer 2.
Since the CW wafer obtained in the middle of the manufacturing process of the silicon single crystal wafer is a wafer that has not been subjected to the mirror polishing process, it can be obtained at low cost. Further, since the surface is rough enough to have a sufficiently high number of interface states, an SOI wafer in which such a CW wafer is used as a base wafer has an interface state density at the interface between the base wafer and the silicon oxide film. (Dit) is high.
In addition, since it can be manufactured in almost the same manufacturing process as before except for using a wafer in the middle of the manufacturing process of a silicon single crystal wafer, there is no need to add a new process, and it is very easy to manufacture and high quality. It has the advantage that it can be set as a simple SOI wafer.

The silicon oxide film as the BOX layer 3 is formed on the surface of the base wafer 2, and the BOX layer 3 is bonded to the SOI layer 7 (bond wafer before thinning the SOI layer 7). The surface on the other side can be polished.
As described above, if the silicon oxide film as the BOX layer is formed on the surface of the base wafer, the SOI wafer having a high interface state density (Dit) at the interface with the base wafer can be obtained. In addition, since the surface of the silicon oxide film to be bonded to the bond wafer is polished, the SOI wafer has very high adhesion to the bond wafer, that is, a high bonding strength.

Such an SOI wafer of the present invention can be manufactured by the following processes, and an example thereof is shown below, but the method for manufacturing an SOI wafer of the present invention is not limited to the following.
FIG. 2 is a process flow showing an example of the process of the SOI wafer manufacturing method of the present invention.

(Process a: Preparation of wafer)
First, as shown in FIG. 2A, a bond wafer 1 and a base wafer 2 are prepared.
Here, a silicon single crystal wafer is used as the bond wafer 1 and a silicon wafer having a resistivity of 100 Ω · cm or more as the base wafer 2 and a surface roughness (Ra) on the side bonded to the bond wafer 1 of 0.1 μm or more. Prepare a crystal wafer.
Here, the resistivity of the base wafer 2 is preferably set to 1000 Ω · cm or more, but the upper limit of the resistivity is not particularly limited, and may be 10 ⁴ Ω · cm, 10 ⁵ Ω · cm or more. .
Further, when the surface roughness (Ra) of the surface to be bonded to the bond wafer is smaller than 0.1 μm, the interface state density (Dit) is not sufficiently high. The surface roughness is 0.1 μm or more.

A CW wafer (chemical etching wafer) can be used as the base wafer 2.
In the middle stage of the production of a silicon single crystal wafer, the number of interface states is large, the surface is rough enough to suppress the formation of the inversion layer, and is rough enough to prevent the bonding from occurring. There is a stage where the CW wafer after chemical etching just satisfies the condition.
Therefore, using a CW wafer as a base wafer and then forming an oxide film on the surface of the CW wafer, compared to the case of performing a process of roughening the surface roughness of a PW wafer that has already been mirror-polished and completed, Since the polishing step and the surface roughening step can be omitted, the manufacturing cost of the wafer can be greatly reduced. In addition, an SOI wafer having a high interface state density (Dit) can be easily obtained, which is very suitable.

  In addition, as the wafer surface (in a state where the surface roughness is poor) before mirror polishing, it is preferable to use a CW wafer that has been subjected to chemical etching as described above, but the surface roughness is poor and Ra is 0. 0. If it is 1 micrometer or more, it will not be limited to a CW wafer, For example, a lapping wafer and a surface grinding wafer may be sufficient.

The chemical etching mainly includes acid etching and alkali etching.
It is known that the surface roughness of the etching surface (that is, the surface roughness of the CW surface) is smaller in the acid etching, and the etching surface formed by the etching conditions (etching liquid composition, liquid temperature, etc.) Although the surface roughness is different, in any case, the surface roughness (Ra) of the CW wafer generally has a value in the range of 0.1 μm to 0.3 μm, and the number of interface states is sufficiently large. In addition, the silicon single crystal wafer has a surface roughness that does not interfere with bonding.

(Process b: Formation of silicon oxide film (BOX layer))
Next, as shown in FIG. 2B, a silicon oxide film 3 is formed on the base wafer 2.

(Process c: Ion implantation)
Next, as shown in FIG. 2C, at least one kind of hydrogen ion or rare gas ion is implanted into one main surface of the bond wafer 1 to form an ion implantation layer 4.

Here, after the formation process of the silicon oxide film 3 on the base wafer 2 and before the next bonding process, the surface of the silicon oxide film on the side to be bonded to the bond wafer 1 is polished. be able to.
If the surface roughness of the surface to be bonded to the base wafer is poor, the surface roughness of the oxide film surface also deteriorates accordingly, the bonding strength with the bond wafer is weakened, voids are generated, Problems such as a decrease in yield may occur.
However, by polishing the surface of the silicon oxide film on the side to be bonded, the incidence of bonding defects can be greatly reduced, and an SOI wafer having a high interface state density (Dit) can be manufactured. Can do.

(Process d: Bonding)
Thereafter, as shown in FIG. 2D, the bond wafer 1 and the base wafer 2 are divided into a surface on the side of the bond wafer 1 where the ion implantation layer 4 is formed, and the surface roughness of the base wafer 2 is 0.1 μm. The above surfaces are bonded to each other with the silicon oxide film 3 as a bonding surface.

(Process e: peeling)
Thereafter, as shown in FIG. 2 (e), the bond wafer 1 is peeled off by the previously formed ion implantation layer 4, and the SOI layer 7 is formed on the base wafer 2 with the BOX layer 3 interposed therebetween. A bonded substrate 6 having an ion-implanted damage layer 8 and a peeled bond wafer 5 are obtained. The bond wafer 5 after peeling can be reused as a bond wafer after removing defects on the peeling surface.
In addition, in this thinning, after bonding at room temperature, if necessary, a low-temperature heat treatment at about 500 ° C. is performed to perform peeling, and then a bonding heat treatment step (f) for increasing the bonding strength is performed. In order. Further, at this time, a method of peeling off the ion-implanted layer by mechanical stress without performing the heat treatment at about 500 ° C. by bonding the wafer surfaces to be bonded after being activated by plasma treatment. It can also be used.

(Process f: Bonding heat treatment)
Thereafter, as shown in FIG. 2F, a bonded heat treatment can be performed on the bonded substrate 6. For example, two wafers can be firmly bonded by performing heat treatment at 1000 ° C. to 1200 ° C. for 10 minutes to 6 hours in an oxidizing or inert gas atmosphere.

(Process g: Planarization treatment)
Thereafter, as shown in FIG. 2G, a planarization process is performed on the SOI layer 7 in order to remove the ion implantation damage layer 8 on the surface of the SOI layer 7 of the bonded substrate 6 on which the bonding heat treatment has been performed. Thus, the SOI wafer 9 is obtained.
As this planarization treatment, for example, chemical mechanical polishing (CMP) or high-temperature heat treatment can be performed.

  As described above, in the method for manufacturing an SOI wafer according to the present invention, the carrier can be trapped by having good crystallinity and increasing the interface state density (Dit) while having a simple structure. Therefore, an SOI wafer capable of suppressing deterioration of electrical characteristics due to the inversion layer of the high resistivity base wafer can be manufactured with high yield and low cost.

  In the above example, the case where the SOI wafer is manufactured by the ion implantation delamination method is described as an example. However, the method of thinning the SOI layer is not limited to this, and the bond wafer is thinned by grinding or polishing. Thus, an SOI wafer can be manufactured. In the above example, the oxide film is formed only on the base wafer, but the oxide film can also be formed on the surface of the bond wafer for bonding.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example 1 and Comparative Example 1)
First, among silicon single crystal wafers of crystal plane orientation <100> cut out from the same ingot with a diameter of 200 mm, CW wafers after chemical etching (after chemical etching with a mixed acid etching solution of hydrofluoric acid, nitric acid, and acetic acid: Ra = Two types were prepared: an oxide film formed on 0.11 μm) and an oxide film formed on a PW wafer (Ra = 0.25 nm) after mirror polishing. The formed oxide film was 100 nm. The surface roughness Ra of the CW wafer was measured using a surface roughness measuring machine manufactured by Komatsu Laboratories Co., Ltd., and the surface roughness Ra of the PW wafer was measured at 10 μm square by AFM. An electrode was attached to the oxide film of this wafer and CV measurement was performed. The interface state density (Dit) was evaluated from the curve of the CV measurement. The results are shown in Table 1. The unit of interface state density (Dit) in the table is [1 / cm ² / eV].
Moreover, the above-mentioned process was performed on a silicon single crystal wafer having a crystal plane orientation <110>, and the same evaluation was performed. The results are also shown in Table 1.

  As shown in Table 1, in the CW wafer, the interface state density (Dit) at the interface between the silicon single crystal and the silicon oxide film is increased by about 10 to 20% regardless of the crystal plane orientation, compared with the PW wafer. all right.

[Preparation of SOI wafer]
Then, an SOI wafer was manufactured by the SOI wafer manufacturing method as shown in FIG.
As a base wafer, a CW wafer (Example 1: Ra = 0.11 μm) cut from a CZ silicon single crystal ingot having a diameter of 300 mm, p-type, plane orientation (100), and resistivity of 1000 Ω · cm and treated by mixed acid etching. And a PW wafer (Comparative Example 1: Ra = 0.25 nm) subjected to mirror polishing on the silicon single crystal wafer, and an oxide film of 150 nm was formed as a BOX layer on the surface by heat treatment.

  On the other hand, the bond wafer was cut from a CZ silicon single crystal ingot having a diameter of 300 mm, a p-type, a plane orientation (100), and a resistivity of 100 Ω · cm, and a silicon single crystal wafer subjected to mixed acid etching and mirror polishing was prepared. Then, hydrogen ions were implanted from the surface of the bond wafer to form an ion implantation layer inside.

Thereafter, the ion-implanted surface of the bond wafer and the oxide film surface of the base wafer were bonded to each other and subjected to a separation heat treatment to be separated by an ion-implanted layer, whereby an SOI wafer having an SOI layer having a thickness of 150 nm was manufactured.
Thereafter, the peeling surface of the SOI layer was planarized to complete an SOI wafer (SOI layer 70 nm) for forming an RF device.

[Measurement of interface state density (Dit)]
On the other hand, for the purpose of measuring the interface state density (Dit) at the interface between the BOX layer and the base wafer, a silicon single crystal wafer having the same specifications as those of the bond wafer and the base wafer used in [Preparation of SOI wafer] is prepared. did.
However, in order to simulate the structure of the SOI wafer, a silicon single crystal wafer prepared as a bond wafer is prepared as a base wafer (provisional) 21 and a base wafer as in the manufacturing process flow of the evaluation SOI wafer shown in FIG. The bonded wafer (temporary) 22 is used, and hydrogen ion implantation is performed on the bond wafer (temporary) 22 on which the silicon oxide film 3 of 150 nm is formed to form the ion implantation layer 14. The SOI layer 17 having a thickness of 150 nm is formed by performing bonding and heat treatment to form an SOI layer 17 having a thickness of 150 nm, and thereafter, bonding heat treatment and planarization treatment are performed to reduce the SOI layer 17 to 70 nm for evaluation. SOI wafer 19 for manufacturing was produced.

  Then, as described in Japanese Patent Application Laid-Open No. 2006-13100, an SOI MOSFET can be used to evaluate the electrical characteristics of the interface between the BOX layer and the SOI layer by bringing the mercury probe 12 into contact with the SOI layer 17. Interface state density (Dit) at the interface between the layer 17 and the BOX layer 3 (that is, structurally equivalent to the interface between the BOX layer 3 and the base wafer 2 of the SOI wafer 9 manufactured in [Preparation of SOI wafer] in FIG. 2) Was measured.

As a result of measuring the interface state density (Dit) of the evaluation SOI wafer 19, the interface state density (Dit) of the evaluation SOI wafer of Comparative Example 1 using a PW wafer as the base wafer was 6.0. While it was × 10 ¹¹ / cm ² / eV, the evaluation SOI wafer interface state density (Dit) of Example 1 using a CW wafer was 7.1 × 10 ¹¹ / cm ² / eV. An increase of nearly 20% was confirmed.
However, the SOI wafer of Comparative Example 1 was well bonded and void free, but the SOI wafer of Example 1 had a small number of voids.

(Example 2)
In the SOI wafer manufacturing method of Example 1, the same SOI as in Example 1 except that the surface of the oxide film formed by oxidizing the CW wafer was polished to flatten the surface (Example 2). An SOI wafer was manufactured by the wafer manufacturing method.

When the surface roughness of the polished silicon oxide film surface was measured at 10 μm square by AFM, Ra = 0.25 nm.
And the SOI wafer of Example 2 became void-free.

  As described above, according to the present invention, an SOI wafer having a high interface state density (Dit) that traps carriers at the interface between the BOX layer and the base wafer without complicating the manufacturing process of the SOI wafer itself. It turns out that it can be provided.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits the same function and effect. It is included in the technical scope.

1 ... bond wafer, 2 ... base wafer,
3 ... BOX layer (silicon oxide film), 4, 14 ... Ion implantation layer, 5 ... Bond wafer after peeling, 6 ... Bonded substrate, 7, 17 ... SOI layer, 8 ... Ion implantation damage layer,
9 ... SOI wafer,
12 ... Mercury probe, 19 ... SOI wafer for evaluation, 21 ... Base wafer (temporary), 22 ... Bond wafer (temporary).

Claims (6)

At least a silicon oxide film is formed on the surface of a base wafer made of silicon single crystal, the base wafer and a bond wafer made of silicon single crystal are bonded together through the silicon oxide film, and the bond wafer is thinned to form an SOI. In a method for manufacturing an SOI wafer for forming a layer,
An SOI wafer having a resistivity of 100 Ω · cm or more and a surface roughness (Ra) of a surface to be bonded to the bond wafer of 0.1 μm or more is used as the base wafer. Production method.   The method for manufacturing an SOI wafer according to claim 1, wherein a CW wafer (chemical etching wafer) is used as the base wafer.   3. The surface of the silicon oxide film on the side to be a bonding surface with the bond wafer is polished after forming a silicon oxide film on the surface of the base wafer. Manufacturing method of SOI wafer. An SOI wafer comprising at least an SOI layer, a silicon oxide film, and a base wafer,
The base wafer is made of a silicon single crystal having a resistivity of 100 Ω · cm or more,
An SOI wafer having a surface roughness (Ra) of an interface between the base wafer and the silicon oxide film of 0.1 μm or more.   The SOI wafer according to claim 4, wherein a CW wafer (chemical etching wafer) is used as the base wafer.   6. The silicon oxide film is formed on the surface of the base wafer, and the surface to be bonded to the bond wafer is polished. SOI wafer described in 1.

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