JP3900741B2 - Manufacturing method of SOI wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a so-called hydrogen ion delamination method (also called a smart cut method) in which an ion-implanted wafer is delaminated after heat treatment to produce an SOI wafer. about the less of an SOI wafer manufacturing how.
[0002]
[Prior art]
As a method for manufacturing an SOI (silicon on insulator) wafer using a bonding method, a technique for bonding two silicon wafers through a silicon oxide film, for example, as disclosed in Japanese Patent Publication No. 5-46086, Conventionally known is a method in which an oxide film is formed on at least one wafer and adhered to each other without interposing foreign matter on the bonding surface, and then heat-treated at a temperature of 200 to 1200 ° C. to increase the bond strength. .
[0003]
Bonded wafers whose bond strength has been increased by heat treatment can be processed by subsequent grinding and polishing. Therefore, device formation is performed by reducing the thickness of the device manufacturing side wafer to the desired thickness by grinding and polishing. An SOI layer can be formed.
The bonded SOI wafer manufactured in this way has the advantages that the SOI layer has excellent crystallinity and the reliability of the buried oxide film directly under the SOI layer is high, but is thinned by grinding and polishing. In addition, it takes time to reduce the thickness of the film, and the material is wasted. Furthermore, the film thickness uniformity is only a target film thickness of ± 0.3 μm at most.
[0004]
On the other hand, with the recent increase in integration and speed of semiconductor devices, the thickness of the SOI layer is required to be further reduced and the film thickness uniformity improved, specifically 0.1 ± 0.00. A film thickness of about 01 μm and film thickness uniformity are required.
In order to realize a thin film SOI wafer having such a film thickness and film thickness uniformity with a bonded wafer, it is impossible to reduce the thickness by conventional grinding and polishing. A method called a hydrogen ion stripping method (also called a smart cut method) disclosed in Kaihei No. 5-211128 has been developed.
[0005]
In this hydrogen ion separation method, an oxide film is formed on at least one of two silicon wafers, hydrogen ions or rare gas ions are implanted from the upper surface of one silicon wafer, and a microbubble layer ( After forming the encapsulating layer, the ion-implanted surface is brought into intimate contact with the other wafer through the oxide film, and then a heat treatment (peeling heat treatment) is applied to ion-implant the wafer with the microbubble layer as the cleaved surface (peeling surface). Is formed into a thin film, and further heat treatment (bonding heat treatment) is applied to firmly bond to form an SOI wafer.
[0006]
In this method, the peeled surface is a good mirror surface, and an SOI wafer with extremely high SOI layer uniformity can be obtained relatively easily. Further, since one of the peeled wafers can be reused, the material can be used effectively. There are also advantages.
In addition, this method can directly bond silicon wafers without going through an oxide film, and not only when bonding silicon wafers, but also by ion-implanting silicon wafers, quartz, silicon carbide, alumina, etc. It is also used when bonding to insulating wafers having different thermal expansion coefficients.
[0007]
[Problems to be solved by the invention]
By the way, as a method of manufacturing an SOI wafer by the hydrogen ion delamination method, depending on whether an oxide film is formed on a bond wafer (wafer for forming an SOI layer) or a base wafer (wafer serving as a support substrate for the SOI layer). The manufacturing method is roughly classified. That is, a method of forming an oxide film only on the base wafer side where ion implantation is not performed as shown in FIG. 2A, and an oxide film is formed on the bond wafer as shown in FIG. There is a method of ion implantation.
In the case of (B), an oxide film may also be formed on the base wafer.
[0008]
Regardless of which method is used, the surface of the bond wafer into which the ion implantation has been performed is common in that it forms a bonding interface. Due to the generation of dust and surface contamination, these deposits are not easily removed even after washing, causing bonding failure and reducing the manufacturing yield of SOI wafers.
[0009]
In addition, among the manufacturing methods of FIGS. 2A and 2B, FIG. 2B is the mainstream at present. One of the reasons is that, if an oxide film is not formed on the bond wafer into which ions are implanted, the variation in ion implantation depth is deteriorated due to the channeling phenomenon, and the film thickness uniformity of the SOI layer after peeling is lowered. Because there is a possibility. Here, the channeling phenomenon refers to a phenomenon in which ions pass through meandering gaps between crystal atoms when ions are incident almost parallel to the crystal axis or plane of a crystalline substance, compared to non-parallel incidence. As a result, the variation in ion implantation depth increases.
[0010]
In the case of a silicon wafer, the surface is processed in a specific orientation (for example, <100>). Therefore, this channeling phenomenon is likely to occur, and it is preferable to suppress this channeling phenomenon by forming an oxide film.
Another reason for forming an oxide film on a bond wafer is that if an oxide film is formed on the bond wafer in advance, impurities (such as boron in the atmosphere or metal or organic matter by ion implantation) This is because (contaminants) can be prevented from diffusing into the active layer (SOI layer), and deterioration of crystallinity and electrical characteristics of the SOI layer can be prevented.
[0011]
However, the ion implantation depth variation (standard deviation σ) in the case of performing the hydrogen ion delamination method can be obtained as σ = 0.4 nm using the current ion implanter if the above-mentioned channeling phenomenon does not occur. it can. That is, since 3σ = 1.2 nm, almost all ions are implanted within the target implantation depth of ± 1.2 nm. Therefore, the thickness of the SOI layer after peeling is the target film thickness of ± 1.5 nm. An SOI wafer having the following excellent film thickness uniformity should be obtained.
[0012]
However, when an oxide film is formed on a bond wafer to be ion-implanted for the reasons described above, the thickness of the oxide film formed varies, so that ions implanted into silicon through this oxide film also have an implantation depth. Affected by.
For example, when 400 nm is required as the buried oxide film thickness of the SOI wafer, if this oxide film is formed using oxidation conditions at a normal mass production level, the variation of the oxide film thickness is only about σ = 2.0 nm. I can't get it. Even if the oxidation conditions are strictly controlled ignoring productivity, the limit is around σ = 1.0 nm, so the SOI film thickness uniformity of the SOI wafer manufactured by forming the oxide film on the bond wafer is as follows. The target film thickness was about ± 3 nm.
[0013]
The present invention has been made in consideration of the above-described problems, and reduces bonding failure, which is the biggest factor that lowers the manufacturing yield of SOI wafers. Further, the film thickness uniformity of the SOI layer is the oxide film thickness of the SOI wafer. It is an object of the present invention to provide an SOI wafer excellent in film thickness uniformity and a method for manufacturing the same so as to depend only on the implantation performance (implantation depth variation) of the ion implantation apparatus without being affected by the variation of the ion implantation apparatus. .
[0014]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the invention described in claim 1 of the present invention is to implant at least one of hydrogen ions or rare gas ions from the bond wafer surface to form a microbubble layer (implanted layer) inside the bond wafer. After the formation, a CVD oxide film is formed on the ion-implanted surface at a first temperature, the surface of the CVD oxide film is planarized, and the surface is brought into close contact with the surface of the base wafer. A method for manufacturing an SOI wafer, characterized in that a heat treatment is applied at a second temperature higher than the temperature, and the bond wafer is peeled into a thin film with a microbubble layer.
[0015]
In this way, by depositing a CVD (Chemical Vapor Deposition) oxide film (oxide film formed by the CVD method) on the surface of the bond wafer where hydrogen ions or rare gas ions are implanted, dust is generated in the ion implantation process. However, it is buried in the oxide film and is not exposed on the surface. Further, even if a convex portion is formed on the surface of the CVD oxide film due to that, it is removed in the subsequent step of flattening the surface of the CVD oxide film, so that poor bonding can be reduced. Since the CVD oxide film (buried oxide film) is formed after the hydrogen ion implantation, the uniformity of the hydrogen ion implantation becomes the film thickness uniformity of the oxide film.
[0016]
Further, the temperature (first temperature) for forming the CVD oxide film on the ion-implanted surface of the bond wafer is set to a temperature at which peeling of the microbubble layer does not occur in the formation stage of the CVD oxide film, and the temperature is claimed. If the first temperature for forming the CVD oxide film is set to 450 ° C. or lower as in Item 2, it is possible to reliably prevent the microbubble layer from peeling off in the CVD oxide film forming step.
Further, if a thermal oxide film is formed in advance on the surface of the base wafer as in claim 3, the dielectric strength of the buried oxide film of the SOI wafer can be improved and the capacitance can be adjusted.
It is to be noted that the ion implantation is preferably performed non-parallel to the crystal axis or crystal plane of the bond wafer as in the fourth aspect. As a result, the channeling phenomenon of implanted ions can be reduced, so that it is possible to prevent variations in ion implantation depth from increasing.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIG. 1, but the present invention is not limited thereto. Here, FIG. 1 is a flowchart showing an example of a manufacturing process of a bonded SOI wafer according to the present invention.
In step (a), two silicon wafers 1 and 2 are prepared, and both wafers are single crystal silicon wafers whose surfaces to be bonded are mirror-polished. In addition, 1 is a base wafer and 2 is a bond wafer.
[0018]
Step (b) is a step of implanting hydrogen ions into the bond wafer 2 to be the SOI layer. At least one of hydrogen ions or rare gas ions, here hydrogen ions, is implanted from the upper surface of one surface of the bond wafer 2 (the surface bonded to the base wafer 1), and parallel to the surface at the average ion penetration depth. The microbubble layer (encapsulation layer) 3 is formed, and the wafer temperature during this implantation is preferably 25 to 450 ° C., more preferably 200 ° C. or less.
And the energy at the time of the said ion implantation is suitably determined by the target thickness of the SOI layer of the SOI wafer to produce. Further, in order to prevent a channeling phenomenon, it is preferable to implant at an incident angle slightly inclined so as to be non-parallel to the crystal axis or crystal plane of the bond wafer 2.
[0019]
Next, step (c) is a step of depositing the CVD oxide film 4 on the surface of the bond wafer 2 into which ions have been implanted (at least the surface bonded to the base wafer). In order to prevent the occurrence of peeling in the microbubble layer 3 at the stage of forming the CVD oxide film 4, the first temperature (deposition temperature) for forming the CVD oxide film is preferably 450 ° C. or lower, for example, 400 to 450 Growth is performed by a chemical vapor deposition (CVD) method in a temperature range of ° C. As the CVD apparatus, an atmospheric pressure CVD apparatus, a low pressure CVD apparatus, a plasma CVD apparatus, or the like can be given.
Further, since this CVD oxide film 4 becomes a buried oxide film of an SOI wafer, its thickness is set according to the application, but usually about 0.1 to 2.0 μm is used.
[0020]
Step (d) is a step of planarizing the surface of the CVD oxide film 4. By depositing the CVD oxide film 4, even if dust generated in the ion implantation process adheres to the surface of the bond wafer, it is buried in the oxide film and is not exposed to the surface, thereby reducing bonding defects caused by the deposits. be able to.
However, for example, when the surface roughness of a CVD oxide film formed with an atmospheric pressure CVD apparatus is measured with an atomic force microscope at 1 μm square, the root mean square roughness (Rms) is about 1.2 nm. For this reason, it is impossible to bond with the base wafer. Accordingly, the surfaces are planarized and bonded using a method such as CMP (Chemical and Mechanical Polishing). Since the CVD oxide film is softer than the thermal oxide film and has a higher polishing rate, it can be easily planarized. At this time, even if the convex portion is formed on the surface of the CVD oxide film due to the deposit on the surface before the CVD oxide film is formed, the bonding failure can be reduced because it is removed in this flattening step.
If Rms on the surface of the CVD oxide film after depositing the CVD oxide film 4 is originally about 0.5 nm or less, the step (d) can be omitted.
[0021]
Next, the step (e) is a step in which the cleaned wafers 1 and 2 are superposed and brought into close contact with each other, by bringing the surfaces of the two wafers into contact with each other in a clean atmosphere at room temperature, and the like. Wafers are bonded to each other without using. At this time, if necessary, a thermal oxide film can be formed on the surface of the base wafer. Since the CVD oxide film 4 is inferior in electrical characteristics such as withstand voltage as compared with the thermal oxide film, the base wafer 1 is required in advance when a high withstand voltage or capacitance is required for the buried oxide film of the SOI wafer. If a thick thermal oxide film is formed, these can be satisfied.
[0022]
In the step (f), the separation wafer 5 and the SOI wafer 6 (SOI layer 7 + CVD oxide film (embedded oxide film) 4 ′ + base wafer 1) are separated by separating with the microbubble layer (encapsulation layer) 3 as a boundary. This is a peeling heat treatment step, and the heat treatment temperature (second temperature) is higher than the heat treatment temperature (first temperature) for forming the CVD oxide film 4. For example, if heat treatment is performed at a temperature of about 500 ° C. or higher in an inert gas atmosphere, the separation wafer 5 and the SOI wafer 6 are separated by crystal rearrangement and bubble aggregation, and at the same time, the adhesion surface at room temperature is also somewhat. Are firmly bonded. The peeled wafer 5 can be reused by performing a regeneration process for removing the surface oxide film and polishing the peeled surface.
[0023]
In order to use the SOI wafer 6 in the device manufacturing process, the bonding force by the peeling heat treatment in the step (f) is not sufficient. Therefore, a high-temperature heat treatment is performed as the bonding heat treatment in the step (g), and the bonding strength is sufficient. To do. This heat treatment can be performed, for example, in an inert gas atmosphere at 1000 ° C. to 1200 ° C. for 30 minutes to 5 hours. Further, if a rapid heating / rapid cooling device such as a lamp heating device is used, sufficient bond strength can be obtained at a temperature of 1000 ° C. to 1350 ° C. in a short time of about 1 to 300 seconds.
In addition, when the bonding heat treatment in the step (g) is also performed as the peeling heat treatment in the step (f), the step (f) can be omitted.
[0024]
Then, the step (h) is a step of removing the damage layer and the surface roughness present on the cleavage plane (peeling surface) which is the surface of the SOI layer 7. As this process, polishing with a very small polishing allowance called touch polishing can be performed, or heat treatment in a reducing atmosphere containing hydrogen can be performed after touch polishing, but reduction containing hydrogen without performing touch polishing. Even if only the heat treatment is performed in a neutral atmosphere, the damaged layer and the surface roughness can be removed in the same manner, and the bonding heat treatment in the step (g) can also be performed, which is more efficient.
[0025]
【Example】
(Example)
First, 20 single crystal silicon wafers having a diameter of 150 mm, a thickness of 625 μm, a crystal axis orientation <100>, a conductivity type p-type, and a resistivity of 10 to 20 Ω · cm and mirror-polished are prepared for bond wafers. The oxide film of 300 nm was formed on the surface of five of the ten wafers for base wafer by thermal oxidation.
Next, H ⁺ ions are implanted into the mirror surface of the bond wafer under conditions of an implantation energy of 40 keV, an implantation amount of 8 × 10 ¹⁶ atoms / cm ² and an implantation angle of 7 °, and then atmospheric pressure CVD using monosilane gas and oxygen gas as raw materials. A CVD oxide film having a thickness of about 400 nm was deposited at 400 ° C. using an apparatus.
When the surface roughness of the CVD oxide film surface immediately after deposition was measured with an atomic force microscope (Nano Scope-II, manufactured by Digital Instruments) at a 1 μm square, Rms = 1.2 nm.
Next, after polishing the surface of the CVD oxide film by about 100 nm by CMP, the surface roughness was measured again. As a result, Rms was improved to 0.2 nm.
[0026]
Thereafter, the bond wafer and the base wafer were washed and dried, and then adhered to each other at room temperature. A heat treatment at 500 ° C. for 30 minutes was applied as a peeling heat treatment in a nitrogen gas atmosphere.
As a result, an SOI wafer in which the film thickness of the SOI layer 7 as shown in FIG. 1F was about 0.35 μm and a release wafer were produced. The SOI wafer after peeling was observed with the naked eye, but no void (unbonded portion) was observed on any of the 10 SOI wafers regardless of the presence or absence of the thermal oxide film of the base wafer. Note that, if the SOI layer is thinned, a portion where the void is present appears to rise, so that the void can be observed without using a special apparatus.
[0027]
Next, this SOI wafer was subjected to bonding heat treatment at 1100 ° C. for 2 hours in a nitrogen gas atmosphere. The SOI wafer after the bonding heat treatment was observed with the naked eye, but no void was observed.
The film thickness of the SOI wafer produced in this way was measured to determine the film thickness uniformity. The film thickness was measured by reflection spectroscopy. Thousands of points were measured at a pitch of 1 mm except for the outer periphery of 10 mm within the surface of the SOI wafer. The average value of the measured standard deviation σ of the film thickness was 0.43 nm. Therefore, it was found that the average value of the film thickness uniformity (± 3σ) of the SOI layer of the manufactured SOI wafer was ± 1.29 nm.
[0028]
【The invention's effect】
As described above, the present invention deposits a CVD oxide film on the surface of an ion-implanted bond wafer when producing a bonded wafer by the hydrogen ion delamination method. The resulting defective coupling can be reduced, and the manufacturing yield can be greatly improved. In addition, since ion implantation is performed directly on the bond wafer surface without an oxide film, the uniformity of the SOI layer thickness is not affected by the variation in the oxide film thickness of the SOI wafer, and the implantation performance (implantation) of the ion implantation apparatus is not affected. An SOI wafer excellent in film thickness uniformity can be manufactured.
In addition, when a thermal oxide film is formed on the surface of a bond wafer to be an SOI layer as in the prior art, interstitial silicon implantation occurs during the formation of the thermal oxide film, which may induce crystal defects in the SOI layer. However, in the present invention, such interstitial silicon implantation does not occur, and there is a secondary effect that the crystallinity of the SOI layer is not deteriorated.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an example of a manufacturing process of a bonded SOI wafer according to the present invention.
FIGS. 2A and 2B are flow charts showing a method for manufacturing an SOI wafer by hydrogen ion delamination. FIG. 2A is a method in which an oxide film is formed only on the base wafer side where no ion implantation is performed, and FIG. In this method, ions are implanted after the film is formed.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base wafer 2 ... Bond wafer 3 ... Micro bubble layer (encapsulation layer) 4 ... CVD oxide film 5 ... Release wafer 6 ... SOI wafer 7 ... SOI layer

Claims (4)

  After implanting at least one of hydrogen ions or rare gas ions from the bond wafer surface to form a microbubble layer (encapsulation layer) inside the bond wafer, a CVD oxide film is formed on the ion implantation surface at a first temperature. Then, after planarizing the surface of the CVD oxide film, the surface is brought into close contact with the surface of the base wafer, and then heat treatment is performed at a second temperature higher than the first temperature to form a bond wafer with a microbubble layer. A method for producing an SOI wafer, comprising peeling off into a thin film.   The method for manufacturing an SOI wafer according to claim 1, wherein the first temperature is 450 ° C. or less.   3. The method for manufacturing an SOI wafer according to claim 1, wherein a thermal oxide film is formed in advance on the surface of the base wafer.   4. The method for manufacturing an SOI wafer according to claim 1, wherein the ion implantation is performed non-parallel to a crystal axis or a crystal plane of the bond wafer. 5.

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