JP3297600B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor substrate and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor substrate applicable to an electronic device, an integrated circuit, or the like manufactured by dielectric isolation or a single crystal semiconductor layer on an insulator, and a manufacturing method thereof.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and has many advantages that cannot be attained by a bulk Si substrate for fabricating a normal Si integrated circuit. Much research has been done because devices using SOI technology have a. That is, by using the SOI technology, for example, the following advantages can be obtained. 1. Dielectric separation is easy and high integration is possible. 2. Excellent radiation resistance. 3. Reduces stray capacitance and enables higher speed. 4. The well process can be omitted. 5. Latch-up can be prevented. 6. A fully depleted field-effect transistor is possible by thinning.

A method of forming an SOI structure having many advantages in the above-described device characteristics is described in, for example, Spec.
ial Issue: “Single-crystal”
silicon on non-single-cr
ystall insulators ”; edited
by G. by. W. cullen, Journal of C
rystal Growth, volume 63, n
o 3, pp 429-590 (1983).

[0004] In the past, a single crystal sapphire substrate was provided with Si
(Silicon on Sapphire), which is heteroepitaxially formed by CVD (Chemical Vapor Deposition), has been studied, which has achieved some success as the most heated SOT technology. Due to the large amount of crystal defects due to lattice mismatch at the substrate interface, the incorporation of aluminum from the sapphire substrate into the Si layer, and above all, the delay in increasing the cost and area of the substrate has limited the spread of its applications. Was. Under these circumstances, relatively recently, attempts have been made to realize an SOI structure without using a sapphire substrate. That is, this attempt is roughly divided into the following two.

[0005] 1. After the surface of the Si single crystal substrate is oxidized, a window is opened to partially expose the Si substrate, and that portion is used as a seed to epitaxially grow laterally to form a Si single crystal layer on SiO ₂ (in this case, , With the deposition of a Si layer on SiO ₂ ).

[0006] 2. The Si single crystal substrate itself is used as an active layer, and SiO ₂ is formed thereunder (this method does not involve the deposition of a Si layer).

Means for realizing the above item 1 include a method of directly growing a single crystal layer Si in a lateral direction by a CVD method, a method of depositing amorphous Si and performing a solid phase lateral epitaxial growth by a heat treatment, Alternatively, an energy beam such as an electron beam or a laser beam is converged and irradiated on the polycrystalline Si layer, and a single crystal layer is grown on SiO ₂ by melting and recrystallization. (Zone Melting
Recrystallization, etc. are known. Although each of these methods has advantages and disadvantages, it still has some problems in controllability, productivity, uniformity, and quality, and none of them has been industrially practically used yet. For example, in the CVD method, sacrificial oxidation is required to make the thin film flat, and in the solid phase growth method, the crystallinity is poor. The beam annealing method has a problem in controllability such as processing time by convergent beam scanning, degree of beam overlap, and focus adjustment. Zone Melting Recrytalli
The zation method is the most mature method, and a relatively large-scale integrated circuit has been prototyped using this method. However, many crystal defects such as sub-grain boundaries still remain.
Minority carrier devices have not been created yet.

As the above two examples, there are the following four types of methods.

1. An oxide film is formed on a Si single crystal substrate having a V-shaped groove anisotropically etched on its surface, and a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate, and then polished from the back surface of the Si substrate. Thereby, a dielectrically separated Si single crystal region surrounded by V grooves is formed on the thick polycrystalline Si layer.
In this method, the crystallinity is good, but the polycrystalline S
There is a problem in terms of controllability and productivity in the process of depositing i several hundred microns thick and the process of polishing a single crystal Si substrate from the back surface to leave only the separated Si active layer.

[0010] 2. Simox (SIMOX: Sepe
ratio by ion implemented
oxygen) to form a SiO ₂ layer by ion implantation of oxygen into a Si single crystal substrate.
Currently the most mature approach due to good consistency with the process. However, in order to form a SiO ₂ layer, it is necessary to implant oxygen ions at 10 ¹⁸ ions / cm ² or more, but the implantation time is long and the productivity is not high. Also, the wafer cost is high. Further, a relatively large number of crystal defects remain, and from the industrial viewpoint, the quality has not reached a sufficient level to produce a minority carrier device.

3. A method of forming an SOI structure by dielectric isolation by oxidation of a porous Si layer. This method uses P-type S
Proton ion implantation of an N-type Si layer on the surface of an i-single-crystal substrate (Imai et al., J. Crystal Growth, vo
63, 547 (1983), or an island formed by epitaxial growth and patterning, and anodized in an HF solution so as to surround the Si island from the surface.
After only the porous Si substrate is made porous, N
This is a method of dielectrically separating the Si islands. in this way,
The separated Si region is determined before the device process, which causes a disadvantage that the degree of freedom in device design is limited.

The present applicant has proposed a new method in Japanese Patent Application Laid-Open No. Hei 5-21338 as a method for solving these inconveniences.

The method disclosed in Japanese Patent Application Laid-Open No. Hei 5-21338 discloses a method in which a member having a non-porous single-crystal semiconductor region disposed on a porous single-crystal semiconductor region is formed, and a surface of the non-porous single-crystal semiconductor region is formed. A method of manufacturing a semiconductor member, comprising bonding a surface of a member having a surface made of an insulating substance, and then removing the porous single-crystal semiconductor region by etching.

The method is applicable to the production of an SOI substrate, and utilizes, for example, a silicon active layer by utilizing etching selectivity between a porous single crystal semiconductor region and a non-porous single crystal semiconductor region. Is an excellent method for obtaining an SOI substrate having a uniform layer thickness. One application example of the method disclosed in JP-A-5-21338 to an SOI substrate is roughly divided into a step of making a single-crystal silicon substrate porous, a step of epitaxially growing single-crystal silicon on a porous silicon layer, Bonding the epitaxial silicon film formed on the porous silicon layer to another substrate via the insulating layer, removing the porous silicon layer from the bonded substrate, and leaving the epitaxial silicon layer on the insulating layer; Consists of

As can be understood from this example, the method uses a single-crystal silicon layer (active layer) constituting an SOI substrate.
Can be formed using a film forming technique such as a CVD method, using a bonding step, and removing the porous silicon layer by utilizing the etching selectivity of the porous silicon layer and the single crystal silicon layer (active layer). For this reason, it is an excellent method in terms of productivity, uniformity, controllability, and economical efficiency in obtaining an Si single crystal layer having excellent crystallinity on an insulator as much as a single crystal wafer.

[0016]

Based on the method disclosed in Japanese Patent Application Laid-Open No. Hei 5-21338, the present inventors have studied to further improve the method. It was clear that there was room for improvement.

That is, the method disclosed in Japanese Patent Application Laid-Open No. Hei 5-21338 is a very excellent method when performed at a laboratory level. However, when a semiconductor member is manufactured in a large-scale factory, If the cost can be further reduced, the contribution to the development of industry will be greater.

The present inventor has studied the above method from such a viewpoint, and has found that the cost can be further reduced by considering what kind of silicon substrate is used as a porous silicon substrate. Obtained.

Here, a description will be given of making silicon (Si) porous.

An Si substrate is anodized using an HF solution (a
It can be made porous by a nodification method. This porous Si layer is made of N 2 for the following reason.
It is easier to form a P-type Si layer than a P-type Si layer.

[0021] Porous Si is manufactured by Uhlir et al.
It was discovered in 56 in the course of research on semiconductor electropolishing (A. Uhlir, Bell Syst. Tech.
J. , Vol. 35, 333 (1956).

In addition, Unagami et al.
And reported that the anodic reaction of Si in HF solution requires holes and that the reaction is as follows (T. Unagami, J. Electroc).
hem. Soc. vol. 127, 476 (198
0).

Si + 2HF + (2-n) e ⁺ → SiF ₂
+ 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λ
e ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the number of holes necessary for dissolving the Si1 atom, and it is assumed that porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type Si having holes
Is easily made porous, but N-type Si is hardly made porous. The selectivity in this porous formation has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Onaka, Kajiwara, IEICE Technical Report, vol. 79, SSD)
79-9549 (1979), (K. Imai, Sol.
id-State Electronics, vol.
24, 159 (1981).

According to observation with a transmission electron microscope, pores having an average diameter of about several tens to several hundreds of angstroms are formed in the porous Si layer, but the single crystallinity is maintained. It is possible to epitaxially grow a single crystal Si layer on top of the layer. However, if the temperature is higher than 1000 ° C., rearrangement of the internal holes occurs, and the characteristics of the accelerated etching may be impaired. For this reason, low temperature growth such as molecular beam epitaxial growth, plasma CVD, low pressure CVD, photo CVD, bias sputtering, and liquid phase growth is suitable for the epitaxial growth of the Si layer.

Further, the density of the porous layer is reduced to less than half since a large amount of voids are formed therein. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the ordinary etching rate of the single crystal layer.

Taking advantage of such characteristics of porous Si,
A bonded wafer can be manufactured by the etch-back method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 5-21338.

The porousness of a silicon substrate disclosed in Japanese Patent Laid-Open No. 21338/1993 is roughly classified as follows.

(1) A P-type substrate is prepared and all of it is made porous.

(2) A low impurity concentration layer is formed on a P-type substrate by a thin film growth method such as an epitaxial growth method, and the P-type substrate is made porous.

(3) After ion implantation of protons is performed on the surface of the P-type substrate to form an N-type single crystal layer on the surface, the portion remaining as P-type is made porous.

In the methods shown in the above (1) to (3), a P-type silicon substrate is used in all cases, and in order to make a large amount of a silicon substrate porous without variation in a large-scale factory, Since the anodization utilizes the anodic reaction of silicon, it is necessary to use a P-type silicon substrate having a strictly controlled specific resistance value. However, since a silicon substrate having a specified resistivity is relatively expensive, if a silicon substrate can be used without depending on the resistivity, the cost can be further reduced to manufacture an SOI substrate. Can be achieved.

An object of the present invention is to provide a method of manufacturing a semiconductor substrate, which is a further improvement of the method disclosed in Japanese Patent Application Laid-Open No. Hei 5-21338.

Another object of the present invention is to provide a method for manufacturing a semiconductor substrate which is further reduced in cost when manufacturing an SOI substrate.

Still another object of the present invention is to provide a method for manufacturing a semiconductor substrate suitable for manufacturing a semiconductor substrate in a factory.

[0036]

The above-mentioned object is achieved by the present invention having the following configuration.

According to the present invention, a step of forming a porous layer on a silicon substrate, a step of forming a non-porous single crystal layer on the porous layer, and bonding the non-porous single crystal layer to a support substrate Forming a bonded substrate, and a method of manufacturing a semiconductor substrate having a step of removing the porous layer, wherein the silicon substrate by diffusing an element capable of controlling the conductivity type into the silicon substrate by a diffusion method, After forming diffusion regions on a first surface side of the substrate and a second surface side opposite to the first surface side, the porous region is formed on the diffusion region on the first surface side. Forming a layer. The present invention provides a porous layer forming step of forming a porous layer on a silicon substrate, a step of forming a non-porous single crystal layer on the porous layer, and bonding the non-porous single crystal layer to a support substrate. A step of forming a bonded substrate and a step of removing the porous layer, wherein the first surface side of the silicon substrate and the first surface side are opposite to the first surface side of the silicon substrate. After forming P-type impurity regions on the second surface side located on the side,
The porous layer is formed in the P-type impurity region on the surface side of the above. The present invention provides a step of forming a porous layer on a silicon substrate, a step of forming a non-porous single crystal layer on the porous layer, and bonding the non-porous single crystal layer and a support substrate together. Forming a substrate; and
Removing a non-porous portion of the silicon substrate from the bonded substrate, and then etching and removing the porous layer, wherein the conductivity type can be controlled in the silicon substrate. After diffusing the element by a diffusion method to form a diffusion region on the first surface side of the silicon substrate, a part of the surface side of the diffusion region is made porous, and the porous layer is formed in the diffusion region. Is formed. The present invention provides a step of forming a porous layer on a silicon substrate, a step of forming a non-porous single crystal layer on the porous layer, and bonding the non-porous single crystal layer and a support substrate together. Forming a substrate, and removing a non-porous portion of the silicon substrate from the bonded substrate, and then etching and removing the porous layer. After forming a P-type impurity region on the surface side of
A part of the surface side of the P-type impurity region is made porous, and the porous layer is formed in the P-type impurity region.

The second aspect of the method for manufacturing a semiconductor substrate according to the present invention is directed to a method of manufacturing a semiconductor substrate, comprising the steps of: providing an element capable of controlling a conductivity type on a first surface side of a silicon substrate and a second surface side located behind the first surface; Forming a diffusion region by diffusing the same by a diffusion method, forming a porous layer in the diffusion region formed on the first surface side, and forming a non-porous single crystal layer on the porous layer. A step of bonding the non-porous single-crystal layer and the support substrate with an insulating layer disposed on at least one of the bonding surfaces, and a step of removing the porous layer. Is what you do.

According to the present invention having the above-described structure, the above-described object is achieved. In the present invention, a diffusion region is formed by diffusing an element whose conductivity type can be controlled by a diffusion method into a silicon substrate, and a silicon layer whose resistance value is strictly controlled since a porous layer is formed in the diffusion region. Even if a substrate is not used, porosity can be obtained in a state where variation is suppressed. That is, a relatively inexpensive silicon substrate with no resistance specified can be used.

Further, in the embodiment in which the diffusion layers are formed on both surfaces of the substrate, the distortion in forming the diffusion layers can be reduced. Thereby, the bonding step can be performed completely, and the possibility of peeling of the substrate is extremely reduced. As a result, the yield of the obtained semiconductor substrate is improved, and the cost of manufacturing the substrate can be reduced. In addition to this, the contact resistance can be reduced when the porous layer is formed using anodization.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the method for manufacturing a semiconductor substrate according to the present invention is as described above. The most characteristic feature of the manufacturing method of the present invention is that after a diffusion region is formed in a silicon substrate by a diffusion method, a porous layer is formed in the diffusion region. Based on this point, the present invention will be described below in detail with reference to FIG.

FIG. 1 is a schematic view showing one example of a method for manufacturing a semiconductor substrate according to the present invention. In the present invention, first, an element for controlling conductivity is diffused into a single crystal silicon substrate (silicon wafer) 100 by using a diffusion method (FIG. 1).
(A)).

According to the present invention, a relatively expensive single crystal whose resistance value is strictly controlled in advance is formed by forming a diffusion layer having a concentration which is easily made porous in a single crystal silicon substrate by using a diffusion method. Even without using a silicon substrate, while suppressing the variation between the silicon substrates to a small one,
Stable porosity can be achieved.

In the present invention, the element capable of controlling the conductivity type to be diffused into a silicon substrate by a diffusion method is one generally used in semiconductor process technology,
For example, it refers to the elements shown in Table 1.

[0045]

[Table 1]

As a diffusion method, it is preferable from the viewpoint of cost to employ a method capable of thermally diffusing an element capable of controlling the conductivity type into the silicon substrate. Examples of such a method include the diffusion methods shown in Table 2.

[0047]

[Table 2]

In the present invention, the porous layer is formed in the diffusion region. The formation of the porous layer is easier in the P-type diffusion region than in the n-type diffusion region. In view of this point, a list of B (boron) diffusion techniques is as shown in Table 3, for example.

[0049]

[Table 3]

In the technique shown in Table 3, the element supplied from the source is basically diffused into the silicon substrate by the heat treatment in the "furnace".

For example, the diffusion method using a spin coat film
It can be performed as follows.

A mixture of B ₂ O ₃ and an organic binder and a solvent is uniformly applied on a silicon substrate (silicon wafer) using a spinner. This is dried and fired to form a B ₂ O ₃ film on the silicon substrate. Next, a silicon substrate is placed in a furnace as shown in FIG. 6 and heat treatment is performed to diffuse boron (B). In FIG. 6, 30
1 indicates a furnace, and 302 indicates a susceptor. Reference numeral 100 denotes a silicon substrate, and one surface of the substrate is coated with a B ₂ O ₃ film 150. For example, by performing a heat treatment at about 900 ° C. to 1300 ° C. using the apparatus shown in FIG.
Boron (B) can diffuse into the silicon substrate. In this case, a diffusion region is formed not only on the surface provided with B ₂ O ₃ but also on the back surface of this surface using a B ₂ O ₃ film formed on another adjacent silicon substrate as a source source. You.

The formation of the diffusion layers on both surfaces of the silicon substrate is advantageous in that the contact resistance with the HF solution can be reduced during the formation of the porous body by anodization.

The concentration of the element which can control the conductivity type contained in the diffusion region formed in the present invention is generally
5.0 × 10 ¹⁶ / cm ^{3 to} 5.0 × 10 ²⁰ / cm ³ , preferably 1.0 × 10 ¹⁷ / cm ^{3 to} 2.0 × 1
0 ²⁰ / cm ³ range, optimally 5.0 × 10 ¹⁷ / cm 3
^{The range of 3 to} 1.0 × 10 ²⁰ / cm ³ is desirable in consideration of the porosity step and the characteristics of the epitaxial film formed on the porous silicon layer.

The thickness of the diffusion region formed in the present invention can be controlled by controlling the temperature and time of the heat treatment. The thickness of the diffusion layer is generally at least 100 °, preferably at least 500 ° and optimally at least 5000 °. However, since the formation of the porosity, which is performed after the formation of the diffusion region, easily proceeds beyond the diffusion region, it is not always necessary to form the diffusion region thicker.

In FIG. 1A, the diffusion layer 101 is formed on one surface of the silicon substrate 100. However, the diffusion layer 101 can be formed on both the surface and the back surface.

In the present invention, in principle, any single-crystal silicon substrate (silicon wafer) can be adopted as the silicon substrate on which the diffusion layer is formed. However, for the purpose of manufacturing a semiconductor substrate at low cost, a relatively inexpensive silicon substrate with no resistance specified or an I
A monitor wafer used in the C process or a so-called reclaimed wafer whose surface is polished to a level that can be re-input to the IC process after removing the surface layer of the wafer having defective elements on the surface is used. It is desirable to do.

In the present invention, the porous layer is formed after the formation of the diffusion layer.

In the present invention, the nonporous single-crystal silicon substrate (silicon wafer) is made porous by anodization (a
Nomination). The resulting porous silicon layer has an average of about 50 ° to 3 °.
A large number of holes having a diameter of about 00 ° are formed, and the layer maintains single crystallinity.

Referring to FIG. 1, a porous layer 200 is formed on a diffusion layer 101 (FIG. 1B). Here, the porous layer may be formed by making the entire diffusion layer 101 porous, leaving the diffusion layer 101 partially as shown in FIG. A part of the silicon substrate 100 may be made porous. At this time, the thickness to be made porous may be about 5 μm to 20 μm on one surface layer of the substrate. Further, the entire silicon substrate 100 may be anodized.

As for the method of forming the porous silicon layer,
This will be described with reference to FIG. Substrate 600 on which diffusion layer is formed
Is set in, for example, an apparatus as shown in FIG. That is, the surface of the substrate on which the diffusion layer is formed is in contact with the hydrofluoric acid-based solution 604, the negative electrode 606 is provided on the solution side, and the opposite side is in contact with the positive metal electrode 605. Alternatively, as shown in FIG. 7 (B), the positive electrode side 605 'may also take a potential via the solution 604'. In this case, the substrate 600 is preferably provided so that the diffusion layer faces the negative electrode 606. As the hydrofluoric acid solution 604, generally, concentrated hydrofluoric acid (49% HF) is used. Diluting with pure water (H ₂ O) is not preferable because etching occurs at a certain concentration, depending on the value of the current flowing. When bubbles are generated from the surface of the substrate 600 during anodization, alcohol can be added as a surfactant for the purpose of efficiently removing the bubbles. As the alcohol, methanol, ethanol, propanol, isopropanol and the like are used. Anodizing may be performed while stirring the solution using a stirrer instead of the surfactant. For the negative electrode 606, a material that is not eroded by the hydrofluoric acid solution, for example, gold (Au), platinum (Pt), or the like is used. The material of the positive electrode 605 may be a commonly used metal material, but the hydrofluoric acid solution 604
Reaches the positive electrode 605, the surface of the positive electrode 605 may be coated with a hydrofluoric acid-resistant metal film. The current value for performing anodization is several hundred mA / cm ² at the maximum, and the minimum value need not be zero. This value is determined within a range where good quality epitaxial growth can be performed on the surface of the porous silicon. Usually, when the current value is large, the rate of anodization increases, and at the same time, the density of the porous silicon layer decreases. That is, the volume occupied by the holes increases. This changes the conditions for epitaxial growth. In the present invention, the porosity of the porous silicon layer
The ty: pore volume / (residual silicon volume + pore volume)) is generally 50% or less, preferably in the range of 1% to 40%, and most preferably in the range of 5% to 30%. It is desirable in consideration of the characteristics and the manufacturing cost.

The porous layer 101 formed as described above
A non-porous single-crystal silicon layer 102 is epitaxially grown thereon (FIG. 1C).

When a single-crystal semiconductor layer is formed over a porous layer, a CVD (Chemical Vapor D)
deposition) method, MBE (Molecular)
A general epitaxial crystal growing method such as a beam epitaxy method and a bias sputtering method can be employed.

Next, an insulating layer 103 is formed on the surface of the epitaxial layer 102 (FIG. 1D).
A deposited film (for example, SiO ₂ film or Si ₃
(N ₄ film), or it can be formed by thermally oxidizing the surface of the epitaxial layer 102. When an insulating layer is formed on the epitaxial layer 102, segregation of impurities at the bonding interface and dangling bonds of atoms at the interface tend to occur when the epitaxial layer is directly bonded to the supporting substrate in the next step. This is advantageous because the possibility of instability of the thin film device characteristics caused by the increase can be reduced. The step of forming a SiO ₂ film on the surface of the epitaxial silicon layer 102 is not essential, and may be omitted if a device configuration that does not cause a problem with the above phenomenon is considered. Where S
The iO ₂ layer 103 functions as an insulating layer of the SOI substrate. The insulating layer needs to be formed on at least one surface of the substrate to be bonded, and there are various modes for forming the insulating layer. Further, the insulating layer is not limited to the SiO ₂ layer.

In the case of oxidation, the thickness of the oxide film only needs to be thick enough not to be affected by contamination from the air taken into the bonding interface.

Next, a Si substrate serving as a support substrate is provided separately from the substrate 100 having the oxidized epitaxial surface.
A substrate 110 having an O ₂ layer 104 on its surface is prepared. The support substrate 110 includes a substrate obtained by oxidizing (including thermal oxidation) the surface of a silicon substrate, quartz glass, crystallized glass, and a substrate obtained by depositing SiO ₂ on an arbitrary substrate. here,
A silicon substrate without the SiO ₂ layer 104 may be used.

FIG. 1E shows the two prepared substrates which are cleaned and then bonded. The cleaning method is performed in accordance with a general step of cleaning a semiconductor substrate (for example, before oxidation).

Pressing the entire surface of the substrate after bonding has the effect of increasing the bonding strength.

By subjecting the bonded substrates to heat treatment, the bonding strength can be increased. It is preferable that the heat treatment temperature is high. However, if the heat treatment temperature is too high, the porous layer 101 may cause a structural change or impurities contained in the substrate may diffuse into the epitaxial layer. You need to choose a time. Specifically, 60
About 0 to 1100 ° C is preferable. Some substrates cannot be heat-treated at high temperatures. For example, when the support substrate 110 is made of quartz glass, heat treatment can be performed only at a temperature of about 200 ° C. or less due to a difference in thermal expansion coefficient between silicon and quartz. If the temperature is exceeded, the bonded substrates are peeled off or broken by stress. However, the heat treatment is only required to withstand the stress at the time of grinding or etching the bulk silicon 100 performed in the next step. Therefore, even at a temperature of 200 ° C. or less, the process can be performed by optimizing the surface treatment conditions for activation.

Next, the silicon substrate portion 100 and the porous portion 200 are selectively removed while leaving the epitaxial growth layer 102 (FIG. 1F). Thus, an SOI substrate is obtained.

Here, when the entire silicon substrate 100 is made porous, it is not necessary to remove the silicon substrate.

In the present invention, when selectively removing the porous layer, etching can be suitably used.
Examples of the etchant include a normal Si etchant, hydrofluoric acid as a selective etchant for porous Si, a mixed solution obtained by adding at least one of alcohol and hydrogen peroxide to hydrofluoric acid, and buffered hydrofluoric acid. Alternatively, a mixed solution obtained by adding at least one of an alcohol and a hydrogen peroxide solution to buffered hydrofluoric acid can be used. Since the porous Si layer has an enormous surface area, it is possible to selectively etch the porous Si even with an ordinary Si etching liquid.

In the example shown in FIG. 1, 102 has been described as an epitaxial silicon layer.
It can be composed of a single-crystal compound semiconductor of I-VI group, III-V group, or the like, or these compound semiconductor layers can be stacked on the epitaxial silicon layer.

Further, the following steps may be added to the steps described above.

(1) Oxidation (pre) of the inner wall of the pore of the porous layer
Oxidation) The thickness of the wall between adjacent holes in the porous silicon layer is very thin, from several nm to several tens of nm. For this reason, when the porous layer is subjected to a high-temperature treatment, such as during the formation of an epitaxial silicon layer or during heat treatment after bonding, the pore walls are agglomerated due to agglomeration of the pore walls, thereby closing the pores and closing the pores, thereby lowering the etching rate. There is. Therefore, after the formation of the porous layer, a thin oxide film can be formed on the hole walls to suppress the coarsening of the holes. However, since it is necessary to epitaxially grow a non-porous single-crystal silicon layer on the porous layer, only the surface of the inner wall of the pore is oxidized inside the pore wall of the porous layer so that the single crystal remains. There is a need to. It is desirable that the oxide film formed here has a thickness of several to several tens of mm. An oxide film having such a thickness is formed in an oxygen atmosphere at 2
More preferably, the temperature is from 250 ° C to 5 ° C.
It is formed by heat treatment at a temperature of 00 ° C.

(2) Hydrogen baking treatment The present inventors have previously disclosed in EP 553 852 A2 a heat treatment in a hydrogen atmosphere to remove minute roughness on the silicon surface and obtain a very smooth silicon surface. That was shown. Also in the present invention, baking in a hydrogen atmosphere can be applied. The hydrogen baking can be performed, for example, after the formation of the porous silicon layer and before the formation of the epitaxial silicon layer, or separately from the SOI substrate obtained after the porous silicon layer is removed by etching. Depending on the hydrogen baking process performed before the formation of the epitaxial silicon layer, a phenomenon occurs in which the outermost surface of the hole is closed due to migration of silicon atoms constituting the porous silicon surface. When the epitaxial silicon layer is formed in a state where the outermost surface of the hole is closed, an epitaxial silicon layer with less crystal defects can be obtained. On the other hand, depending on the hydrogen baking performed after the etching of the porous silicon layer, the action of smoothing the somewhat roughened epitaxial silicon surface due to the etching and the step of removing boron in the clean room that is inevitably taken into the bonding interface during bonding are called. There is action.

While one example of the method for manufacturing a semiconductor substrate of the present invention has been described with reference to FIG. 1, an embodiment in which the structure of the members to be bonded is different will be described below.

Embodiment 2 The embodiment shown in FIG. 2 will be described. 2 which are the same as those in FIG. 1 indicate the same parts in FIG. In the example shown in FIG. 1, the surfaces of the two substrates to be bonded are the insulating layer (SiO ₂ layer) 103 and the insulating layer (SiO ₂ layer) 104, but both surfaces need not necessarily be the insulating layers. Instead, at least one surface may be formed of an insulating layer (for example, SiO ₂ ). In the embodiment shown here, the surface of the epitaxial silicon layer 1102 (FIG. 2C) formed over the porous silicon layer is bonded to the surface of the insulating film 1104 (eg, an oxide film) formed over the silicon substrate 1110 ( 2D) and a silicon substrate 1110 in which the surface of an insulating film 1103 (eg, an oxide film formed by thermally oxidizing the surface) on the epitaxial silicon layer 1102 (FIG. 2F) is not oxidized. It is bonded to the surface (FIG. 2 (G)). In the embodiment shown here, the other steps can be performed in the same manner as in the example shown in FIG.

Embodiment 3 The embodiment shown in FIG. 3 will be described. 3 which are the same as those in FIG. 1 indicate the same parts as those in FIG. In the embodiment shown here, a glass material 1210 such as quartz glass or blue plate glass (FIGS. 3D and 3F) is attached to a substrate to be bonded to a substrate (FIGS. 3C and 3F) on which an epitaxial silicon film is formed. G)) is used. As this mode, an epitaxial silicon layer 1102 (FIG. 3C) is bonded to a glass substrate 1210 (FIG. 3D), or an insulating film 1103 on the epitaxial silicon layer 1102 (for example, by thermally oxidizing the surface). The formed oxide film) (FIG. 3F) and the glass substrate 1
210 (FIG. 3G).

In the embodiment shown here, the other steps are the same as those shown in FIG.
Can be performed similarly to the example shown in FIG.

Next, an embodiment in which diffusion layers are formed on two surfaces of a silicon single crystal substrate will be described.

Embodiment 4 A description will be given with reference to FIGS.

In this embodiment, first, a diffusion layer 101 (for example, a P ⁺ layer) is formed on the first surface side of the silicon single crystal substrate 100 and on the second surface side located on the back side of the first surface ( FIG. 4 (a).

Next, one diffusion layer 101 is made porous to form a porous layer 200 (FIG. 4B). Porous 200
May be formed by making the entire region of the diffusion layer 101 porous, or may be formed by leaving the region of the diffusion layer 101 as shown in FIG. Next, the single crystal semiconductor layer 102 is formed over the porous layer 200 (FIG. 4C). The single crystal semiconductor layer 102 can be made of silicon, but can be made of a compound semiconductor of II-VI group, III-V group, or the like instead. After that, the single crystal semiconductor layer 10
2 is bonded to the support substrate 300 (FIG. 4).
(D)). The support substrate 300 may be configured by disposing the insulating layer 104 on the surface of the silicon substrate 110. For example, the support substrate 300 may be a single glass substrate having a light transmitting property, a single non-transmitting insulator, or a laminate thereof. The substrate may be constituted, in other words, any substrate may be used as long as its surface is made of an insulating material. Specific bonding means include anodic bonding, pressing, heat treatment, or a combination thereof.
Next, the diffusion layer 101 silicon substrate 1
00 and the porous layer 200 are removed (FIG. 4E). For the removal here, a chemical method using etching or the like can be employed in addition to a mechanical method such as grinding and polishing.

In FIG. 5, the same parts as those shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. Step (d) is performed for the example shown in FIG.
Is different from the example shown in FIG. 4 in that the insulating layer 103 is attached to a supporting substrate 300 after the insulating layer 103 is formed over the single crystal semiconductor layer 102. In this example, the support substrate 300 may be a silicon substrate alone, a glass substrate alone, or a laminate of a film and a substrate on them.

Also in this embodiment, the method for forming the diffusion layer is shown in FIG.
Can be performed in the same manner as described in the description using. In addition, the various steps described in the embodiment in which the diffusion layer is formed on one side of the silicon substrate can be adopted in this embodiment.

In this embodiment in which the diffusion layers are formed on both sides of the substrate, there is an effect of reducing the contact resistance during anodization and an effect of reducing the strain during the formation of the diffusion layers.

[0088]

EXAMPLES Hereinafter, the present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples.

(Example 1) A single-crystal Si substrate having no resistance specified was prepared, and P ⁺ was deposited on the first surface side of the substrate by a diffusion method.
A high concentration layer was formed with a thickness of 5 μm.

The formation of the P ⁺ high concentration layer by the diffusion method was performed as follows. That is, a solution obtained by dissolving B ₂ O ₃ in a solvent was applied to the main surface side of the Si substrate by spin coating. Next, calcination was performed at a temperature of 140 ° C. to evaporate the solvent. The substrate thus obtained was placed in a diffusion furnace, and the inside of the furnace tube was maintained at a temperature of 1200 ° C. for 6 hours, so-called drive-in diffusion was performed to form a P ⁺ high concentration layer.

Next, the Si substrate on which the P ⁺ high concentration layer was formed was immersed in an HF solution, and anodized from the first surface side to form a porous layer on the first surface side. The conditions of the anodization were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 11 (min) Thickness of porous Si: 12 (μm)

Next, the substrate on which the porous layer was formed was subjected to an oxidation treatment at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner wall of the porous Si hole was covered with a thermal oxide film. After this, a CVD (Chemical) is formed on the porous Si layer.
A single-crystal Si layer was epitaxially grown to a thickness of 0.2 μm by using a Vapor Deposition method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ Gas flow rate: 0.5 / 180 (l / min) Gas pressure: 80 (Torr) Temperature: 950 (° C.) Growth rate: 0.3 (μm / min)

Subsequently, a 50 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

Next, the surface of the SiO ₂ layer and the surface of the separately prepared second Si substrate on which a 500 nm SiO ₂ layer was formed were brought into contact with each other, and then heat-treated at 900 ° C. for 2 hours. Lamination was performed. As a result, a bonded substrate was obtained.

Next, the side of the bonded substrate on which the P ⁺ layer is formed is ground and polished to remove the P ⁺ layer and the non-porous single-crystal Si region, exposing the entire surface of the porous Si layer. Was.

Next, the exposed porous Si layer was selectively etched using a mixed solution of 49% hydrofluoric acid and 30% hydrogenated aqueous solution. As a result, the single-crystal Si layer remained without being etched, and the porous Si was selectively etched using the single-crystal Si layer as an etch stop material, and was completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power. (about nm) is a practically negligible decrease in film thickness.

By a series of these steps, a single-crystal Si layer having a thickness of 0.2 μm can be formed on the Si oxide film.
A so-called SOI substrate was obtained. When a cross section of this SOI substrate was observed using a transmission electron microscope, no new crystal defects were introduced into the single-crystal Si layer, and it was confirmed that good crystallinity was maintained.

(Example 2) Production of an SOI substrate in the same manner as in Example 1 except that a spin coat film using B ₂ O ₃ was formed on the front surface and the back surface of the Si substrate, and a scattering region was formed. Was done. Observation of the obtained SOI substrate in the same manner as in Example 1 confirmed that the single-crystal Si thin film was an excellent one with extremely few defects.

Example 3 A spin-coat film was formed using a paste obtained by adding an organic binder and a solvent to B ₂ O ₃ , and a diffusion region was formed by arranging 10 Si substrates in a diffusion furnace. An SOI substrate was manufactured in the same manner as in Example 1 except that the manufacturing was performed.

In the case of this example, B on the adjacent silicon substrate
Diffusion layers were formed on both surfaces of the silicon substrate by vapor phase diffusion from the ₂ O ₃ film. It was confirmed that the SOI substrate obtained in this example was also excellent with very few defects.

Example 4 A single-crystal Si substrate with no resistance specified was prepared, and a P ⁺ high-concentration layer having a thickness of 5 μm was formed on the first front side and the rear side of the substrate by a diffusion method. .

The formation of the P ⁺ high concentration layer by the diffusion method was performed as follows. That is, after setting the Si substrate in the furnace core tube, N ₂ gas is introduced into the liquid diffusion source containing BBr ₃ , bubbling is performed, and the vaporized gas is mixed with the carrier gas (N ₂ + O ₂ ) in the furnace core tube. Was introduced. After the B ₂ O ₃ layer was formed by maintaining the inside of the furnace core at a temperature of 1050 ° C. for 1 hour, the inside of the furnace core was then maintained at a temperature of 1200 ° C. for 6 hours, so-called drive-in diffusion was performed, and the P ⁺ high concentration was obtained. A layer was formed.

Next, the Si substrate on which the P ⁺ high concentration layer was formed was immersed in an HF solution and anodized from the first surface side to form a porous layer on the first surface side. The conditions of the anodization were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 11 (min) Thickness of porous Si: 12 (μm)

Next, the substrate on which the porous layer was formed was subjected to an oxidation treatment at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner wall of the porous Si hole was covered with a thermal oxide film. After this, a CVD (Chemical) is formed on the porous Si layer.
A single-crystal Si layer was epitaxially grown to a thickness of 0.2 μm by using a Vapor Deposition method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ Gas flow rate: 0.5 / 180 (l / min) Gas pressure: 80 (Torr) Temperature: 950 (° C.) Growth rate: 0.3 (μm / min)

Subsequently, a 50 nm SiO ₂ layer was formed on the surface of the epitaxial Si layer by thermal oxidation.

Next, the surface of the SiO ₂ layer and the surface of a separately prepared second Si substrate on which a 500 nm SiO ₂ layer was formed were brought into contact with each other, and then heat-treated at 900 ° C. for 2 hours. Lamination was performed. As a result, a bonded substrate was obtained.

Next, the side of the bonded substrate on which the P ⁺ layer is formed is ground and polished to remove the P ⁺ layer and the non-porous single-crystal Si region, thereby exposing the entire surface of the porous Si layer. Was.

Next, the exposed porous Si layer was selectively etched using a mixed solution of 49% hydrofluoric acid and 30% hydrogenated aqueous solution. As a result, the single-crystal Si layer remained without being etched, and the porous Si was selectively etched using the single-crystal Si layer as an etch stop material, and was completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching liquid is extremely low, and the selectivity with respect to the etching rate of the porous layer reaches more than the tenth power. (about nm) is a practically negligible decrease in film thickness.

Through a series of these steps, a single-crystal Si layer having a thickness of 0.2 μm can be formed on the Si oxide film.
A so-called SOI substrate was obtained. When a cross section of this SOI substrate was observed using a transmission electron microscope, no new crystal defects were introduced into the single-crystal Si layer, and it was confirmed that good crystallinity was maintained.

In the case of this example, since the P ⁺ layers are formed on both sides of the substrate, the contact resistance during the formation of the porous layer can be reduced, and the strain accompanying the formation of the P ⁺ layer can be alleviated. A substrate and an SOI substrate were formed.

Example 5 (i) Anodizing conditions were as follows.

Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 12 (min) Thickness of porous Si: 10 (μm)

(Ii) MOCVD (Me) on porous Si
tal Organic Chemical Vapo
Single-crystal GaAs was epitaxially grown to a thickness of 1 μm under the following conditions by using an r deposition method.

Source gas: TMG / AsH ₃ / H ₂ Gas pressure: 80 (Torr) Temperature: 700 (° C.)

(Iii) The surface of the GaAs layer and the surface of a separately prepared Si substrate on which a 500 nm SiO ₂ layer was formed were brought into contact with each other, and then heat-treated at 700 ° C. for 2 hours for bonding. thing.

A semiconductor substrate was manufactured in the same manner as in the process shown in Example 4 except for the above items i) to iii), and a single-crystal Ga having a thickness of 1 μm was formed on the Si oxide film.
A substrate provided with an As layer was obtained. When a cross section of the obtained substrate was observed using a transmission electron microscope, no new crystal defects were introduced into the single crystal GaAs layer, and it was confirmed that good crystallinity was maintained.

Also in the case of this example, the strain accompanying the formation of the P ⁺ layer could be relaxed, and the semiconductor substrate could be obtained extremely stably.

Example 6 (i) Anodizing conditions were as follows.

Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 12 (min) Thickness of porous Si: 10 (μm)

(Ii) CVD (Chem) on porous Si
The single-crystal Si layer was epitaxially grown to a thickness of 0.2 μm under the following conditions by using an ideal vapor deposition method.

Source gas: SiH ₂ Cl ₂ / H ₂ Gas flow rate: 0.25 / 230 (l / min) Gas pressure: 760 (Torr) Temperature: 1040 (° C.) Growth rate: 0.14 (μm / min)

An SOI substrate was fabricated in the same manner as in the process of Example 4 except for the items (i) and (ii) described above, and a single layer having a thickness of 0.2 μm was formed on the Si oxide film. A substrate provided with a crystalline Si layer was obtained.

When the cross section of the obtained substrate was observed using a transmission electron microscope, no new crystal defects were introduced into the single crystal layer, and it was confirmed that good crystallinity was maintained.

Example 7 (i) The thickness of the P ⁺ high-concentration layer by the diffusion method was 10 μm.

(Ii) Anodizing conditions were as follows.

Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 12 (min) Thickness of porous Si: 10 (μm)

(Iii) CVD (Ch) on the porous Si layer
A single-crystal Si layer was epitaxially grown to a thickness of 0.2 μm using an electronic vapor deposition method under the following conditions.

Source gas: SiH ₂ Cl ₂ / H ₂ Gas flow rate: 0.4 / 230 (l / min) Gas pressure: 80 (Torr) Temperature: 900 (° C.) Growth rate: 0.13 (μm / min)

(Iv) After forming a 50 nm SiO ₂ layer on the surface of the epitaxial Si layer by thermal oxidation,
_{The two-} layer surface and the surface of the separately prepared quartz substrate were overlapped, and thinning and heat treatment (maximum temperature: 400 ° C.) were alternately performed to perform bonding.

A semiconductor substrate was manufactured in the same manner as in the process of Example 4 except for the items (i) to (iv) described above, and a single layer having a thickness of 0.2 μm was formed on the Si oxide film. A semiconductor substrate provided with a crystalline Si layer was obtained.

When a cross section of the obtained substrate was observed using a transmission electron microscope, no new crystal defects were introduced into the single crystal layer, and it was confirmed that good crystallinity was maintained.

Example 8 Except that the surface of the GaAs layer was superimposed on the surface of a separately prepared quartz substrate, and thinning and heat treatment (maximum temperature: 400 ° C.) were performed alternately, and bonding was performed. A semiconductor substrate was produced in the same manner as in Example 5. In this example, as in Example 5, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

Example 9 (i) Anodizing conditions were as follows.

Current density: 5 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 12 (min) Thickness of porous Si: 10 (μm)

(Ii) After forming a 50 nm SiO ₂ layer on the surface of the epitaxial Si layer by thermal oxidation,
_A semiconductor substrate was prepared in the same manner as in Example 1 except that the _two- layer surface and the surface of a separately prepared quartz substrate were overlapped, and thinning and heat treatment (maximum temperature: 400 ° C.) were alternately performed and bonded. Was prepared. In this example, as in Example 4, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

Example 10 (i) A recycled single crystal Si substrate was used.

(Ii) The thickness of the P ⁺ high concentration layer formed by the diffusion method is 10 μm.

(Iii) CVD (Che) on porous Si
A single-crystal Si layer was epitaxially grown to a thickness of 0.2 μm by the following conditions using a physical vapor deposition (Metal Vapor Deposition) method.

Source gas: SiH ₂ Cl ₂ / H ₂ Gas flow rate: 0.25 / 230 (l / min) Gas pressure: 760 (Torr) Temperature: 1040 (° C.) Growth rate: 0.14 (μm / min)

A semiconductor substrate was manufactured in the same manner as in Example 4, except for the items (i), (ii), and (iii).
In this example, as in Example 4, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

(Example 11) A semiconductor substrate was produced in the same manner as in Example 5 except that a recycled single crystal Si substrate was used and a P ⁺ high concentration layer was formed thereon. In this example, as in Example 5, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

(Example 12) A semiconductor substrate was produced in the same manner as in Example 6, except that a recycled single crystal Si substrate was used and a P ⁺ high concentration layer was formed thereon. In this example, as in Example 6, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

(Example 13) A semiconductor substrate was produced in the same manner as in Example 9 except that a recycled single crystal Si substrate was used and a P ⁺ high concentration layer was formed thereon. In this example, as in Example 9, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

(Example 14) A semiconductor substrate was produced in the same manner as in Example 5 except that a recycled single crystal Si substrate was used and a P ⁺ high concentration layer was formed thereon. In this example, as in Example 9, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

(Example 15) CVD (C
chemical Vapor Deposition)
Conditions for forming and growing single-crystal Si by the following method were as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ Gas flow rate: 0.25 / 230 (l / min) Gas pressure: 760 (Torr) Temperature: 1040 (° C.) Growth rate: 0.14 (μm / min)

A semiconductor substrate was manufactured in the same manner as in Example 13 except for this. In this example, as in Example 13, a substrate provided with an excellent crystalline semiconductor layer could be formed stably.

[0154] without forming the SiO ₂ layer on the surface of (Example 16) epitaxial Si layer, the epitaxial Si layer, as in Example 4 except that bonded to the Si substrate with the SiO ₂ layer separately prepared Thus, an SIO substrate was formed. Also in this example, an SOI substrate having excellent crystallinity was obtained.

[0155] (Example 17) SiO ₂ in which the SiO ₂ layer obtained by epitaxial Si layer by thermal oxidation, separately prepared
No layer is formed. An SIO substrate was formed in the same manner as in Example 4 except that the substrate was bonded to a Si substrate. Also in this example, an SOI substrate having excellent crystallinity was obtained.

(Example 18) 1) First, a P ⁺ diffusion layer was formed in a silicon wafer by using the method shown in Example 1.

2) 49% HF and ethyl alcohol:
In a solution mixed at a ratio of 1, the silicon wafer was set as an anode and a 5-inch diameter platinum plate was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution.
Current density 10 mA / c between the silicon wafer and platinum
An electric current was applied at m ² for 12 minutes, the silicon wafer was anodized, and the surface layer was made of silicon having a thickness of 12 μm. The wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%.

3) Subsequently, oxidation treatment was performed for 1 hour in an oxygen atmosphere at 400 ° C. on the wafer having the porous silicon layer formed thereon. Since this oxidation process forms only an oxide film of about 50 ° or less, only a silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside.

4) The wafer was exposed to an HF aqueous solution diluted to 1.25% for about 30 seconds, and then washed with water to remove the ultrathin silicon oxide film formed on the surface of the porous layer.

5) Place the wafer in a CVD growth furnace,
The following heat treatment was performed continuously.

A) Temperature: 1120 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 l / min Time: 7.5 minutes b) Temperature: 900 ° C. Pressure: 80 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.4 (1 / mi
n) By this heat treatment, a single-crystal silicon layer having a thickness of about 0.29 μm was formed.

6) Subsequently, the wafer was exposed to a mixed atmosphere of oxygen and hydrogen at 900 ° C., and the single crystal silicon layer was oxidized to form a silicon oxide film having a thickness of 200 nm.

7) This wafer is subjected to chemical cleaning for use in a normal semiconductor process together with the second Si wafer,
As a final chemical cleaning, the wafer was dipped in a dilute HF solution, rinsed with pure water, dried, and then gently brought into contact with the surfaces of the two wafers. Then 1
A heat treatment at 180 degrees for 5 minutes was applied.

8) Next, the back side of the wafer having the porous silicon was ground to expose the porous silicon on the entire surface of the substrate. Thereafter, when the wafer is immersed in a mixed aqueous solution of HF and H ₂ O ₂ for about 2 hours, the porous silicon is etched and disappears, and an epitaxial layer having a thickness of about 0.2 μm is formed on the second substrate via a silicon oxide film. The silicon layer has been relocated.

9) This substrate was placed in a 100% hydrogen atmosphere
Heat treatment was performed at 100 degrees for 4 hours.

10) Nomarski differential interference optical microscope Observation of the entire surface of the epitaxial silicon layer confirmed that an SOI substrate with extremely few defects was obtained.

Example 19 A spin coat film was formed and fired on the first surface side of a single crystal Si substrate in the same manner as in Example 1. The wafer was then placed in a furnace core tube and, as shown in Example 4, this time
A diffusion layer was formed on the back surface of the single crystal Si substrate.

Subsequently, an SOI substrate was manufactured by the same steps as those shown in the fourth embodiment. The obtained SOI substrate was excellent in crystallinity.

[0169]

According to the present invention, a diffusion region is formed by diffusing an element whose conductivity type can be controlled into a silicon substrate using a diffusion method, and a porous layer is formed in the region. The porosity can be increased in a state where the variation is suppressed without using a silicon substrate whose strictness is controlled. That is, a relatively inexpensive silicon substrate with no resistance specified can be used. Further, in the aspect in which the diffusion layers are formed on both surfaces of the substrate, the distortion during the formation of the diffusion layers can be reduced. Thereby, the laminating step can be completely performed, and the possibility of peeling of the substrate is extremely reduced. As a result, the yield of the obtained semiconductor substrate is improved, and the cost of manufacturing the substrate can be reduced. In addition to this, the contact resistance can be reduced when the porous layer is formed using anodization.

[Brief description of the drawings]

FIG. 1 is a schematic view showing one example of a method for manufacturing a semiconductor substrate of the present invention.

FIG. 2 is a schematic view illustrating one example of a method for manufacturing a semiconductor substrate of the present invention.

FIG. 3 is a schematic view illustrating one example of a method for manufacturing a semiconductor substrate of the present invention.

FIG. 4 is a schematic view illustrating one example of a method for manufacturing a semiconductor substrate of the present invention.

FIG. 5 is a schematic view showing one example of a method for manufacturing a semiconductor substrate of the present invention.

FIG. 6 is a schematic view showing an example of a diffusion step applicable to the present invention.

FIG. 7 is a schematic view showing an example of an anodizing apparatus applicable to the method for producing a semiconductor substrate of the present invention.

Continuation of the front page (56) References JP-A-5-21338 (JP, A) JP-A-5-217828 (JP, A) JP-A-6-163341 (JP, A) JP-A-7-142502 (JP) JP-A-6-244388 (JP, A) JP-A-7-176487 (JP, A) JP-A-5-217821 (JP, A) JP-A-5-217990 (JP, A) JP-A-62-108539 (JP, A) Takao Abe et al., "Silicon Crystals and Doping," Second Edition, Maruzen Co., Ltd., March 25, 1988, p. P. Holmstrom, et. Al. , "Complete Die Electric Isolation by Highly Selective and Self-Stopping Formation of the Oxidized Porous Silicon", Appl. Phys. Let t. , December 31, 1983, vol. 42, No. 4, pp. 386-388 (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/12 H01L 21/02 H01L 21/22-21/24 H01L 21/304 H01L 21/306-21/3063 H01L 21 / 308

Claims (22)

(57) [Claims] A step of forming a porous layer on a silicon substrate; a step of forming a non-porous single crystal layer on the porous layer; and bonding the non-porous single crystal layer to a support substrate. A step of forming a bonded substrate, and a method of manufacturing a semiconductor substrate having a step of removing the porous layer, wherein an element capable of controlling a conductivity type is diffused into the silicon substrate by a diffusion method. The first surface side,
And forming a diffusion region on the second surface side opposite to the first surface side, and then forming the porous layer on the diffusion region on the first surface side. Of manufacturing a semiconductor substrate. 2. A step of forming a porous layer on a silicon substrate; a step of forming a non-porous single crystal layer on the porous layer; and bonding the non-porous single crystal layer and a support substrate together. In a method for manufacturing a semiconductor substrate, comprising: a step of forming a bonding substrate; and a step of removing the porous layer, wherein the silicon substrate is located on a first surface side and on a side opposite to the first surface side. Forming a P-type impurity region on the second surface side, and then forming the porous layer in the P-type impurity region on the first surface side. 3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the non-porous single-crystal layer and the supporting substrate are bonded together with an insulating layer interposed therebetween. 4. The concentration of an element capable of controlling the conductivity type contained in the diffusion region or the concentration of boron contained in the P-type impurity region is from 5.0 × 10 ¹⁶ / cm ^{3 to} 5. ^3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the range is 0 × 10 ²⁰ / cm ^{3. 4} . 5. The concentration of an element capable of controlling the conductivity type contained in the diffusion region or the concentration of boron contained in the P-type impurity region is 1.0 × 10 ¹⁷ / cm ^{3 to} 2. ^3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the range is 0 × 10 ²⁰ / cm ^{3. 4} . 6. The concentration of an element capable of controlling the conductivity type contained in the diffusion region or the concentration of boron contained in the P-type impurity region is from 5.0 × 10 ¹⁷ / cm ^{3 to} 1. ^3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the range is 0 × 10 ²⁰ / cm ^{3. 4} . 7. The method for manufacturing a semiconductor substrate according to claim 1, wherein the thickness of the diffusion region or the P-type impurity region is 50 nm or more. 8. The method according to claim 1, wherein the porosity of the porous layer is 50% or less. 9. The porosity of the porous layer is from 1% to 40%.
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the ratio is in the range of%. 10. The porosity of the porous layer is 5% to 3%.
3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the range is 0%. 11. The method for manufacturing a semiconductor substrate according to claim 1, wherein the porous layer is formed in a part of the diffusion region or the P-type impurity region. 12. The method for manufacturing a semiconductor substrate according to claim 1, wherein the non-porous single-crystal layer is formed by oxidizing an inner wall of a hole of the porous layer and thereafter epitaxially growing the inner wall. 13. The method for manufacturing a semiconductor substrate according to claim 1, wherein the non-porous single-crystal layer is formed by subjecting the porous layer to a heat treatment in an atmosphere containing hydrogen and then epitaxially growing the same. 14. The non-porous single crystal layer is epitaxially grown after a step of forming an acid film on inner walls of pores of the porous layer and a step of heat-treating the porous layer in an atmosphere containing hydrogen. The method for manufacturing a semiconductor substrate according to claim 1, wherein: 15. The removal of the porous layer may be performed by mixing at least one of alcohol or hydrogen peroxide with hydrofluoric acid, buffered hydrofluoric acid, or at least one of alcohol or hydrogen peroxide with buffered hydrofluoric acid. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the method is performed by using any one of the mixed liquids to which is added. 16. The method of manufacturing a semiconductor substrate according to claim 1, wherein after removing the porous layer, the non-porous single crystal layer disposed on the support substrate is heat-treated in a hydrogen atmosphere. 17. A method for preparing a plurality of silicon substrates on which a solid substance for supplying an element capable of controlling the conductivity type is provided on the first surface side, and performing a heat treatment by arranging the plurality of silicon substrates in a furnace. The first surface side and the second surface side
2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the diffusion region is formed on a surface side of the semiconductor substrate. 18. The method for manufacturing a semiconductor substrate according to claim 2, wherein the P-type impurity region is formed by diffusing boron into a single crystal silicon substrate. 19. The method according to claim 2, wherein the silicon substrate is P-type, and the P-type impurity concentration of the P-type impurity region is higher than the P-type impurity concentration. 20. A step of forming a porous layer on a silicon substrate; a step of forming a non-porous single crystal layer on the porous layer; and bonding the non-porous single crystal layer and a support substrate together. Forming a bonded substrate; and removing a non-porous portion of the silicon substrate from the bonded substrate, and then etching and removing the porous layer. After diffusing an element capable of controlling the conductivity type into the substrate by a diffusion method to form a diffusion region on the first surface side of the silicon substrate, a part of the surface side of the diffusion region is made porous, A method for manufacturing a semiconductor substrate, comprising forming the porous layer in the diffusion region. 21. A step of forming a porous layer on a silicon substrate; a step of forming a non-porous single crystal layer on the porous layer; and bonding the non-porous single crystal layer and a support substrate together. Forming a bonded substrate; and removing a non-porous portion of the silicon substrate from the bonded substrate, and then etching and removing the porous layer. After forming a P-type impurity region on the surface side of the substrate, a part of the surface side of the P-type impurity region is made porous, and the porous layer is formed in the P-type impurity region. A method for manufacturing a semiconductor substrate. 22. The method for manufacturing a semiconductor substrate according to claim 20, wherein after removing the porous layer, the non-porous single crystal layer disposed on the support substrate is heat-treated in a hydrogen atmosphere.