KR100246902B1 - Semiconductor substrate and fabrication method for the same - Google Patents

Abstract

Forming a diffusion region by using a diffusion method in which an element capable of controlling a conductivity type is diffused onto a silicon substrate; Forming a porous layer in said diffusion region; Forming a non-porous single crystal layer on the porous layer; Forming an insulating layer on either the adhered surface of the non-porous single crystal layer or the adhered surface of the base substrate, and adhering the non-porous single crystal layer to the base substrate; Characterized in that the step of removing the porous layer.

Description

Semiconductor substrate and manufacturing method

The present invention relates to a semiconductor substrate and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor substrate suitable for an electronic device or an integrated circuit fabricated in a single crystal semiconductor layer on a dielectric separation or insulator, and a method of manufacturing the semiconductor substrate.

The formation of a single crystal Si semiconductor layer on an insulator constitutes a well known procedure called silicon on an insulator (SOI) technology. Many studies have been made because devices using SOI technology have many advantages that cannot be obtained by using bulk Si substrates for producing conventional Si integrated circuits. In other words, for example, the following advantages are obtained by using the SOI technology.

1) Dielectric separation is easy, so large scale integration is possible

2) Excellent radiation resistance

3) High speed is possible due to the reduced floating capacity.

4) Well process can be omitted

5) Possible to prevent latchup

6) Formation of a fully depleted field effect transistor is possible when the film thickness is reduced.

For a method of forming an SOI structure having many advantages in the above described device characteristics, for example, Special Issue: "Single-crystal silicon on non-single crystal insulators"; edited by G.W.Cullen, Journal of Crystal Growth, Volume 63, No. 3, pp. 429-590 (1983).

In addition, as a prior method, what is called SOS (silicon on sapphire) which forms Si by heteroepitaxial growth by CVD (chemical vapor deposition) on a single crystal sapphire substrate, this method is the most mature SOI gas Although it has been used successfully as a substrate, a large amount of crystal defects due to lattice mismatch of the interface between the Si layer and the sapphire substrate of the lower layer, the incorporation of aluminum from the sapphire substrate into the Si layer, and especially the high manufacturing cost of the substrate, Due to the fact that the technology for large area is not yet developed, there is a limit to the range of applications in which SOS can be used. Therefore, recent attempts have been made to realize an SOI structure without using a sapphire substrate. Such an attempt has generally been made by performing one of the following two procedures.

1) After oxidizing the surface of the Si single crystal substrate, a part of the Si substrate is exposed, and the portion is used as a seed to epitaxially grow Si to form a Si single crystal layer on SiO ₂ (in this case, , With deposition of a Si layer on SiO ₂ ).

2) A Si single crystal substrate is used as the active layer to form SiO ₂ in the lower portion of the active layer (not involving deposition of the Si layer here).

As a method for performing the above procedure 1), a method of directly epitaxially growing a single crystal layer Si in the transverse direction by a CVD method; A method of depositing amorphous Si and laterally epitaxially growing it into a solid phase by heat treatment, or converging and irradiating an energy beam such as an electron beam or a laser beam to an amorphous or polycrystalline Si layer, and growing a single crystal on SiO ₂ by molten material crystallization. Way; Background Art A method of scanning a melting zone in a band shape by a rod heater (zone melting and recrystallization) is well known. Each of these methods has advantages and disadvantages, but all have some problems in controllability, productivity, uniformity, and quality, and have not yet been put to practical use. For example, the CVD method requires sacrificial oxidation to form a planarized thin film, and the crystallinity is poor in the solid phase growth method. In the beam annealing method, there is a problem in processing time by convergent beam scanning and controllability of beam overlap and focus adjustment. The area melt recrystallization method is the most mature method used in the experiments based on the manufacture of a relatively large scale integrated circuit, but many crystal defects such as grain boundary defects are generated, and it is not practical to manufacture minority carrier devices.

As the procedure of 2) above, the following three methods can be mentioned.

1) An oxide film is formed on a Si single crystal substrate having an anisotropically etched V-shaped groove, and a polycrystalline Si layer is deposited on the oxide film as thick as a Si substrate, and then thick polycrystalline Si is polished from the back surface of the Si substrate. A method for forming a dielectrically separated Si single crystal region surrounded by a V-shaped groove on a layer. In this method, although the crystallinity is good, there is a problem in terms of controllability and productivity since a process of depositing a polycrystalline Si layer by several hundred micrometers and a process of obtaining only an Si active layer polished and separated from the back surface of a single crystal Si substrate are used.

2) There is a method called SIMOX (separation by ion implanted oxygen) which forms SiO ₂ layer by oxygen ion implantation in Si single crystal substrate. This method is the most mature method because of its excellent compatibility with Si process. However, in order to form the SiO layer, oxygen ions need to be implanted at 10 ¹⁸ ions / cm 2, which requires a long time for the implantation process, and thus productivity is not high. In addition, since the SIMOX wafer is expensive and there are a relatively large number of crystal defects, industrially, it has not reached a sufficient quality capable of producing a minority carrier device.

3) A method of forming an SOI structure by dielectric separation by oxidation of porous Si. In this method, an N-type Si layer is implanted into the surface of a p-type Si single crystal substrate (Imai et al., ″ J. Crystal Growth ″, vol. 63, 547 (1983)) or by epitaxial growth and patterning. It is a method of forming in a shape, porously changing only a P-type Si substrate by anodization method in HF solution so as to surround Si islands on the surface, and then dielectrically separating the N-type Si islands by accelerated oxidation. . In this method, the separated Si region is determined before the device process is performed, and there is a problem that the degree of freedom in device design is limited.

The present applicant has proposed a new method in Japanese Patent Laid-Open No. 5-21338 to solve this problem.

The method disclosed in Japanese Patent Laid-Open No. 5-21339 forms a member in which a non-porous single crystal semiconductor region is located on a porous single crystal semiconductor region, and on the surface of the non-porous single crystal semiconductor region, the surface is made of an insulating material. A method of manufacturing a semiconductor member in which the porous single crystal semiconductor region is removed by etching after adhering the members.

This method is applicable to fabrication of SOI substrates and is an excellent method of selectively etching porous single crystal semiconductor regions and nonporous single crystal semiconductor regions to obtain, for example, an SOI substrate having a silicon active layer of uniform thickness. As an example of application to the SOI substrate of the method disclosed in Japanese Patent Laid-Open No. 5-21338, a process of porously monocrystalline silicon substrate, a process of epitaxially growing single crystal silicon on the porous silicon layer, and the porous silicon And a step of adhering the epitaxial silicon film on which the layer is formed to another substrate via the insulating layer, and removing the porous silicon from the bonded substrate and leaving the epitaxial silicon layer on the insulating layer.

As can be seen from this example, the method is excellent in productivity, uniformity, controllability, and economic efficiency of forming a Si single crystal layer having excellent crystallinity on the insulating layer as well as a single crystal wafer. In addition, the single crystal silicon layer (active layer) constituting the SOI substrate can be formed by a film forming technique such as a CVD method, the bonding process is performed, and the porous silicon layer is selectively subjected to selective etching of the porous silicon layer prior to the single crystal silicon layer (active layer). The point which removes a silicon layer is mentioned.

MEANS TO SOLVE THE PROBLEM The present inventors considered the point which should further improve based on the method disclosed by the said Unexamined-Japanese-Patent No. 5-21338, and decided that it was a manufacturing cost reduction. That is, the method disclosed in Japanese Patent Laid-Open No. 5-21338 was performed well at the laboratory level, but in this method, if the cost can be further reduced for manufacturing a semiconductor member in a large-scale factory, it is necessary for industrial development. It is expected to contribute more.

In view of these advantages, the present inventors have studied the above method and found that the production cost can be further reduced by considering the type of the porous silicon substrate.

Hereinafter, the silicon (Si) is porous.

The Si substrate can be made porous by anodization method using HF solution. This porous Si layer tends to be formed in the P-shaped Si layer rather than the N-type Si layer for the following reason.

Porous Si was discovered by Ulril in 1956 in the course of electropolishing of semiconductors (A. Uhlir, Bell Syst. Tech. J., vol. 35. 333, 1956).

In addition, Unagami et al. Studied the dissolution reaction of Si in anodization, and reported that holes were required for the anodization of Si in HF solution, and the reaction is as follows. (T.Unagami, J. Electrochem. Soc. Vol. 127, 476 (1980)).

Si + 2HF + (2-n ) e + → SiF 2 + 2H + + ne -

SiF ₂ + 2HF → SiF ₄ + H ₂

SiF ₂ + 2HF → H ₂ SiF ₆

or,

Si + 4HF + (4-λ ) e + → SiF 4 + 4H + + λe -

SiF ₄ + 2HF → H ₂ SiF ₆

Here, e ⁺ and e ^- represent holes and electrons, respectively, n and λ are the number of holes required to dissolve Si atoms, respectively, and porous Si is formed when n> 2 or λ> 4 is satisfied.

As a result, P-type Si in which holes exist is easily porous, while N-type Si is difficult to be porous. Selectivity for the modification of this porous silicon substrate is demonstrated by Nagano et al. And Namai (Nagano, Nakajima, Yasuno, Onaka and Kajiwara, Electronic communication society study report, Vol. 79, SSD79-9549 (1979)) and (K. Imai, ″ Solid-state Electronics :, Vol. 24,159 (1981)).

The porous Si layer has a hole with an average diameter of about tens to hundreds of microns, although it is observed by transmission electron microscopy, but monocrystalline property is maintained, and epitaxial growth of the unitary Si layer on top of the porous layer is performed. It is possible. However, at 1000 ° C. or higher, rearrangement of the holes inside may occur, which may deteriorate the characteristics of the accelerated etching. For this reason, for epitaxial growth of the Si layer, low temperature growth such as molecular beam epitaxial deposition, plasma CVD, reduced pressure CVD, photoCVD, bias sputtering, or liquid phase growth method is preferable.

In addition, since a large amount of voids are formed in the porous layer, the density is reduced to less than half. As a result, the surface area is dramatically increased compared to the volume, so that the chemical etching rate of the layer is significantly increased compared to the etching rate of the normal single crystal layer.

It is disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-21338 that it is possible to produce an adhesive wafer by the etch-back method by utilizing the characteristics of porous Si as described above.

The manufacturing method of the porous silicon substrate disclosed in Japanese Patent Laid-Open No. 5-21338 can be summarized as follows.

(1) P-type substrate is prepared and porous.

(2) A low impurity concentration layer is formed on the P-type substrate by a thin film deposition method such as epitaxial deposition, and the P-type substrate portion is made porous.

(3) An N-type single crystal layer is formed on the surface of the P-type substrate by protonion injection, and the remaining P-type substrate is porous.

Subsequent to the method (1) to (3) described above, a P-type silicon substrate is used. In order to manufacture a large amount of porous silicon substrates uniformly in a large-scale factory, it is necessary to use a P-type substrate with a strictly adjusted resistivity because the polarization is performed by the anodic reaction of silicon, but a silicon substrate having a specified resistivity is relatively expensive. Therefore, if the silicon substrate can be used regardless of the resistivity, the manufacturing cost of the SOI substrate can be further reduced.

Accordingly, one object of the present invention is to provide a method for manufacturing a semiconductor substrate obtained by improving the method disclosed in Japanese Patent Laid-Open No. 5-21338.

Another object of the present invention is to provide a method for manufacturing a semiconductor substrate which can further reduce the manufacturing cost of the SOI substrate.

Another object of the present invention is to provide a method for producing a semiconductor substrate suitable for manufacturing a semiconductor substrate in a factory.

Each of the above objects is achieved by the present invention devised as follows.

According to the first aspect of the present invention, a method of manufacturing a semiconductor substrate includes: forming a diffusion region by using a diffusion method in which an element capable of controlling a conductivity type is diffused onto a silicon substrate; Forming a porous layer in said diffusion region; Forming a non-porous single crystal layer on the porous layer; Forming an insulating layer on the adhered surface of the nonporous single crystal layer or on the adhered surface of the base substrate, and adhering the nonporous single crystal layer to the base substrate; The step of removing the porous layer is provided.

According to the second aspect of the present invention, a method of fabricating a semiconductor substrate includes a diffusion method of diffusing an element capable of controlling conductivity into a first surface of a silicon substrate and a second surface of the back surface of the first surface. Forming a diffusion region; Forming a porous layer in a diffusion region formed on said first surface; Forming a non-porous single crystal layer on the porous layer; Forming an insulating layer on the adhered surface of the non-porous single crystal layer or on the adhered surface of the base substrate, adhering the non-porous single crystal layer and the base substrate, and removing the porous layer.

The above object is achieved by the present invention configured as described above. In the present invention, since the element capable of controlling the conductivity type is diffused by the diffusion method to form a diffusion region, and a porous insect is formed in this region, even when a silicon substrate having a strictly controlled resistivity is not used. Can be made porous uniformly. That is, a relatively low resistance silicon substrate can be used.

In addition, according to the mode of forming the diffusion layers on both surfaces of the substrate, the warpage generated during the formation of the diffusion layer can be reduced. As a result, a sufficient bonding process can be performed, and the possibility that the bonded substrate is peeled off is substantially reduced. Therefore, the yield of the obtained silicon substrate can be improved and the manufacturing cost of a board | substrate can be reduced. In addition, the contact resistance generated when the porous layer is formed by anodization can also be reduced.

1 (a) to 1 (f) are schematic diagrams showing an example of a method for manufacturing a semiconductor substrate according to the present invention.

2 (a) to 2 (h) are schematic diagrams showing another example of the method for manufacturing a semiconductor substrate according to the present invention.

3 (a) to 3 (h) are schematic diagrams showing still another example of the method for manufacturing a semiconductor substrate according to the present invention.

4 (a) to 4 (f) are schematic diagrams showing still another example of the method for manufacturing a semiconductor substrate according to the present invention.

5 (a) to 5 (f) are schematic diagrams showing still another example of the method for manufacturing a semiconductor substrate according to the present invention.

6 is a schematic diagram showing an example of a diffusion procedure applicable to the present invention.

7 (a) and 7 (b) are schematic diagrams showing a method of forming a porous silicon layer.

* Explanation of symbols for main parts of the drawings

100, 600: silicon substrate 101: diffusion layer

102,1102 non-porous single crystal semiconductor (silicon) layer

103, 104, 1103: insulation layer (SiO ₂ layer)

110, 300, 1110, 1210: base board

200: porous layer 301: furnace (diffusion furnace)

302: susceptor 600: substrate

604, 604 ': Fluoride solution 605, 605': Anode

606: cathode 1104: insulating film (oxide film)

The most peculiar feature of the method for manufacturing a semiconductor substrate according to the present invention as described above is that after forming a diffusion region on a silicon substrate by a diffusion method, a porous layer is formed on the diffusion region. Based on these characteristics, this invention is demonstrated in detail, referring FIG. 1 (a) thru | or FIG. 1 (f).

Example 1:

1 (a) to 1 (f) are schematic diagrams illustrating an example of a method for manufacturing a semiconductor substrate of the present invention. First, an element for controlling the conductivity type is diffused into the single crystal silicon substrate (silicon wafer) 100 by the diffusion method (FIG. 1 (a)).

In the present invention, the diffusion layer is used to form a diffusion layer having a density that is easily porous with the single crystal silicon substrate, so that the difference between the silicon substrates is reduced, even when a relatively expensive single crystal silicon substrate with a tightly controlled resistance is not used. A steady process for porousizing a silicon substrate can be performed.

In the present invention, an element that can control the conductivity type and is diffused into the silicon substrate by the diffusion method is generally used in semiconductor manufacturing process technology, for example, those shown in Table 1.

Because of the manufacturing cost, it is preferable to thermally diffuse the silicon substrate to an element that can control the conductivity type by employing a diffusion method, and an example of such a method is shown in Table 2.

In the present invention, since the porous layer is formed in the diffusion region, the porous layer can be formed more easily in the P-type diffusion region than in the N-type diffusion region. Based on this, the technique shown in Table 3 is mentioned as a technique of diffusing B (boron), for example.

Even by the technique shown in Table 3, basically, the element supplied from the source is diffused into the silicon substrate by heat treatment in the "no".

For example, the diffusion method using the spin coating film is performed as follows.

A mixture of an organic binder and a solvent containing B ₂ O ₃ is uniformly coated on a silicon substrate (silicon wafer) using a spinner, and then dried and annealed to form a B ₂ O ₃ film on the silicon substrate. Next, the silicon substrate is placed in a furnace shown in FIG. 6, and boron (B) is diffused by heat treatment. In FIG. 6, 301 is a furnace and 302 is a susceptor. A B ₂ O ₃ film was formed on one surface of the silicon substrate 100, and the silicon substrate 100 was heat-treated at 900 to 1300 ° C. by the apparatus shown in FIG. 6 to form boron in the silicon substrate 100. (B) is diffused. In this case, the diffusion region is formed not only on the surface on which the B ₂ O ₃ film is deposited but also on the back side thereof, using a B ₂ O ₃ film formed on another adjacent silicon substrate as a source. This is very convenient for forming the diffusion layers on both sides of the silicon substrate because the resistance at the time of contact with the HF solution can be reduced when porous by anodization.

In the present invention, in consideration of the characteristics of the epitaxial film formed on the porous siliconization process and the porous silicon layer, the concentration of the element that can control the conductivity type contained in the diffusion region is generally 5.0 × 10 ¹⁶ / cm 3 to 5.0 × 10 ²⁰ / cm 3, preferably 1.0 × 10 ¹⁷ / cm 3 to 20 × 10 ²⁰ / cm 3, most preferably 5.0 × 10 ¹⁷ / cm 3 to 1.0 × 10 ²⁰ / cm 3.

The thickness of the diffusion region formed in the present invention can be controlled by adjusting the heating time and temperature. The thickness of the diffusion layer is generally 100 GPa or more, preferably 500 GPa or more, and most preferably 5000 GPa or more, but since the porous process to be performed after the formation of the diffusion region proceeds easily over the diffusion region, the diffusion region formed is It is not necessarily thick.

In FIG. 1A, the diffusion layer 101 is formed only on one side of the silicon substrate 100, but the diffusion layer 101 may be formed on both surfaces of the silicon substrate 100.

Basically, in the present invention, any type of single crystal silicon substrate (silicon wafer) can be employed as the silicon substrate for forming the diffusion layer, but if the purpose is to reduce the manufacturing cost of the semiconductor substrate, a relatively low resistance-free silicon substrate and IC It is preferable to use a monitor wafer for a process or a so-called recycled wafer which can be polished and reused in an IC process.

In the present invention, the porous layer is formed after the diffusion layer is formed.

A nonporous single crystal silicon substrate (silicon wafer) can be made porous by anodization. The obtained porous silicon layer had a large number of holes having an average diameter of about 50 to 300 mm 3 and maintained a single crystal structure.

In FIG. 1 (b), the porous layer 200 is formed in the diffusion layer 101, and the entirety of this diffusion layer 101 is made porous, or as shown in FIG. 1 (b), the diffusion layer ( A part of 101) may omit this step. In addition, the entirety of the diffusion layer 101 and a part of the silicon substrate 100 may be made porous.

The thickness for porous formation is only about 5 to 20 µm of the surface layer on one side of the substrate, and the entire silicon substrate 100 may be anodized.

Hereinafter, a method of forming a porous silicon layer will be described with reference to FIGS. 7 (a) and 7 (b). The substrate 600 having the diffusion layer formed thereon is placed in the apparatus shown in Fig. 7A. Specifically, the surface on which the diffusion layer of the substrate 600 is formed is brought into contact with the fluoride (fluoride) solution 604 located at the cathode (negative electrode) 606, and the other surface of the substrate 600 is made of a metal anode. (Positive electrode) 605. As another structure, as shown in FIG. 7 (b), the anode 605 'may acquire a potential via the solution 604'. As the fluoride solution 604, concentrated fluoride (49% HF) is generally used. Depending on the strength of the current being conducted, it is undesirable to dilute the solution with hydrogen (H ₂ O) because etching occurs at a certain concentration of the solution. When bubbles are generated on the surface of the substrate 600 during anodization, alcohol may be added as a surfactant to remove the bubbles efficiently. Such alcohols include methanol, ethanol, propanol or isopropanol. In addition, in order to stir the solution for anodization, you may use the stirring apparatus instead of surfactant. The cathode 606 is made of a material such as gold (Au) or platinum (Pt) that is corroded to the fluoride solution, and the anode 605 is made of a common metal material. When the anodization of the substrate 600 is completed, the fluoride solution 604 contacts the anode 605, so that the surface of the anode 605 needs to be coated with a metal film resistant to corrosion with the fluoride solution. The maximum intensity of the polarization current may be several hundred mA / cm 2, and the minimum intensity may be any value except zero. This current strength is determined within a range capable of high quality epitaxial growth on the surface of the porous silicon substrate. Usually, at high current strength, the anodization rate is increased, and at the same time the density of the porous silicon layer is reduced. That is, the internal volume of the pores increases. Thus, the epitaxial growth conditions change. In the present embodiment, in consideration of the properties of the epitaxial layer and the manufacturing cost, the porosity of the porous silicon layer, that is, the porosity (pore volume / (residual silicon volume + pore volume)) is generally 50% or less, preferably 1 to 40%, most preferably in the range of 5 to 30%.

The non-porous single crystal silicon layer 102 is epitaxially grown on the porous layer 200 thus formed (FIG. 1 (c)). In order to form the single crystal silicon layer 102 on the porous layer 200, conventional epitaxial crystal growth methods such as CVD (chemical vapor deposition), MBE (molecular beam epitaxy), or bias sputtering can be employed. have.

Next, the insulating layer 103 is formed on the surface of the epitaxial layer 102 (FIG. 1 (d)). The insulating layer 103 can be formed by a deposition film (for example, a SiO ₂ film or a Si ₃ N ₄ film) using the CVD method or by thermal oxidation of the surface of the epitaxial layer 102. In forming the insulating layer 103 on the epitaxial layer 102, a method of directly adhering the epitaxial layer 102 to the base substrate is effective. In other words, this method reduces the instability of the characteristics of the thin film device caused by the separation of impurities on the adhesive surface and the frequent occurrence of dangling bonds between atoms on the adhesive surface (these phenomena tend to occur during the bonding process). It is possible to do

However, the process of forming the SiO ₂ film 103 on the epitaxial layer 102 is not a necessary procedure. In other words, if the device is designed such that the phenomenon is not a problem, this procedure may be omitted. For the SOI substrate, the SiO ₂ layer 103 functions as an insulating layer, but the insulating layer must be formed on at least one side of one of the substrates to be bonded, and there are various modes for forming the insulating layer. The insulating layer is not limited to the SiO ₂ layer.

In oxidation, the oxide film needs to be thickened so as not to be contaminated by air absorbed by the adhesive surface.

A substrate 110 formed on top of the SiO ₂ layer 104 serving as a base substrate is prepared separately from the substrate 100 having an epitaxial surface whose surface is oxidized. Examples of the base substrate 110 include a silicon substrate whose surface is oxidized (by thermal oxidation), a quartz glass substrate, a crystallized glass substrate, or any substrate having SiO ₂ deposited thereon. A silicon substrate on which no SiO ₂ layer 104 is formed may be used.

The two substrates thus prepared are washed and bonded (FIG. 1 (e)). The cleaning step is performed in the same manner as the normal cleaning step (for example, before oxidation) of the semiconductor substrate.

By pressing the surface of the substrate during adhesion of these substrates, the adhesive force can be increased.

Heat treatment is carried out on the adhesive substrate to increase the adhesion. Heating at a high temperature is preferable, but if the temperature is too high, the structure of the porous layer 200 may change, or impurities contained in the substrate may diffuse into the epitaxial layer. Therefore, the temperature and time must be selected so that the heating does not cause these phenomena, specifically, 600 ° C to 1100 ° C is preferred. However, heat treatment cannot be performed on some substrates. For example, the base substrate 110 made of quartz glass may be heated only up to 200 ° C. because the coefficient of thermal expansion of quartz is different from that of silicon. When the heating temperature exceeds 200 ° C., the bonded substrates are peeled off from each other by stress or are broken. However, the heat treatment needs to provide sufficient stress to withstand the stresses generated during the polishing or etching of the bulk silicon 100 performed in the following process. Therefore, if the surface treatment conditions for activation are optimized, it can be uniformly heat treated at a temperature of 200 ℃ or less.

Next, the silicon substrate 100 and the porous layer 200 are removed while the epitaxial layer 102 is held (FIG. 1 (f)). In this way, an SOI substrate can be obtained. If the entirety of the silicon substrate 100 is made porous, it is not necessary to remove the silicon substrate.

According to the present invention, it is preferable to selectively remove the porous layer by etching. Examples of the etchant include a conventional Si etching solution, a mixture of hydrofluoric acid for selectively etching porous Si, at least one of alcohol or hydrogen peroxide and hydrofluoric acid, between buffered hydrogen fluoride, or alcohol or hydrogen peroxide. And a mixed liquid of at least any one of and a buffered hydrofluoric acid. Since the porous Si layer has a large surface area, it can be selectively etched even with a conventional Si etching liquid.

In the example shown in FIGS. 1 (a) to 1 (f), the layer 102 was regarded as an epitaxial silicon layer, but the layer 102 was made of group II-VI or group III-V. It can be formed from a single crystal compound semiconductor, and such a compound semiconductor layer may be laminated on the epitaxial layer.

In addition, the following processes can be added to the said process.

(1) Peroxidation of the inner wall of the hole in the porous layer

The walls of adjacent air spaces in the porous layer are very thin, ranging from several nm to several tens of nm. In the process of treating the porous layer at a high temperature, that is, in the heat treatment process of the bonded substrate, the pore walls aggregate and become unevenly (that is, roughen) to close the holes, and as a result, the etching rate is reduced. Therefore, a thin oxide film is deposited on the pore wall after formation of the porous layer to prevent roughening of the pore wall. However, since it is necessary to epitaxially grow the non-porous single crystal silicon layer on the porous layer, only the inner wall surface of the pores in the porous layer must be oxidized, and thus the single crystal structure is maintained inside the pore wall. The thickness of the oxide film is preferably several kPa to several tens of kPa, and the oxide film having such a thickness is formed by heat treatment at a temperature of 200 to 700 캜, preferably 250 to 500 캜 in an oxygen atmosphere.

(2) Hydrogen Baking Process

The inventors have disclosed in EP 553852 A2 that the silicon surface is heated in a hydrogen atmosphere to remove the minimum roughness from the surface, resulting in a very smooth silicon surface. Baking in a hydrogen atmosphere can also be applied to the present invention. This hydrogen baking step can be carried out, for example, after the formation of the porous silicon layer and before the formation of the epitaxial silicon layer, or on the SOI substrate obtained after the porous silicon layer is removed by etching. In the hydrogen baking step performed before the formation of the epitaxial silicon layer, the phenomenon that the outermost surface of the hole is closed by the movement of silicon atoms constituting the surface of the porous silicon layer occurs. When the epitaxial silicon surface is formed while closing the outermost surface of the hole, the obtained epitaxial silicon layer has almost no crystal defects. In the hydrogen baking process performed after the porous silicon layer is removed by etching, the surface of the somewhat irregular epitaxial silicon layer is smoothed as a result of etching, and boron in the clean room inevitably absorbed by the adhesive surface during the bonding process is removed. Can be evaporated.

An example of a method for manufacturing a semiconductor substrate of the present invention has been described with reference to FIGS. 1A to 1F, but the following will describe an example in which the structure of the member to be bonded is different.

Example 2:

The example shown to FIG. 2 (a)-2 (h) is demonstrated. In Figs. 2 (a) to 2 (h), the same reference numerals as those of the above-mentioned 1 (a) to 1 (f) denote corresponding or identical components. In the examples shown in FIGS. 1 (a) to 1 (f), insulating layers (SiO ₂ layers) 103 and 104 were formed on respective surfaces of both substrates to be bonded, but insulation was performed on both surfaces. It is not necessary to necessarily form a layer (for example, SiO ₂ ), but may be formed only on at least one surface. In this example, the insulating film 1104 (for example, an oxide film) formed on the silicon substrate 1110 is formed on the surface of the epitaxial silicon layer 1102 (second (c)) deposited on the porous silicon layer 200. Structure (second (d)) and an insulating film 1103 (second (f)) (for example, an oxide film formed by thermal oxidation) formed on the epitaxial silicon layer 1102 The structure (second (g) diagram) in which the surface is bonded to the silicon substrate 1110 whose surface is not oxidized is shown. In this example, other processes can be performed in the manner as shown in FIGS. 1 to 1 (f).

Example 3:

The example shown in FIG. 3 (a)-FIG. 3 (h) is demonstrated. In Figs. 3 (a) to 3 (h), the same reference numerals as those of the above-mentioned 1 (a) to 1 (f) denote corresponding or identical components. The characteristic of this example is that the substrate 1210 (third (d) and third (d) to contact the substrate 100 (third (c) and third (f)) on which the epitaxial silicon film 200 is formed. 3 (g)) is used for glass materials, such as quartz glass or green glass. In this example, a mode (FIG. 3 (d)) for adhering the epitaxial silicon layer 1102 (FIG. 3 (c)) to the glass substrate 1210 is formed on the epitaxial silicon layer 1102. A mode (figure 3 (f)) in which the insulating film 1103 (for example, an oxide film obtained by thermal oxidation) is adhered to the glass substrate 1210 is shown. In this example, other processes can be performed in the manner as shown in FIGS. 1 (a) to 1 (f).

Hereinafter, an example of forming the diffusion layers on both surfaces of the single crystal silicon substrate will be described.

Example 4:

This example will be described with reference to FIGS. 4A to 4F and 5A to 5F.

In this example, first, a diffusion layer (for example, a + P type layer) 101 is formed on the first surface of the single crystal silicon substrate 100 and the second surface located on the rear surface thereof (FIG. 4 (a)). .

Next, the diffusion layer 101 on one side is made porous to form the porous layer 200 (FIG. 4 (b)). The porous layer 200 may be formed by making the entire area of the diffusion layer 101 porous, or as shown in FIG. 4 (b), may be formed while maintaining the diffusion layer 101 during the porous process. Next, the single crystal semiconductor layer 102 is formed on the porous layer 200 (FIG. 4 (c)). The single crystal semiconductor layer 102 may be formed of silicon, or may be formed of a compound semiconductor material such as group II-VI or group III-V. The surface of the single crystal semiconductor layer 102 is adhered to the base substrate 370 (FIG. 4 (d)). The base substrate 300 may be formed by forming the insulating layer 104 on the silicon substrate 110, or may be composed of a transparent glass substrate, a non-transparent insulating member, or a laminate thereof. In short, the base substrate 300 need only be a substrate having an insulating material formed on its surface. As specific bonding means to be used, anodic bonding, pressurization, heat treatment, or a combination thereof may be mentioned. In this way, the diffusion layer 101, the silicon substrate 100, and the porous layer 200 are removed from the bonded structure (FIG. 4 (e)). The removal here can employ not only mechanical methods such as polishing but also chemical methods such as etching.

In FIGS. 5 (a) to 5 (f), the same reference numerals as those of the above 4 (a) to 4 (f) denote corresponding or identical components, and thus detailed description thereof will be omitted. . In the example shown in FIG. 5 (a) to FIG. 5 (f), in FIG. 5 (d), the insulating layer 103 is formed on the single crystal semiconductor layer 102, and this insulating layer 103 ) Is bonded to the base substrate 300, which is different from the example shown in FIGS. 4 (a) to 4 (f). In this example, the base substrate 300 may be a single glass substrate or a structure in which a film or a substrate is laminated on such a substrate.

In this example, the diffusion layer can be formed in the same manner as described with reference to the first (a) to the first (f). In this example, it is also possible to employ the above-described various processes in the example in which the diffusion layer is formed on one surface of the silicon substrate.

According to this example in which the diffusion layers are formed on both surfaces of the substrate, the contact resistance at the time of anodization can be reduced, and the warpage at the time of formation of the diffusion layer can be reduced.

Hereinafter, preferred embodiments of the present invention will be described in detail. However, the present invention is not limited to these examples.

[First Embodiment]

A single crystal Si substrate with no resistance was specified, and a P ⁺ high concentration layer was formed on the first surface of the Si substrate by a diffusion method with a thickness of 5 탆.

Formation of the P ⁺ high concentration layer by the diffusion method was performed as follows. That is, after coating a solution containing B ₂ O ₃ on the main surface of the Si substrate by spin coating, the solution was annealed at 140 ° C. to evaporate the solution. The structure thus obtained was placed in the diffusion furnace for 6 hours while maintaining the temperature of the core tube at 1200 ° C. So-called drive-in was performed on the substrate to form a P ⁺ high concentration layer.

The Si substrate on which the P ⁺ high concentration layer was formed was immersed in an HF solution, and the first surface was anodized to form a porous layer on the first surface. The conditions for polarization were as follows.

Current density: 7 (mAcm ^-2 )

Anodic solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1

Time: 11 (min)

Thickness of Porous Si: 12 (㎛)

Next, the substrate on which the porous layer was formed was subjected to oxidation treatment for 1 hour at 400 ° C. in an oxygen atmosphere. By this oxidation, the inner wall of the pores of the porous Si layer was covered with a thermal oxide film. Thereafter, a single crystal Si layer was epitaxially grown to a thickness of 0.2 mu m on the porous Si layer by the CVD method. Growth conditions were as follows.

Source gas: SiH ₂ Cl ₂ / H ₂

Gas flow rate: 0.5 / 180 (ℓ / min)

Gas Pressure: 80 (Torr)

Temperature: 950 (℃)

Growth rate: 0.3 (㎛ / min)

Subsequently, a 50 nm SiO ₂ layer was formed on the surface of this epitaxial Si layer by thermal oxidation.

The SiO surface, polymerized exactly the surface of the Si substrate of a second form an SiO ₂ layer of 500nm of the _second layer (i.e., the overlap) by contacting bonded by heat treatment for 2 hours, the structure obtained in 900 ℃. As a result, an adhesive substrate was obtained.

Next, the P ⁺ layer of the adhesive substrate was polished to remove the P ⁺ layer and the non-porous single crystal Si region, thereby exposing the porous Si layer to the entire surface.

The exposed porous Si layer was then selectively etched using a mixture of 49% hydrofluoric acid and 30% hydrogen peroxide solution. At this time, etching of single crystal Si did not occur, and the porous Si layer was completely removed by selective etching while using the single crystal Si layer as an etching stopper.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and the ratio of the selective etching rate of the porous layer at this rate reaches a power of 10 or more, so that the amount of etching applied to the nonporous layer can be negligible in practical use. It was small enough (a few nm).

Through this series of steps, a 0.2 탆 thick single crystal Si layer was formed on the Si oxide film, so that a so-called SOI substrate was obtained. The cross section of this SOI substrate was observed using a transmission electron microscope, and it was confirmed that no new crystal defects were introduced into the single crystal Si layer, and a good crystal structure was maintained.

Second Embodiment

A spin coating film of B ₂ O ₃ was deposited on the front and back surfaces of the Si substrate to form a diffusion layer. The fabrication method of the SOI substrate was performed in the same manner as in the first embodiment. The SOI substrate thus obtained was observed in the same manner as in the first embodiment, and it was confirmed that the quality of the single crystal Si thin film was good and the crystal defects were extremely small.

Third Embodiment

Using a paste obtained by adding an organic binder and a solvent to B ₂ O ₃ , a spin coating film was formed on a Si substrate, and ten Si substrates were placed in a diffusion furnace to form a diffusion region thereon. Except for the number of substrates, the same process as the fabrication of the SOI substrate of the first embodiment was performed.

In this embodiment, diffusion layers are formed on both sides of the silicon substrate by vapor phase diffusion of the B ₂ O ₃ film onto the adjacent silicon substrate. It was confirmed that the SOI substrate obtained in this example also had good quality and very few crystal defects.

Fourth Embodiment

A single crystal Si substrate with no resistance was specified, and a P ⁺ high concentration layer was formed on the first and back surfaces of the Si substrate by a diffusion method with a thickness of 5 탆.

Formation of the P ⁺ high concentration layer by the diffusion method was performed as follows. That is, the Si substrate was placed in the core tube, and N ₂ gas was introduced into the liquid diffusion source containing BBr ₃ to bubbling, and the vaporized material was introduced into the core tube together with the carrier gas (N ₂ + O ₂ ). . After maintaining the temperature of the core tube at 1050 ° C. for 1 hour to form a B ₂ O ₃ layer, the temperature of the core tube was maintained at 1200 ° C., so-called drive-in was performed on the substrate to form a P ⁺ high concentration layer. .

The Si substrate on which the P ⁺ high concentration layer was formed was immersed in an HF solution, and the first surface was anodized to form a porous layer on the first surface. The conditions for polarization were as follows.

Current density: 7 (mAcm ^-2 )

Anodic solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1

Time: 11 (min)

Thickness of Porous Si: 12 (㎛)

Next, the substrate on which the porous layer was formed was subjected to oxidation treatment for 1 hour at 400 ° C. in an oxygen atmosphere. By this oxidation, the inner wall of the pores of the porous Si layer was covered with a thermal oxide film. Thereafter, a single crystal Si layer was epitaxially grown to a thickness of 0.2 mu m on the porous Si layer by the CVD method. Growth conditions were as follows.

Source gas: SiH ₂ Cl ₂ / H ₂

Gas flow rate: 0.5 / 180 (ℓ / min)

Gas Pressure: 80 (Torr)

Temperature: 950 (℃)

Growth rate: 0.3 (㎛ / min)

Subsequently, a 50 nm SiO ₂ layer was formed on the surface of this epitaxial Si layer by thermal oxidation.

And a surface of the SiO ₂ layer, by contacting the polymerization exactly the surface of the Si substrate of the second to form a SiO ₂ layer of 500nm (i.e., overlap) was adhered by heating the structure obtained during the 900 ℃, 2 hours. As a result, an adhesive substrate was obtained.

Next, the P ⁺ layer of the adhesive substrate was polished to remove the P ⁺ layer and the non-porous single crystal Si region, thereby exposing the porous Si layer to the entire surface.

Next, the exposed porous Si layer was selectively etched using a mixture of 49% hydrofluoric acid and 30% hydrogen peroxide. At this time, etching of single crystal Si did not occur, and the porous Si layer was completely removed by selective etching while using the single crystal Si layer as an etching stopper.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and the ratio of the selective etching rate of the porous layer at this rate reaches a power of 10 or more, so that the amount of etching applied to the nonporous layer can be negligible in practical use. It was as small as several nm.

Through this series of steps, a 0.2 탆 thick single crystal Si layer was formed on the Si oxide film, so that a so-called SOI substrate was obtained. The cross section of this SOI substrate was observed using a transmission electron microscope, and it was confirmed that no new crystal defects were introduced into the single crystal Si layer, and a good crystal structure was maintained.

In this embodiment, since the P ⁺ layers were formed on both sides of the substrate, the contact resistance at the time of forming the porous layer was reduced, and the warpage accompanying the P ⁺ layer formation was also reduced. As a result, the SOI substrate was able to be formed by bonding the substrate with extremely stable.

[Example 5]

In this embodiment, except for the changed conditions listed in (i) to (iii) below, a semiconductor substrate was fabricated in the same manner as in the fourth embodiment.

(Iii) The polarization conditions were as follows.

Current density: 5 (mAcm ^-2 )

Anodic solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1

Time: 12 (min)

Thickness of Porous Si: 10 (㎛)

(Ii) A single crystal GaAs layer was epitaxially grown to l mu m thickness on the porous Si layer by the MOCVD (Metal Organic Chemical Vapor Deposition) method under the following growth conditions.

Source gas: TMG / AsH ₃ // H ₂

Gas Pressure: 80 (Torr)

Temperature: 700 (℃)

(Iii) A structure obtained by precisely polymerizing and contacting the surface of the GaAs layer and the surface of another Si substrate on which the SiO ₂ layer was formed with 500 nm was bonded by heat treatment at 700 ° C. for 2 hours.

Thus, the board | substrate with which the single-crystal GaAs layer of 1 micrometer thickness was formed on the Si oxide film was obtained. When the cross section of the obtained substrate was observed using a transmission electron microscope, new crystal defects were not introduced into the single crystal GaAs layer, and it was confirmed that a good crystal structure was maintained.

Also in this embodiment, the warpage accompanying the formation of the P ⁺ layer can be reduced, and the SOI substrate can be produced extremely stably.

[Sixth Embodiment]

In this embodiment, except for the changed conditions listed in the following (i) and (ii), the semiconductor substrate was fabricated in the same manner as in the fourth embodiment.

(Iii) The polarization conditions were as follows.

Current density: 5 (mAcm ^-2 )

Anodic solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1

Time: 12 (min)

Thickness of Porous Si: 10 (㎛)

(Ii) A single crystal Si layer was epitaxially grown to a thickness of 0.2 탆 on the porous Si layer by the CVD method under the following growth conditions.

Source gas: SiH ₂ Cl ₂ / H ₂

Gas flow rate: 0.25 / 230 (ℓ / min)

Gas Pressure: 760 (Torr)

Temperature: 1040 (℃)

Growth rate: 0.14 (㎛ / min)

An SOI substrate having a 0.2 탆 thick single crystal Si layer formed on an Si oxide film was obtained.

The cross section of the substrate thus obtained was observed using a transmission electron microscope, and it was confirmed that no new crystal defects were introduced into the single crystal Si layer, and a good crystal structure was maintained.

[Seventh Embodiment]

A semiconductor substrate was fabricated in the same manner as in the fourth embodiment except for the changed conditions listed in (i) to (iv) below.

(Iii) The thickness of the P ⁺ high concentration layer formed by the diffusion method was 10 µm.

(Ii) The polarization conditions were as follows.

Current density: 5 (mAcm ^-2 )

Anodic solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1

Time: 12 (min)

Thickness of Porous Si: 10 (㎛)

(Iii) A single crystal Si layer was epitaxially grown to a thickness of 0.2 탆 on the porous Si layer by the CVD method under the following growth conditions.

Source gas: SiH ₂ Cl ₂ / H ₂

Gas flow rate: 0.4 / 230 (ℓ / min)

Gas Pressure: 80 (Torr)

Temperature: 900 (℃)

Growth rate: 0.13 (㎛ / min)

(Iii) A 50 nm SiO ₂ layer is formed on the surface of the epitaxial Si layer by thermal oxidation, and then the surface of the quartz substrate prepared separately from the surface of the SiO ₂ layer is polymerized to form a thin film and heat treatment (maximum temperature 400 ° C.). Alternately, these substrates were bonded together.

In this manner, a semiconductor substrate having a 0.2 탆 single crystal Si layer formed on the Si oxide film was obtained.

When the cross section of the obtained substrate was observed using a transmission electron microscope, new crystal defects were not introduced into the single crystal Si layer, and it was confirmed that a good crystal structure was maintained.

[Eighth Embodiment]

The process of fabricating the semiconductor substrate was carried out in the same manner as in the fifth embodiment except that the surface of the quartz substrate prepared separately from the surface of the GaAs layer was polymerized to alternately thin and heat-treat (400 ° C.) to bond the two substrates together. It was done. In this embodiment, as in the seventh embodiment, a substrate on which a semiconductor layer having excellent crystallinity was formed was obtained.

[Example 9]

In this embodiment, except for the changed conditions listed in the following (i) and (ii), the semiconductor substrate was fabricated in the same manner as in the fourth embodiment.

(Iii) The polarization conditions were as follows.

Current density: 5 (mAcm ^-2 )

Anodic solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1

Time: 12 (min)

Thickness of Porous Si: 10 (㎛)

(Ii) A 50 nm SiO ₂ layer is formed on the surface of the epitaxial Si layer by thermal oxidation, and then the surface of the quartz substrate prepared separately from the surface of the SiO ₂ layer is polymerized to form a thin film and heat treatment (maximum temperature 400 ° C.). Alternately, these two substrates were bonded together.

In this manner, a semiconductor substrate having a 0.2 탆 single crystal Si layer formed on the Si oxide film was obtained.

When the cross section of the obtained substrate was observed using a transmission electron microscope, new crystal defects were not introduced into the single crystal Si layer, and it was confirmed that a good crystal structure was maintained.

[Example 10]

A semiconductor substrate was fabricated in the same manner as in the fourth embodiment except for the changed conditions opened in the following (i) to (iv).

(Iii) A regenerated single crystal Si substrate was used.

(Ii) The thickness of the P ⁺ high concentration layer formed by the diffusion method was 10 µm.

(Iii) A single crystal Si layer was epitaxially grown to a thickness of 0.2 mu m on the porous Si layer by the CVD method under the following conditions.

Source gas: SiH ₂ Cl ₂ / H ₂

Gas flow rate: 0.25 / 230 (ℓ / min)

Gas Pressure: 760 (Torr)

Temperature: 1040 (℃)

Growth rate: 0.14 (㎛ / min)

In this embodiment, similarly to the fourth embodiment, a substrate on which an excellent crystalline semiconductor layer was formed was obtained.

[Eleventh embodiment]

A semiconductor substrate was fabricated in the same manner as in the fifth embodiment except that a P ⁺ high concentration layer was formed thereon using a regenerated single crystal Si substrate. In this embodiment, as in the fifth embodiment, a substrate on which an excellent crystalline semiconductor layer was formed was obtained.

[Twelfth Example]

A semiconductor substrate was manufactured in the same manner as in the sixth embodiment except that a P ⁺ high concentration layer was formed thereon using a regenerated single crystal Si substrate. In this embodiment, as in the sixth embodiment, a substrate on which an excellent crystalline semiconductor layer was formed was obtained.

[Thirteenth Embodiment]

A semiconductor substrate was fabricated in the same manner as in the ninth embodiment except that a P ⁺ high concentration layer was formed thereon using a regenerated single crystal Si substrate. In this embodiment, as in the ninth embodiment, a substrate on which an excellent crystalline semiconductor layer was formed was obtained.

[Example 14]

A semiconductor substrate was fabricated in the same manner as in the eighth embodiment except that a P ⁺ high concentration layer was formed thereon using a regenerated single crystal Si substrate. In this embodiment, similarly to the eighth embodiment, a substrate on which an excellent crystalline semiconductor layer was formed was obtained.

[Example 15]

The conditions for forming a single crystal Si layer on the porous Si layer by CVD were as follows.

Source gas: SiH ₂ Cl ₂ / H ₂

Gas flow rate: 0.25 / 230 (ℓ / min)

Gas Pressure: 760 (Torr)

Temperature: 1040 (℃)

Growth rate: 0.14 (㎛ / min)

Except for these conditions, the semiconductor substrate was fabricated in the same manner as in the thirteenth embodiment. In this embodiment, as in the thirteenth embodiment, a substrate on which a semiconductor layer having excellent crystallinity was formed was obtained.

[Example 16]

Instead of forming an SiO ₂ layer on the surface of the epitaxial Si layer, a process for producing an SOI substrate in the same manner as in the fourth embodiment, except that the epitaxial Si layer was bonded to another Si substrate on which the SiO ₂ layer was formed. Was performed. In this embodiment as well, an excellent crystalline SOI substrate can be obtained.

[Example 17]

The SOI substrate was fabricated in the same manner as in the fourth embodiment except that the epitaxial Si layer was thermally oxidized to another Si substrate on which no SiO ₂ layer was formed. Also in this example, an excellent crystalline SOI substrate was obtained.

[Example 18]

(1) First, a P ⁺ diffusion layer was formed on a silicon wafer using the method shown in the first embodiment.

(2) In a solution in which 49% HF and ethyl alcohol were mixed at 2: 1, the silicon wafer was used as an anode, and a platinum disk having a diameter of 5 inches was used as the cathode, facing the silicon wafer. The back side of the silicon wafer was coated to prevent energization of platinum through the solution, while the side and end faces of the silicon wafer were also plated, so that the entire surface was energized with platinum through the solution. An electric current was applied for 9 minutes at a current density of 10 mA / cm 2 between the silicon wafer and platinum to anodicize the silicon wafer to form a porous silicon layer having a thickness of 12 μm on the surface layer. The porosity was about 20% when the wafer on which the porous layer was formed was taken out of the solution and the porosity was measured.

(3) Subsequently, the wafer on which the porous silicon layer was formed was oxidized for 1 hour at 400 ° C. in an oxygen atmosphere. Since only about 50 GPa of oxide films were formed during this oxidation treatment, the silicon oxide film was formed only on the surface of the porous silicon layer and the sidewalls of the pores, and the single crystal silicon region was maintained inside.

(4) The wafer was immersed in dilute 1.25% HF aqueous solution for 30 seconds and washed with water to remove the ultra-thin silicon oxide film formed on the porous surface.

(5) The wafer was placed in a CYD growth furnace, and subsequently heat treated under the following conditions.

(a) Temperature: 1120 ℃

Pressure: 80Torr

Gas: H2, 230 (ℓ / min)

Time: 7.5 minutes

(b) Temperature: 900 ℃

Pressure: 80Torr

Gas: H ₂ / SiH ₂ Cl ₂ ; 230 (ℓ / min)

By the above treatment, a single crystal silicon layer of about 0.29 mu m was formed.

(6) The wafer was exposed in a mixed atmosphere of oxygen and hydrogen to oxidize the single crystal silicon layer to form a 200 nm thick silicon oxide film.

(7) The wafer and the second Si wafer were washed with a chemical solution used in a conventional semiconductor manufacturing process. The wafers were immersed in dilute HF solution of the final chemical cleaning, and then rinsed with pure water and dried. Thereafter, the surfaces of these wafers were slowly polymerized and contacted to bond. The bonded wafer was then heat treated at 1180 ° C. for 5 minutes.

(8) Next, the back side of the wafer on which the porous silicon layer was formed was polished to expose the porous silicon layer on the entire surface of the substrate. Thereafter, the wafer was immersed in a solution of HF and H ₂ O ₂ for about 2 hours to remove the porous silicon by etching, thereby forming an epitaxial silicon layer on the second Si wafer (substrate) via a silicon oxide film. 0.2 micrometer was formed.

(9) The substrate was heat treated at 1100 ° C. for 4 hours in a 100% hydrogen atmosphere.

(10) The entire surface of the epitaxial silicon layer was observed with a Nomarsky differential interference microscope, and it was confirmed that an SOI substrate having extremely low crystal defects could be obtained.

[Example 19]

As in the first embodiment, a spin coat film was formed on the first surface of the single crystal Si substrate and then baked. Thereafter, similarly to the fourth embodiment, the wafer was placed in the core tube and a diffusion layer was formed on the back side of the substrate. Subsequently, the same process as in Example 4 was carried out to produce an SOI substrate. The crystallinity of the obtained SOI structure was good.

In the present invention, a diffusion region is formed by diffusing an element that can control the conductivity type by a diffusion method, and a porous layer is formed in this region, so that even when a silicon substrate having a strictly controlled resistivity is not used, a silicon substrate is used. It can be made porous uniformly. That is, a relatively low resistance silicon substrate can be used.

In addition, according to the mode of forming the diffusion layers on both surfaces of the substrate, the warpage generated during the formation of the diffusion layer can be reduced. As a result, a sufficient bonding process can be performed, and the possibility that the bonded substrate is peeled off is substantially reduced. Therefore, the yield of the obtained silicon substrate can be improved and the manufacturing cost of a board | substrate can be reduced. In addition, the contact resistance generated when the porous layer is formed by anodization can be reduced.

Claims (102)

Forming a diffusion region by using a diffusion method in which an element capable of controlling a conductivity type is diffused onto a silicon substrate; Forming a porous layer in said diffusion region; Forming a non-porous single crystal layer on the porous layer; Forming an insulating layer on either the adhered surface of the non-porous single crystal layer or the adhered surface of the base substrate, and adhering the non-porous single crystal layer to the base substrate; A method for manufacturing a semiconductor substrate, comprising the step of removing the porous layer. The method for manufacturing a semiconductor substrate according to claim 1, wherein the element capable of controlling the conductivity type is an element capable of controlling conductivity N type of silicon. The method of manufacturing a semiconductor substrate according to claim 2, wherein the element capable of controlling the conductivity type is selected from the group consisting of P, As, and Sb. The method of manufacturing a semiconductor substrate according to claim 1, wherein the element capable of controlling the conductive type is an element capable of controlling a conductive P type of silicon. The method of manufacturing a semiconductor substrate according to claim 4, wherein the element capable of controlling the conductivity type is B. 6. The method of manufacturing a semiconductor substrate according to claim 1, wherein the diffusion method is a process of thermally diffusing the element onto a silicon substrate. 6. The method of manufacturing a semiconductor substrate according to claim 5, wherein the element capable of controlling the conductivity type is supplied from a gas source. The method of claim 7, wherein the base is B ₂ H ₆ . The method of manufacturing a semiconductor substrate according to claim 5, wherein the element capable of controlling the conductivity type is supplied by using a liquid as a source. The method of claim 9, wherein the liquid is BBr ₃ . 6. The method of manufacturing a semiconductor substrate according to claim 5, wherein the element capable of controlling the conductivity type is supplied from a solid source. The method of claim 11, wherein the solid is B ₂ O ₃ . The method of claim 5, wherein the element capable of controlling the conductivity type is supplied from a solid material formed on the silicon substrate. The method of claim 13, wherein the solid material is selected from a CVD film, a BSG, and a spin coating film. The semiconductor substrate according to claim 1, wherein the conductivity type can be controlled, and the concentration of the element contained in the diffusion layer is adjusted to be in a range of 5.0 × 10 ¹⁶ / cm 3 to 5.0 × 10 ²⁰ / cm 3. How to make. The semiconductor substrate according to claim 15, wherein the conductivity type can be controlled, and the concentration of the element contained in the diffusion layer is adjusted to be in a range of 1.0 × 10 ¹⁷ / cm 3 to 2.0 × 10 ²⁰ / cm 3. How to make. 17. The semiconductor according to claim 16, wherein the conductivity type can be controlled and the concentration of the element contained in the diffusion layer is adjusted to be in the range of 5.0 x 10 ¹⁷ / cm 3 to 1.0 x 10 ²⁰ / cm 3. Method of manufacturing a substrate. The method of manufacturing a semiconductor substrate according to claim 1, wherein the diffusion layer has a thickness of 500 GPa or more. The method of claim 1, wherein the porosity of the porous layer is controlled to 50% or less. 20. The method of claim 19, wherein the porosity of the porous layer is controlled to be in the range of 1% to 40%. 21. The method of claim 20, wherein the porosity of the porous layer is controlled to be in the range of 5% to 30%. 2. The method of claim 1, wherein the non-porous single crystal layer is a single crystal Si layer. The method of claim 1, wherein the non-porous unitary layer is a single crystal compound semiconductor layer. 23. The method of claim 22, wherein the insulating layer is selected from the group consisting of a thermal oxide film, a deposited SiO ₂ film and a deposited Si ₃ N ₄ film. 25. The method of claim 24, wherein the insulating layer is formed on the nonporous single crystal layer. 25. The method of claim 24, wherein the insulating layer is formed by thermal oxidation of a surface of the single crystal silicon layer. The method of claim 1, wherein the base substrate is a single crystal silicon substrate. 28. The method of claim 27, wherein an oxide layer is formed on the adhered surface of the base substrate. 28. The method of claim 27, wherein the surface of the base substrate to be bonded is formed of single crystal silicon. The method of claim 1, wherein the base substrate is made of glass. 25. The method of claim 24, wherein the insulating layer is formed on the base substrate side. 32. The method of claim 31, wherein the insulating layer is formed by thermal oxidation of a single crystal silicon substrate. 32. The method of claim 31, wherein the insulating layer constitutes a glass substrate. 32. The manufacturing method of a semiconductor substrate according to claim 31, wherein adhesion is carried out without forming said insulating layer on said nonporous single crystal layer. 23. The method of claim 22, wherein after oxidizing the inner wall of the pores of the porous layer, the non-porous silicon layer is formed by epitaxial growth. 36. The method of claim 35, wherein the non-porous silicon layer is formed by epitaxial growth after heat treatment on the porous layer in a hydrogen atmosphere. 2. The porous layer according to claim 1, wherein the porous layer is prepared by using a mixed liquid of at least one of hydrofluoric acid, alcohol or hydrogen peroxide and buffered hydrofluoric acid, or a mixed liquid of at least one of alcohol or hydrogen peroxide and buffered hydrofluoric acid. Method of manufacturing a semiconductor substrate, characterized in that removed. The method of manufacturing a semiconductor substrate according to claim 1, wherein after the porous layer is removed, heat treatment is performed in a hydrogen atmosphere. Forming a diffusion region on the first surface of the silicon substrate and on the second surface on the rear side of the first surface by using a diffusion method for diffusing an element capable of controlling the conductivity type; Forming a porous layer in a diffusion region formed on the first surface; Forming a non-porous single crystal layer on the porous layer; Forming an insulating layer on either the adhered surface of the non-porous single crystal layer or the adhered surface of the base substrate, and adhering the non-porous single crystal layer and the base substrate; A method for manufacturing a semiconductor substrate, comprising the step of removing the porous layer. 40. The method of claim 39, wherein the element capable of controlling the conductivity type is an element capable of controlling conductivity N type of silicon. 41. The method of claim 40, wherein the element capable of controlling the conductivity type is selected from the group consisting of P, As, and Sb. 40. The method of claim 39, wherein the element capable of controlling the conductive type is an element capable of controlling a conductive P type of silicon. 43. The method of claim 42, wherein the element capable of controlling the conductivity type is B. 40. The manufacturing method of a semiconductor substrate according to claim 39, wherein said diffusion method is a process of thermally diffusing said element onto a silicon substrate. 44. The method of claim 43, wherein the element capable of controlling the conductivity type is supplied by using gas as a source. 46. The method of claim 45, wherein the base is B ₂ H ₆ . 44. The method of claim 43, wherein the element capable of controlling the conductivity type is supplied by using a liquid as a source. 48. The method of claim 47, wherein the liquid is BBr ₃ . The manufacturing method of a semiconductor substrate according to claim 43, wherein said element capable of controlling said conductivity type is supplied from a solid source. 50. The method of claim 49, wherein the solid is B ₂ O ₃ . 44. The method of claim 43, wherein the element capable of controlling the conductivity type is supplied from a solid material formed on the silicon substrate. 52. The method of claim 51, wherein the solid material is selected from a CVD film, a BSG, and a spin coating film. 40. The semiconductor substrate according to claim 39, wherein the conductivity type can be controlled, and the concentration of the element contained in the diffusion layer is adjusted to be in the range of 5.0 x 10 ⁶ / cm 3 to 5.0 x 10 ²⁰ / cm 3. How to make. 54. The semiconductor substrate according to claim 53, wherein the conductivity type can be controlled, and the concentration of the element contained in the diffusion layer is adjusted to be in the range of 1.0x10 ¹⁷ / cm 3 to 2.0x10 ²⁰ / cm 3. How to make. 55. The semiconductor substrate according to claim 54, wherein the conductivity type can be controlled and the concentration of the element contained in the diffusion layer is adjusted to be in the range of 5.0 x 10 ¹⁷ / cm 3 to 1.0 x 10 ²⁰ / cm 3. How to make. 40. The method of claim 39, wherein the diffusion layer has a thickness of at least 500 GPa. 40. The method of claim 39, wherein the porosity of the porous layer is controlled to 50% or less. 59. The method of claim 57, wherein the porosity of the porous layer is controlled to be in the range of 1% to 40%. 59. The method of claim 58, wherein the porosity of the porous layer is controlled to be in the range of 5% to 30%. 40. The method of claim 39, wherein the nonporous unitary layer is a single crystal Si layer. 40. The method of claim 39, wherein the nonporous single crystal layer is a single crystal compound semiconductor layer. 61. The method of claim 60, wherein the insulating layer is selected from the group consisting of a thermal oxide film, a deposited SiO ₂ film and a deposited Si ₃ N ₄ film. 63. The method of claim 62, wherein the insulating layer is formed on the nonporous single crystal layer. 63. The method of claim 62, wherein the insulating layer is formed by thermal oxidation of a surface of the single crystal silicon layer. 40. The method of claim 39, wherein the base substrate is a single crystal silicon substrate. 67. The method of claim 65, wherein an oxide layer is formed on the adhered surface of the base substrate. 67. The method of claim 65, wherein the surface of the base substrate to be bonded is formed of single crystal silicon. 40. The method of claim 39, wherein the base substrate is made of glass. 63. The method of claim 62, wherein the insulating layer is formed on the base substrate side. 70. The method of claim 69, wherein the insulating layer is formed by thermal oxidation of a single crystal silicon substrate. 70. The method of claim 69, wherein the insulating layer constitutes a glass substrate. 70. The manufacturing method of a semiconductor substrate according to claim 69, wherein adhesion is carried out without forming said insulating layer on said nonporous single crystal layer. 61. The method of claim 60, wherein the nonporous silicon layer is formed by epitaxial growth after oxidizing the inner wall of the pores of the porous layer. 74. The method of claim 73, wherein the non-porous silicon layer is formed by epitaxial growth after heat treatment on the porous layer in a hydrogen atmosphere. 40. The porous layer according to claim 39, wherein the porous layer is prepared by using a mixed solution of at least one of hydrofluoric acid, alcohol or hydrogen peroxide solution, buffered hydrofluoric acid, or a mixture of at least one of alcohol or hydrogen peroxide solution and buffered hydrofluoric acid. Method of manufacturing a semiconductor substrate, characterized in that removed. 40. The method of manufacturing a semiconductor substrate according to claim 39, wherein after the porous layer is removed, heat treatment is performed in a hydrogen atmosphere. 40. The method of claim 39, wherein a plurality of silicon substrates each having a solid material formed thereon on the first surface is disposed in a furnace and heated to diffuse the diffusion over each of the first and second surfaces of the plurality of substrates. A method of manufacturing a semiconductor substrate, wherein the region is formed. Forming a diffusion region by using a diffusion method in which an element capable of controlling a conductivity type is diffused onto a silicon substrate; Forming a porous layer in said diffusion region; Forming a non-porous layer on the porous layer; Forming an insulating layer on either the adhered surface of the non-porous single crystal layer or the adhered surface of the base substrate, and adhering the non-porous single crystal layer to the base substrate; A semiconductor substrate obtained by a method of manufacturing a semiconductor substrate comprising the step of removing the porous layer. Forming a diffusion region on the first surface of the silicon substrate and on the second surface on the rear side of the first surface by using a diffusion method for diffusing an element capable of controlling the conductivity type; Forming a porous layer in said diffusion region formed on said first surface; Forming a non-porous single crystal layer on the porous layer; An insulating layer is formed on either the adhered surface of the non-porous single crystal layer or the adhered surface of the base substrate, and bonding the non-porous single crystal layer and the base substrate; A semiconductor substrate comprising the step of removing the porous layer obtained by a method of manufacturing a semiconductor substrate. Forming a P ⁺ layer integrated with the element capable of controlling the conductivity type on the surface of the silicon substrate; Forming a porous layer in said P ⁺ layer; Forming a non-porous single crystal layer on the porous layer; Forming an insulating layer on either the adhered surface of the non-porous single crystal layer or the adhered surface of the base substrate, and adhering the non-porous single crystal layer to the base substrate; A semiconductor substrate obtained by a method of manufacturing a semiconductor substrate comprising the step of removing the porous layer. 81. The semiconductor substrate according to claim 80, wherein said element capable of controlling said conductivity type is B. 81. The semiconductor substrate according to claim 80, wherein said element capable of controlling said conductivity type is supplied with a gas by itself. 85. The semiconductor substrate of claim 82 wherein the gas is B ₂ H ₆ . The method of claim 80, wherein the concentration of the element is 5.0 × 10 ¹⁶ / ㎤ to 5.0 × 10 ²⁰ / ㎤ semiconductor substrate characterized in that the adjustment to be within the range of. 85. The semiconductor substrate according to claim 84, wherein said concentration of said element is adjusted to be in the range of 1.0 x 10 ¹⁷ / cm 3 to 2.0 x 10 ²⁰ / cm 3. 86. The semiconductor substrate according to claim 85, wherein said concentration of said element is adjusted to be in the range of 5.0 x 10 ¹⁷ / cm 3 to 1.0 x 10 ²⁰ / cm 3. 81. The semiconductor substrate of claim 80 wherein the thickness of said P ⁺ layer is at least 500 microns. 81. The semiconductor substrate according to claim 80, wherein a porosity of the porous layer is controlled to 50% or less. 89. The semiconductor substrate according to claim 88, wherein said porosity of said porous layer is controlled to be in the range of 1% to 40%. 90. The semiconductor substrate according to claim 89, wherein said porosity of said porous layer is controlled to be in the range of 5% to 30%. 81. The semiconductor substrate of claim 80, wherein the nonporous single crystal layer is a single crystal Si layer. 81. The semiconductor substrate according to claim 80, wherein the nonporous single crystal layer is a single crystal compound semiconductor layer. 81. The semiconductor substrate according to claim 80, wherein said insulating layer is selected from the group consisting of a thermal oxide film, a deposited SiO ₂ film and a deposited Si ₃ N ₄ film. 95. The semiconductor substrate according to claim 93, wherein said insulating layer is formed on said nonporous single crystal layer. 95. The semiconductor substrate according to claim 93, wherein said insulating layer is formed by thermal oxidation of the surface of said single crystal silicon layer. 81. The semiconductor substrate of claim 80, wherein the base substrate is a single crystal silicon substrate. 98. The semiconductor substrate of claim 96, wherein the surface to be bonded to the base substrate is formed of single crystal silicon. 81. The semiconductor substrate according to claim 80, wherein said base substrate is made of glass. 92. The semiconductor substrate according to claim 91, wherein after oxidizing the inner wall of the pores of the porous layer, the non-porous silicon layer is formed by epitaxial growth. 100. The semiconductor substrate according to claim 99, wherein said nonporous silicon layer is formed by epitaxial growth after heat treatment on said porous layer in a hydrogen atmosphere. 82. The porous layer according to claim 80, wherein the porous layer is formed by using a mixture of at least one of hydrofluoric acid, alcohol, or hydrogen peroxide and buffered hydrofluoric acid, or a mixture of at least one of alcohol or hydrogen peroxide and buffered hydrofluoric acid. A semiconductor substrate, characterized in that removed. 81. The semiconductor substrate according to claim 80, wherein after the porous layer is removed, heat treatment is performed in a hydrogen atmosphere.