JP5183958B2 - Manufacturing method of SOI wafer - Google Patents

Description

  The present invention relates to a method for manufacturing an SOI (Silicon on Insulator) wafer by a bonding method, and more particularly to a method for manufacturing an SOI wafer having gettering ability.

  In recent years, high-integrated CMOS, IC, high-voltage devices, etc. have been manufactured using SOI wafers. The specific structure of an SOI wafer is that an oxide film or the like is buried under a silicon single crystal layer (hereinafter referred to as an SOI layer) used as an active layer which becomes a surface device fabrication region with respect to the depth direction of the wafer. It has a three-layer structure in which an insulating layer (hereinafter sometimes referred to as a Box layer) is sandwiched and a silicon single crystal layer (hereinafter referred to as a support substrate) is provided below the insulating layer. The SOI wafer having such a structure has features such as low parasitic capacitance and high radiation resistance. Therefore, effects such as high-speed and low-power consumption operation and latch-up prevention are expected, and it is promising as a substrate for high-performance semiconductor elements.

  As a method for manufacturing this SOI wafer, for example, the following method is known. Specifically, two mirror-polished silicon single crystal wafers (a silicon single crystal wafer (bond wafer) serving as an SOI layer and a silicon single crystal wafer (base wafer) serving as a support substrate) are prepared, and at least one silicon substrate is prepared. An oxide film is formed on the surface. Then, after bonding these silicon single crystal wafers with an oxide film interposed therebetween, bonding heat treatment is performed to increase the bond strength. Thereafter, the bond wafer is thinned to obtain an SOI wafer on which an SOI layer is formed. As a method for thinning, a bond wafer is ground to a desired thickness, polished, or the like, or a bonding layer is formed by ion implantation of hydrogen or helium in advance before bonding. There is a method called an ion implantation separation method (for example, Patent Document 1) in which a heat treatment is performed at a lower temperature and the bond wafer is peeled off by this release layer, followed by the bonding heat treatment described above.

  As described above, SOI wafers have many structural advantages from the viewpoint of electrical characteristics, but have structural disadvantages from the viewpoint of resistance to metal impurity contamination. That is, in many cases, the diffusion rate of metal impurities is slower in the silicon oxide film than in silicon. As a result, when contaminated from the surface of the SOI layer, metal impurities are difficult to pass through the Box layer, so that they are accumulated in the thin SOI layer. Therefore, the adverse effect of metal contamination is greater than in the case of a silicon substrate having no SOI structure. Therefore, in an SOI wafer, one of the more important qualities is to have a capability (gettering capability) of capturing a metal impurity and removing it from a region to be an active layer of a semiconductor element.

  In general, gettering techniques (oxygen precipitates, high-concentration boron addition, backside polycrystalline silicon film, etc.) used in the case of a silicon substrate having no SOI structure are all provided on the support substrate side opposite to the active layer. A ring layer is introduced. However, even if a gettering layer is introduced on the support substrate side using a similar method in an SOI wafer, the above-described gettering layer does not function sufficiently because the metal impurities hardly pass through the Box layer. Has a problem that it cannot be applied to SOI wafers as they are.

In order to solve such a problem, several methods for introducing a gettering region in the vicinity of the SOI layer have been proposed in the SOI wafer manufacturing method by the bonding method.
For example, before bonding, phosphorus or silicon is ion-implanted into the bonding surface of the bond wafer to introduce strain and defects, and after bonding, a gettering layer between the SOI layer and the Box layer is formed (for example, a patent Reference 2).
There has also been proposed a method in which ions other than phosphorus and silicon, for example, boron, carbon, argon, krypton, and xenon are ion-implanted into a bonding surface of a bond wafer before bonding (see Patent Document 3).

  However, when a device is manufactured using an SOI wafer manufactured by such a method, there is a problem that a leakage current may be abnormally generated or an oxide film breakdown voltage may be deteriorated.

Japanese Patent No. 3048201 JP-A-6-163862 Japanese Patent Laid-Open No. 10-32209

  Accordingly, the present invention has been made in view of such problems, and provides a method for manufacturing an SOI wafer having sufficient gettering capability while suppressing generation of leakage current and deterioration of oxide film breakdown voltage. For the purpose.

The present invention has been made to solve the above-described problems, and includes at least a step of preparing a base wafer and a bond wafer made of silicon single crystal, and an insulating film on at least one surface of the base wafer and the bond wafer. A step of forming an ion-implanted damage layer by ion-implanting a neutral element electrically inactive in silicon from the surface of either the base wafer or the bond wafer; and the ion In the method for manufacturing an SOI wafer, comprising the step of bonding the base wafer and the bond wafer through the insulating film to the implanted surface, and the step of thinning the bonded wafer. Neutral element ion implantation in the forming step is performed at a dose of 1 × 10 ¹² at. It that provides method for manufacturing an SOI wafer characterized by performing a oms / cm ² to 1 × ¹⁰ than 15 atoms / cm ^2.

As described above, in a method for manufacturing an SOI wafer, the method includes a step of forming an ion-implanted damage layer by ion-implanting a neutral element that is electrically inactive in silicon into either a base wafer or a bond wafer. the ion implantation of the neutral element, by performing dose amount of less than 1 × ¹⁰ 12 atoms / cm ² or more ^{1 × 10 15 atoms / cm 2} , that the secondary defects from the ion-implanted damaged layer during the bonding heat treatment is generated An SOI wafer having a sufficient gettering capability can be manufactured while suppressing the above. As a result, it is possible to obtain an SOI wafer in which generation of leakage current and deterioration of oxide film breakdown voltage are suppressed.

In this case, the neutral element of the ion implantation, argon, carbon, oxygen, have preferably be at least one silicon.

  Thus, if the neutral element to be ion-implanted is at least one of argon, carbon, oxygen, and silicon, sufficient gettering ability can be effectively added with a lower dose. In addition, with such a low dose, the occurrence of secondary defects during the bonding heat treatment can be further suppressed. Further, these elements are preferable because they do not adversely affect device characteristics.

In this case, when carbon is ion-implanted as the neutral element, the dose is set to 1 × 10 ¹³ atoms / cm ² or less, and when oxygen is ion-implanted, the dose is set to less than 1 × 10 ¹⁵ atoms / cm ^2. , when argon or silicon ion implantation have preferable that a dose of 1 × ¹⁰ 14 atoms / cm ² or less.

  If such a dose amount is set according to each neutral element to be ion-implanted, the occurrence of secondary defects during the bonding heat treatment can be suppressed more reliably. Even with such a dose, sufficient gettering capability can be added.

Moreover, it is not preferable that the acceleration voltage for ion implantation of the neutral element than 200 keV. Moreover, it is not preferable that the thickness of the ion-implanted damaged layer and 0.5μm or less.

  Thus, if the acceleration voltage when ion-implanting the neutral element is 200 keV or less or the thickness of the ion-implanted damaged layer is 0.5 μm or less, the thickness of the ion-implanted damaged layer is sufficiently thin. Generation of secondary defects from the ion-implanted damaged layer during the heat treatment can be further suppressed. Further, even with such a thickness of the ion implantation damage layer, sufficient gettering capability can be added.

Also, the insulating film has preferably be a combination silicon oxide film or a silicon nitride film, or these.

  As described above, if the insulating film is a silicon oxide film, a silicon nitride film, or a combination thereof, a dense and high-quality insulating film can be easily formed, and an SOI wafer having excellent insulating characteristics and gettering ability can be obtained. it can.

Further, the thinning of the bond wafer, Ru can be performed by grinding the bond wafer. In addition, before the bonding step, the bonding wafer is thinned by providing an ion implantation layer for peeling by ion implantation of hydrogen or helium from the surface of the bonding wafer before the bonding step. in, Ru can be done by peeling the bond wafer at the ion-implanted layer for delamination by delamination heat treatment.

  Thus, even when thinning the bond wafer is performed by grinding a bond wafer suitable for forming a thick SOI layer, it is performed by an ion implantation separation method suitable for forming a thin film SOI layer. Even if it exists, sufficient gettering capability can be added to an ion implantation damage layer, and generation | occurrence | production of the secondary defect from the ion implantation damage layer at the time of bonding heat processing can be suppressed.

Further, prior to at least the bonding step, Ru can also comprise the step of the element serving as a donor in silicon the neutral element from the surface ion-implanted by ion implantation to form an n ⁺ layer. In this case, the element to be the donor, phosphorus, arsenic, Ru can be at least one of antimony.

Thus, at least prior to the bonding step, a step of forming an n ⁺ layer by ion-implanting an element serving as a donor in silicon from a surface on which a neutral element is ion-implanted is provided. If at least one of phosphorus, arsenic, and antimony is used, a stronger gettering site can be obtained by combining the gettering ability by the n ⁺ layer and the gettering ability by the ion implantation damage layer. Even in such a case, the occurrence of secondary defects from the ion-implanted damage layer during the bonding heat treatment can be suppressed.

Moreover, in these cases, the dose amount of ion implantation of the neutral element, have preferably be 5 × ¹⁰ 12 atoms / cm ² or more.
As described above, when the dose amount of the ion implantation of the neutral element is set to 5 × 10 ¹² atoms / cm ² or more, an SOI wafer having sufficient gettering ability can be manufactured more reliably.

  According to the present invention, it is possible to manufacture an SOI wafer having a sufficient gettering capability in an ion implantation damage layer while suppressing generation of secondary defects from the ion implantation damage layer during the bonding heat treatment. If a device is manufactured using the SOI wafer manufactured in this way, it is a device that is resistant to heavy metal contamination, but it can prevent the occurrence of abnormal leakage current, deterioration of oxide film breakdown voltage, etc. because it has few defects. .

Hereinafter, the present invention will be described more specifically with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a diagram showing an example of a method for manufacturing an SOI wafer by the bonding method of the present invention. The outline of the manufacturing method of the SOI wafer by the bonding method to which the present invention is applied is as follows.

First, in the step (a), a silicon single crystal wafer (bond wafer) 11 to be an SOI layer for forming a semiconductor element and a silicon single crystal wafer (base wafer) 14 to be a support substrate are prepared.
Next, in step (b), an insulating film 13 to be a buried insulating layer is formed on at least one of the base wafer 14 and the bond wafer 11 (here, the insulating film 13 is formed on the base wafer 14).

  Next, in step (c), ion implantation of a neutral element is performed from at least one surface of the base wafer 14 or the bond wafer 11 to form an ion implantation damage layer 12 (here, ion implantation damage to the bond wafer 11). Forming a layer). Prior to ion implantation, a screen oxide film may be formed on the surface of the bond wafer 11. Further, the screen oxide film may or may not be removed before the step (d). In the present invention, the dose amount of ion implantation of the neutral element is defined, which will be described later.

Next, in the step (d), the base wafer 14 and the bond wafer 11 are bonded together with the surface on the side where the ion-implanted damage layer 12 is formed by ion implantation as a bonding surface through the insulating film 13. In this way, a bonded wafer 20 having a bonded surface 15 is obtained.
Next, in the step (e), a bonding heat treatment for increasing the bonding strength of the bonding surface 15 is performed. For example, two wafers can be firmly bonded by performing heat treatment at 1000 ° C. to 1200 ° C. for 10 minutes to 6 hours in an oxidizing or inert gas atmosphere.
Next, in the step (f), the bond wafer 11 is thinned to a desired thickness, and the SOI layer 51 is formed on the support substrate 54 with the Box layer 53 interposed therebetween, and the SOI wafer having the ion implantation damage layer 52 is formed. Get 50.

For thinning the bond wafer, for example, a method by surface grinding and mirror polishing suitable for forming a relatively thick SOI layer can be used, or a bond wafer and a base wafer suitable for forming a thin SOI layer can be used. Before the step (d) of bonding, a separation ion layer is formed by injecting hydrogen ions or helium ions into the bonding surface of the bond wafer in advance, and bonding is performed with the separation ion implantation layer after the bonding. A method called an ion implantation separation method in which the wafer is thinned by peeling off the wafer can also be used. In addition, when thinning by ion implantation peeling method, after bonding at room temperature, after performing peeling by performing low temperature heat treatment at about 500 ° C., if necessary, bonding heat treatment step for increasing bond strength (E) is performed in the order of steps. Further, at this time, a method of peeling off the ion-implanted layer by mechanical stress without performing the heat treatment at about 500 ° C. by bonding the wafer surface to be bonded after being activated by plasma treatment. It can also be used.
Note that the ion implantation layer for peeling may be formed before or after the ion implantation step for forming the gettering layer.

  In this way, the SOI wafer 50 having the ion-implanted damage layer 52 is obtained. When ions are implanted into the bond wafer 11 in the step (c) of FIG. ), An ion implantation damage layer 52 is formed in the interface region between the SOI layer 51 and the Box layer 53. Conversely, when ions are implanted into the base wafer 14, an ion implantation damage layer 52 is formed in the interface region of the support substrate 54 with the Box layer 53, as shown in FIG.

  Through such a process, according to the method of manufacturing an SOI wafer as a gettering layer by introducing an ion implantation damage layer by ion implantation into a silicon single crystal wafer, the leakage current is abnormal as described above. There has been a problem that it may occur or the breakdown voltage of the oxide film may deteriorate.

As a specific factor for the reason for the deterioration of the characteristics of such an SOI wafer, the present inventors have focused on secondary defects generated from the ion implantation damage layer after the bonding heat treatment.
That is, conventionally, the dose amount of ion implantation for introducing an ion implantation damage layer for the purpose of gettering into an SOI wafer is required to be 1 × 10 ¹⁵ atoms / cm ² or more. With such a dose amount, a strong gettering ability can surely be added to the SOI wafer, but on the other hand, a large amount of secondary defects are generated during the bonding heat treatment, and the SOI wafer is generated. In some cases, the characteristics of the material deteriorated. If the digit of the dose amount increases by one digit, the time required for ion implantation becomes about 10 times. When the dose is 1 × 10 ¹⁵ atoms / cm ² or more as in the conventional case, ion implantation for a long time is required, resulting in low productivity and high cost.

  Based on these facts, the present inventors have further studied, and in the manufacture of SOI wafer by the bonding method, in the ion implantation for forming the ion implantation damage layer for the purpose of gettering, the electrical In the case of ion-implanting a neutral element that is inert to the metal (hereinafter simply referred to as a neutral element), it has been found that metal impurities can be sufficiently gettered even if the dose is lower than in the prior art. The present invention was completed by optimizing various conditions.

Specifically, in the SOI wafer manufacturing method as shown in FIG. 1, in the ion implantation step of FIG. 1 (c), the dose amount of the neutral element to be ion implanted is 1 × 10 ¹² atoms / if cm ² or more 1 × 10 15 ^atoms / cm ² less than a, it was found that it is possible to suppress the conjunction obtain sufficient gettering capability, secondary defects from the ion-implanted damaged layer during the bonding heat treatment occurs . In addition, since sufficient gettering capability can be obtained with a low dose as in the present invention, it is not necessary to perform long-time ion implantation as in the prior art, and productivity can be increased and costs can be kept low. .

In order to further suppress the generation of secondary defects from the ion-implanted damage layer during the bonding heat treatment, the dose of the neutral element is more preferably 1 × 10 ¹⁴ atoms / cm ² or less, It is particularly preferable to set it to 1 × 10 ¹³ atoms / cm ² or less.
Note that 1 × 10 ¹² atoms / cm ² , which is the lower limit of the effective dose amount of the present invention, is a substantially lower limit value of the dose amount that can be stably ion-implanted by a normal ion implantation apparatus.
In this case, in order to more reliably add gettering capability to the SOI wafer, the dose of the neutral element is preferably set to 5 × 10 ¹² atoms / cm ² or more.

It has also been found that the upper limit of the dose amount for suppressing the generation of secondary defects varies depending on the type of element to be implanted. As the neutral element to be ion-implanted, each ion species of argon, carbon, oxygen, and silicon is suitable.
In particular, when argon is ion-implanted into silicon and an ion-implanted damage layer is introduced, a gettering site having strong gettering ability can be obtained, which is preferable.

In this case, in order to more reliably suppress the generation of secondary defects during the bonding heat treatment, when carbon is ion-implanted, the dose is set to 1 × 10 ¹³ atoms / cm ² or less, and oxygen is ion-implanted. The dose is preferably less than 1 × 10 ¹⁵ atoms / cm ^2, and in the case of ion implantation of argon or silicon, the dose is preferably 1 × 10 ¹⁴ atoms / cm ² or less.

Further, in such a neutral element ion implantation step, when the acceleration voltage of the ion implantation apparatus is set to 200 keV or less, the generation of secondary defects from the ion implantation damage layer during the bonding heat treatment is more reliably suppressed. Is preferable. Even with such an acceleration voltage, a sufficient gettering effect can be added to the SOI wafer.
Although the lower limit of the acceleration voltage at the time of ion implantation of this neutral element is not clearly limited, it is necessary to ion-implant into the silicon single crystal wafer, so depending on the implanted element, For example, it can be 10 keV.

Moreover, it is preferable to adjust the acceleration voltage of the ion implantation apparatus of the present invention so that the thickness of the ion implantation damage layer is 0.5 μm or less. The thickness of such an ion-implanted damage layer varies depending on the neutral element to be implanted, but can be roughly achieved by setting the acceleration voltage of the ion implantation apparatus to about 200 keV or less.
With such a thickness of the ion-implanted damage layer, the ion-implanted damage layer can hardly be observed by ordinary cross-sectional TEM observation, but sufficient gettering capability should be added when an SOI wafer is manufactured. Can do. And if it is the thickness of such an ion implantation damage layer, generation | occurrence | production of the secondary defect from the ion implantation damage layer at the time of bonding heat processing can be suppressed more reliably.
The lower limit of the thickness of the ion implantation damage layer is not particularly limited, but is determined by the lower limit of the acceleration voltage of the ion implantation apparatus.

  By the way, in the present invention, the ion-implanted damage layer is formed in the vicinity of the bonding surface between the bond wafer and the base wafer. That is, as described above, as shown in FIG. 2, when ions are implanted into the surface of the bond wafer, the interface region of the SOI layer and the box layer is ion implanted into the surface of the base wafer. An ion implantation damage layer is formed in an interface region with the Box layer. At this time, since the bonding state of the bonded surfaces is not different from each other, the gettering ability of both ion implantation damage layers is essentially the same.

  However, due to the difference between the diffusion rate of metal impurities in silicon and the diffusion rate in silicon oxide, the metal impurities hardly pass through the Box layer. Therefore, it can be said that the gettering layer is preferably formed in the interface region of the SOI layer with the Box layer in order to getter the metal contamination attached to the surface of the SOI layer which is a device manufacturing region. In other words, it is more preferable that neutral elements are ion-implanted on the surface of the bond wafer to form an ion-implanted damage layer and bonding is performed.

  However, even when an ion-implanted damage layer is formed on the surface of the base wafer and a gettering layer is formed in the interface region of the support substrate with the Box layer, a gettering layer is introduced on the back surface of the SOI wafer. More effective gettering sites can be obtained. Also, the thickness of the SOI wafer Box layer is getting thinner year by year. If the thickness of the Box layer is as thin as 100 nm or less, for example, even an ion implantation damage layer formed in the interface region between the support substrate and the Box layer is more effective for gettering of metal contamination in the SOI layer. .

  The SOI wafer manufacturing method of the present invention can be applied without any problem even if the insulating layer to be a Box layer is a silicon oxide film, a silicon nitride film, or the like. If a silicon oxide film is used, it is preferable to thermally oxidize the bond wafer or the base wafer, so that a dense and high-quality film can be easily produced. However, the present invention is not limited to this method. An oxide film may be deposited. Even when a silicon nitride film, a silicon oxynitride film, or another insulating film is formed, each can be formed by using a normal method. Further, a silicon nitride film and a silicon oxide film may be combined.

Further, in the method for producing an SOI wafer of the present invention, an n ⁺ layer may be further introduced in the vicinity of the layer on which the ion-implanted damaged layer of the present invention is formed. This n ⁺ layer may be required in terms of device structure, but it also has a gettering capability at the same time, so combined with the gettering capability by the ion implantation damage layer of neutral elements, more powerful gettering Become a site.
Specifically, at least prior to the bonding step, an n ⁺ layer is formed by ion implantation of elements serving as donors in silicon, that is, phosphorus, arsenic, antimony, etc., from the same surface as the surface on which neutral elements are ion-implanted. Such an n ⁺ layer can be introduced by introducing a process to be performed.

Further, even when an n ⁺ layer is introduced in addition to the ion implantation damage layer as described above, if the ion implantation damage layer is formed by ion implantation of a neutral amount of a dose according to the present invention, the bonding heat treatment is performed. Since the generation of secondary defects from the ion-implanted damaged layer can be suppressed, it is possible to prevent leakage defects and deterioration of the oxide film breakdown voltage.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples of the present invention, but the present invention is not limited thereto.

Example 1
In accordance with the steps shown in FIG. 1, an SOI wafer into which an ion-implanted damage layer was introduced was manufactured as follows.
First, two mirror-polished N-type silicon single crystal wafers having a diameter of 200 mm and a plane orientation {100} were prepared (a). On the surface of the base wafer 14, a silicon oxide film 13 having a thickness of about 1 μm to be a Box layer was formed by thermal oxidation (b).

Next, argon was ion-implanted into the surface of the bond wafer 11 under the conditions of an acceleration voltage of 100 keV and a dose of 1 × 10 ¹⁴ atoms / cm ² (c).

Next, the bond wafer 11 and the base wafer 14 were bonded to each other with the surface of the bond wafer 11 into which argon was ion-implanted as the bonding surface, with the silicon oxide film 13 interposed therebetween (d). Next, bonding heat treatment for increasing the bonding strength was performed under the following conditions (e). That is, a wafer bonded to a heat treatment furnace set at 800 ° C. is charged, heated up to a maximum temperature of 1150 ° C. at a heating rate of 10 ° C./min, held for 2 hours, and then cooled to 800 ° C. Was pulled out of the heat treatment furnace.
Thereafter, the bonded wafer 11 side of the bonded wafer 20 was thinned to a thickness of about 12 μm by surface grinding and mirror polishing to obtain an SOI wafer 50 (f).

The SOI wafer thus manufactured was cut in the thickness direction, the cut surface was polished, and then a cross-sectional TEM observation was performed.
Further, the gettering ability of the SOI wafer manufactured in this way was evaluated as follows. First, Ni was applied to the SOI layer surface at a concentration of about 1 × 10 ¹³ atoms / cm ² and diffused inside by heat treatment at 1000 ° C. for 1 hour. Next, the surface oxide film, SOI layer, Box layer, and support substrate surface layer (from the surface on the Box layer side to about 2 μm) are etched stepwise, and the Ni concentration in the solution is determined by ICP-MS (inductively coupled plasma mass). The distribution in the depth direction of the Ni concentration was measured by measuring with the analysis method. The surface oxide film and the Box layer were each measured in one step with an HF solution, the SOI layer was divided into six steps in about 2 μm steps from the surface of the SOI layer with a mixed acid solution, and the support substrate surface layer was measured in one step with a mixed acid solution.

(Examples 2, 3, and 4)
Example 1 except that the neutral element to be ion-implanted is carbon (Example 2), oxygen (Example 3), and silicon (Example 4), and the SOI layer is thinned to a thickness of about 14 μm. An SOI wafer was produced by the same method as described above. Thereafter, cross-sectional TEM observation of the SOI wafer was performed by the same method as in Example 1 to evaluate the gettering ability. However, the Ni concentration was measured by dividing the SOI layer into seven stages.

(Comparative Examples 1, 2, 3, 4)
Argon (Comparative Example 1), carbon (Comparative Example 2), oxygen (Comparative Example 3), and silicon (Comparative Example 4) were ion-implanted with a dose of 1 × 10 ¹⁵ atoms / cm ² , and the SOI layer was about 14 μm. An SOI wafer was manufactured in the same manner as in Example 1 except that the thickness was reduced to a thickness of. Thereafter, cross-sectional TEM observation of the SOI wafer was performed by the same method as in Example 1 to evaluate the gettering ability. However, the Ni concentration was measured by dividing the SOI layer into seven stages.

Cross-sectional TEM images of the SOI wafers of Examples 1 to 4 and Comparative Examples 1 to 4 are shown in FIG. The dotted line indicates the interface between the Box layer and the SOI layer including the ion implantation damage layer, and the broken line indicates a distance of 0.2 μm from the interface between the Box layer and the SOI layer.
Moreover, the result of the gettering ability evaluation of SOI wafer of Examples 1-4 and Comparative Examples 1-4 was shown in FIG. “SiO2” on the horizontal axis indicates the surface oxide film, “SOI-1 to 6 (7)” indicates the SOI layers measured by dividing them in order from the surface, “BOX” indicates the Box layer, and “BAS” For the support substrate, “SUM” indicates the total.
Table 1 summarizes the number of defects present in 1 μm × 1 μm measured by cross-sectional TEM observation of Examples 1 to 4 and Comparative Examples 1 to 4.

In any neutral element, when the dose is 1 × 10 ¹⁴ atoms / cm ² , defects that can be observed with a TEM image are hardly formed. Further, if the SOI layer has a distance of 0-2 μm from the Box layer (SOI-6 for argon, SOI-7 for other elements) as a gettering layer, Ni is trapped in this gettering layer. And has sufficient gettering ability.
On the other hand, when the dose amount is 1 × 10 ¹⁵ atoms / cm ² , the gettering ability is slightly stronger than when the dose amount is 1 × 10 ¹⁴ atoms / cm ² , but there is a defect at the interface. The formation of the SOI layer is considered to have an adverse effect on the characteristics of the SOI layer. In Table 1, “> 10” indicates several tens of levels, and “> 100” indicates several hundred levels. Further, as described above, when the dose amount is 1 × 10 ¹⁵ atoms / cm ² or more, ion implantation for a long time is required, resulting in low productivity and high cost.

(Comparative Example 5)
An SOI wafer was manufactured by the same method as in Example 1 except that the ion implantation damage layer was not formed on the bond wafer 11 by ion implantation, and the gettering ability was evaluated.
As a result, as shown in FIG. 5, Ni was distributed at a high concentration on the surface side of the SOI layer, and the gettering ability was extremely low.

(Examples 5 and 6, Comparative Example 6)
Further, each element of argon, carbon, oxygen, and silicon is dosed at a dose of 1 × 10 ¹² atoms / cm ² (Example 5), 1 × 10 ¹³ atoms / cm ² (Example 6), and 1 × 10 ¹⁶ atoms. An SOI wafer was manufactured in the same manner as in Example 1 except that ions were implanted as / cm ² (Comparative Example 6). Thereafter, cross-sectional TEM observation of the SOI wafer was performed in the same manner as in Example 1, and the results are also shown in Table 1.

For any neutral element, no defects were observed when the dose was 1 × 10 ¹² atoms / cm ² or 1 × 10 ¹³ atoms / cm ² .
On the other hand, when the dose amount is 1 × 10 ¹⁶ atoms / cm ² , the number of defects is too large for any neutral element, and measurement is impossible (indicated by “x” in Table 1). there were.

(Examples 7 to 16, Comparative Example 7)
Two N-type silicon single crystal wafers having a diameter of 200 mm and a mirror-polished surface orientation of {100} were prepared. A silicon oxide film having a thickness of about 1.3 μm to be a Box layer was formed on the surface of the base wafer by thermal oxidation.

  Subsequently, argon was ion-implanted on the surface of the bond wafer under the conditions shown in Table 2.

  Next, after bonding and bonding heat treatment by the same method as in Example 1, the bond wafer side was thinned to a thickness of about 14 μm by surface grinding and mirror polishing to obtain an SOI wafer. .

The gettering ability of the SOI wafer thus manufactured was evaluated by the same method as in Example 1. First, Ni was applied to the SOI surface at a concentration of about 5 × 10 ¹² atoms / cm ² and diffused inside by heat treatment at 1000 ° C. for 1 hour. Next, the surface oxide film, the SOI layer, the Box layer, and the support substrate surface layer were etched stepwise, and the Ni concentration in the solution was measured by ICP-MS to obtain the Ni concentration in the depth direction. . The surface oxide film and the Box layer were each measured in one step with an HF solution, the SOI layer was divided into seven steps in about 2 μm steps from the surface of the SOI layer with a mixed acid solution, and the support substrate surface layer was measured in one step with a mixed acid solution. Further, defects near the interface between the SOI layer and the Box layer were observed by cross-sectional TEM observation.

The gettering ability of Examples 7 to 11 and 16 and Comparative Example 7 is shown in FIG. The vertical axis represents the Ni concentration of the layer (gettering layer) whose distance from the Box layer of the SOI layer is 0 to 2 μm. When the dose amount was 5 × 10 ¹² atoms / cm ² or more (Examples 7 to 11 and Comparative Example 7), almost the entire amount of Ni applied to the surface was gettered. However, in Comparative Example 7, many defects were observed in the gettering layer by cross-sectional TEM observation as in FIG. In Example 11, defects were observed, but the density was not as high as in Comparative Example 7, and the occurrence of secondary defects was clearly suppressed.
When the dose was 1 × 10 ¹² atoms / cm ² (Example 16), almost no defects were formed, and the Ni concentration in the gettering layer was a stable value of 10 ¹¹ atoms / cm ² . However, the gettering ability is lower than those in Examples 7 to 11, and in order to obtain an SOI wafer having sufficient gettering ability more reliably, the dose amount should be 5 × 10 ¹² atoms / cm ² or more. It turns out that is good.

  The gettering ability of Examples 12 to 15 is shown in FIG. In any acceleration voltage, it had a sufficient gettering ability.

(Examples 17 to 20)
Two P-type silicon single crystal wafers having a diameter of 200 mm and a plane orientation of {100} and having been mirror-polished were prepared. A silicon oxide film having a thickness of about 75 nm was formed on the surface of the bond wafer, and a silicon oxide film having a thickness of about 225 nm was formed on the surface of the base wafer by thermal oxidation.

Next, hydrogen for ion implantation separation was ion-implanted on the surface of the bond wafer. Subsequently, argon was ion-implanted under the conditions of an acceleration voltage of 40 keV (Example 17), 60 keV (Example 18), 80 keV (Example 19), and 100 keV (Example 20). At that time, the dose was set to 1 × 10 ¹⁴ atoms / cm ² .

  Subsequently, an SOI wafer having a film thickness of about 0.3 μm was obtained through steps such as bonding, exfoliation heat treatment, bonding heat treatment, SOI layer adjustment oxidation, and oxide film removal by the same procedure as that of a normal ion implantation delamination method.

  Furthermore, a silicon layer having a thickness of about 2.7 μm was deposited on the surface of the SOI wafer by epitaxial growth, so that the thickness of the SOI layer was about 3 μm.

The gettering ability of the SOI wafer thus manufactured was evaluated by the same method as in Example 1. First, Ni was applied to the SOI surface at a concentration of about 5 × 10 ¹² atoms / cm ² and diffused inside by heat treatment at 1000 ° C. for 1 hour. Next, the surface oxide film, the SOI layer, the Box layer, and the support substrate surface layer were etched stepwise, and the Ni concentration in the solution was measured by ICP-MS to obtain the Ni concentration in the depth direction. . The surface oxide film and the Box layer were each measured in one step with an HF solution, the SOI layer was divided into five steps in about 0.6 μm steps from the SOI layer surface with a mixed acid solution, and the support substrate surface layer was measured in one step with a mixed acid solution. .

  The gettering ability of Examples 17 to 20 is shown in FIG. The vertical axis represents the Ni concentration of the layer (gettering layer) whose distance from the Box layer of the SOI layer is 0 to 0.6 μm. As in the case of Examples 12 to 15, the accelerating voltage was sufficient for any acceleration voltage.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is the figure which showed the outline of the manufacturing method of SOI wafer by the bonding method of this invention. 2A and 2B are cross-sectional views of an SOI wafer according to the present invention, in which FIG. 1A shows a case where an ion implantation damage layer is formed on a bond wafer, and FIG. 2B shows a case where an ion implantation damage layer is formed on a base wafer. It is a cross-sectional TEM photograph near the ion implantation damage layer of SOI wafer obtained by Examples 1-4 and Comparative Examples 1-4. It is a figure which shows the gettering capability of the SOI wafer obtained in Examples 1-4 and Comparative Examples 1-4. 6 is a diagram showing the gettering ability of an SOI wafer obtained in Comparative Example 5. FIG. It is a figure which shows the gettering capability of SOI wafer obtained by Examples 7-11 and 16 and the comparative example 7. FIG. It is a figure which shows the gettering capability of the SOI wafer obtained in Examples 12-15. It is a figure which shows the gettering capability of the SOI wafer obtained in Examples 17-20.

Explanation of symbols

11 ... Bond wafer, 12 ... Ion-implanted damage layer, 13 ... Insulating film,
14 ... Base wafer, 15 ... Laminated surface,
20 ... Laminated wafer,
50 ... SOI wafer,
51 ... SOI layer, 52 ... Ion implantation damage layer, 53 ... Box layer,
54: Support substrate.

Claims (8)

at least,
A step of preparing a base wafer and a bond wafer made of silicon single crystal;
Forming an insulating film on the surface of the bond wafer;
A step of forming an ion-implanted damage layer by ion-implanting at least one of argon, carbon, oxygen, and silicon as a neutral element electrically inactive in silicon from the surface of the bond wafer on which the insulating film is formed. When,
Bonding the base wafer and the bond wafer to the ion-implanted surface via the insulating film;
Forming a thin film of the bonded bond wafer , and at least prior to the bonding process, ion-implanting an element serving as a donor in silicon from a surface on which the neutral element is ion-implanted to form an n ⁺ layer In the method for manufacturing an SOI wafer including a step of forming, the ion implantation of the neutral element in the ion implantation damage layer forming step includes:
When carbon is ion-implanted as the neutral element, the dose is set to 1 × 10 ¹² atoms / cm ² or more and 1 × 10 ¹³ atoms / cm ² or less, and when ion implantation of argon, oxygen, or silicon is performed, the dose amount is set. Is performed at 1 × 10 ¹² atoms / cm ² or more and less than 1 × 10 ¹⁵ atoms / cm ² .   2. The method for manufacturing an SOI wafer according to claim 1, wherein an acceleration voltage at the time of ion-implanting the neutral element is set to 200 keV or less.   3. The method for manufacturing an SOI wafer according to claim 1, wherein the thickness of the ion-implanted damaged layer is 0.5 [mu] m or less.   4. The method for manufacturing an SOI wafer according to claim 1, wherein the insulating film is a silicon oxide film, a silicon nitride film, or a combination thereof.   5. The method for manufacturing an SOI wafer according to claim 1, wherein the thinning of the bond wafer is performed by grinding the bond wafer.   In the thinning process of the bond wafer, in advance, the ion implantation layer for peeling is provided by ion-implanting hydrogen or helium from the surface of the bond wafer before the bonding process, and in the thinning process of the bond wafer, 5. The method for manufacturing an SOI wafer according to claim 1, wherein the bonding wafer is peeled off by the peeling ion implantation layer by a peeling heat treatment. 6. 2. The method for producing an SOI wafer according to claim 1 , wherein the donor element is at least one of phosphorus, arsenic, and antimony. The dose of the ion implantation of the neutral ^{element, 5 × 10 12 atoms / cm} 2 or more and a manufacturing method of an SOI wafer according to any one of claims 1 to 7, characterized in that.

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