JPH11307471A - Manufacture for soi substrate - Google Patents

Manufacture for soi substrate

Info

Publication number
JPH11307471A
JPH11307471A JP11159698A JP11159698A JPH11307471A JP H11307471 A JPH11307471 A JP H11307471A JP 11159698 A JP11159698 A JP 11159698A JP 11159698 A JP11159698 A JP 11159698A JP H11307471 A JPH11307471 A JP H11307471A
Authority
JP
Japan
Prior art keywords
substrate
silicon substrate
type
layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11159698A
Other languages
Japanese (ja)
Other versions
JP3452123B2 (en
Inventor
Takeshi Nakajima
健 中嶋
Tetsuya Nakai
哲弥 中井
Kenji Tomizawa
憲治 冨澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP11159698A priority Critical patent/JP3452123B2/en
Publication of JPH11307471A publication Critical patent/JPH11307471A/en
Application granted granted Critical
Publication of JP3452123B2 publication Critical patent/JP3452123B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)

Abstract

PROBLEM TO BE SOLVED: To have great gettering capability and eliminate contamination on a semiconductor layer with heavy metal impurities an SOI substrate in which the semiconductor layers made by use of hydrogen ion injection art are superimposed on a semiconductor substrate via an oxide film. SOLUTION: An oxide film 12 is formed on a surface of a p-type first silicon substrate 11. Hydrogen ions are injected from a surface of a first substrate to form a hydrogen ion injection region 11a inside the substrate. A p<+> -type or p<++> polysilicon layer 14 is formed on one face of a p-type second silicon substrate 13 to be a support substrate. A p-type polysilicon layer 16 is formed on the polysilicon layer 14 to be ground. The second substrate is superimposed on the first substrate so that this polysilicon layer 16 is closely adhered to the oxide film, to be closely adhered to each other. The first substrate is closely adhered to the second substrate to heat them, while the first substrate is separated from the second substrate in a hydrogen ion injection region 11a to form a silicon layer 11b on a surface of the second substrate. The second substrate is further heated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、水素イオン注入技
術を用いて作製される絶縁膜上に半導体層を設けたSO
I(Silicon On Insulator)基板の製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SO film having a semiconductor layer provided on an insulating film manufactured by using a hydrogen ion implantation technique.
The present invention relates to a method for manufacturing an I (Silicon On Insulator) substrate.

【0002】[0002]

【従来の技術】この種のSOI基板は将来の超高集積回
路(ULSI)基板として注目されてきている。このS
OI基板の製造方法には、シリコン基板同士を絶縁膜
を介して貼り合わせる方法、絶縁性基板又は絶縁性薄
膜を表面に有する基板の上にシリコン薄膜を堆積させる
方法、シリコン基板の内部に高濃度の酸素イオンを注
入した後、高温でアニール処理してこのシリコン基板表
面から所定の深さの領域に埋込みシリコン酸化層を形成
し、その表面側のSi層を活性領域とするSIMOX法
などがある。また最近、半導体基板に水素イオン等の注
入を行った後に、この半導体基板をイオン注入面を重ね
合せ面として支持基板に重ね合せ、この積層体を500
℃を越える温度に昇温して上記半導体基板を上記水素イ
オン等を注入した領域で支持基板から分離し、支持基板
の表面に半導体の薄膜を有する薄い半導体材料フィルム
の製造方法が提案されている(特開平5−21112
8)。この方法では、イオンを半導体基板の内部に表面
から均一に注入できれば、均一な厚さの薄い半導体層を
有する半導体基板が得られる。また支持基板の表面に予
め酸化膜を設けておけば、この方法により支持基板とこ
の基板上に形成されて埋込み酸化膜として作用する酸化
膜とこの酸化膜上に形成された半導体層とを有するSO
I基板を製造することができる。
2. Description of the Related Art An SOI substrate of this kind has attracted attention as a future ultra-high integrated circuit (ULSI) substrate. This S
The method of manufacturing an OI substrate includes a method of bonding silicon substrates to each other via an insulating film, a method of depositing a silicon thin film on an insulating substrate or a substrate having an insulating thin film on the surface, and a method of forming a high-concentration silicon inside a silicon substrate. After implanting oxygen ions, annealing is performed at a high temperature to form a buried silicon oxide layer at a predetermined depth from the surface of the silicon substrate, and there is a SIMOX method using the Si layer on the surface as an active region. . Also, recently, after implanting hydrogen ions or the like into a semiconductor substrate, the semiconductor substrate is superimposed on a support substrate with the ion-implanted surface as an overlapping surface, and this laminate is
A method for producing a thin semiconductor material film having a semiconductor thin film on the surface of a supporting substrate has been proposed in which the temperature of the semiconductor substrate is raised to a temperature exceeding ℃ to separate the semiconductor substrate from the supporting substrate in a region where the hydrogen ions or the like are implanted. (JP-A-5-21112
8). According to this method, a semiconductor substrate having a thin semiconductor layer having a uniform thickness can be obtained if ions can be uniformly implanted into the inside of the semiconductor substrate from the surface. If an oxide film is provided on the surface of the support substrate in advance, the method has a support substrate, an oxide film formed on the substrate and acting as a buried oxide film, and a semiconductor layer formed on the oxide film. SO
An I substrate can be manufactured.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記酸化膜上
に形成された上記半導体層がデバイスプロセス中に重金
属不純物により汚染された場合には、埋込み酸化膜がゲ
ッタリング能力を有するゲッタリング層となって重金属
不純物を捕捉した後で、熱処理の進行に伴って結晶化し
た酸化層が一旦捕捉した重金属不純物を上記半導体層中
に放出し再分布を生じ易く、これに起因して半導体層の
汚染による品質劣化が生じる問題がある。本発明の目的
は、水素イオン注入技術を用いて作製される半導体層が
酸化膜を介して半導体基板上に重ね合わされているSO
I基板において、大きなゲッタリング能力を有し半導体
層を重金属不純物で汚染させないSOI基板の製造方法
を提供することにある。
However, if the semiconductor layer formed on the oxide film is contaminated by heavy metal impurities during the device process, the buried oxide film may be replaced with a gettering layer having gettering ability. After the heavy metal impurities are trapped, the oxide layer crystallized with the progress of the heat treatment releases the trapped heavy metal impurities into the semiconductor layer and tends to redistribute, thereby causing contamination of the semiconductor layer. There is a problem that the quality is deteriorated due to this. An object of the present invention is to provide a SOI in which a semiconductor layer formed by using a hydrogen ion implantation technique is superposed on a semiconductor substrate via an oxide film.
An object of the present invention is to provide a method for manufacturing an SOI substrate which has a large gettering ability and does not contaminate a semiconductor layer with heavy metal impurities.

【0004】[0004]

【課題を解決するための手段】請求項1に係る発明は、
図1に示すように、p型の第1シリコン基板11の表面
に酸化膜12を形成する工程と、第1シリコン基板11
の表面から水素イオンを注入して第1シリコン基板11
内部に水素イオン注入領域11aを形成する工程と、支
持基板となるp型の第2シリコン基板13の片面にp+
型又はp++型のポリシリコン層14を形成する工程と、
第2シリコン基板13のp+型又はp++型のポリシリコ
ン層14上にp-型のポリシリコン層16を形成する工
程と、このp-型のポリシリコン層16を鏡面研磨する
工程と、酸化膜12にp-型のポリシリコン層16が密
着するように第1シリコン基板11に第2シリコン基板
13を重ね合わせて密着させる工程と、第1シリコン基
板11を第2シリコン基板13に密着させたまま所定の
温度で熱処理して第1シリコン基板11を水素イオン注
入領域11aで第2シリコン基板13から分離して第2
シリコン基板13の表面にシリコン層11bを形成する
工程と、表面にシリコン層11bを有する第2シリコン
基板13を更に熱処理する工程とを含むSOI基板の製
造方法である。図1に示すように、酸化膜12の下側に
はこれに密着してp-型のポリシリコン層16及びp+
又はp++型のポリシリコン層14が形成されているた
め、シリコン層11bがデバイスプロセス中に重金属不
純物により汚染されても、p-型のポリシリコン層16
及びp+型又はp++型のポリシリコン層14がゲッタリ
ング層として作用する。これはポリシリコン層における
シリコン粒界が重金属不純物をゲッタリングすることに
よるものである。また、p+型又はp++型のポリシリコ
ン層では欠陥が発生しやすい。この欠陥によりゲッタリ
ング能力が高くなる。更にボロンは鉄等の重金属不純物
と安定な鉄−ボロン対を形成することから、ボロン濃度
の高いp+型又はp++型のポリシリコン層では、この点
からも重金属不純物に対するゲッタリング能力が高い。
即ち、シリコン層11b中の重金属不純物が酸化膜12
を通過してp-型のポリシリコン層16及びp+型又はp
++型のポリシリコン層14に捕捉され、熱処理が進行し
てもシリコン層11bは重金属不純物で汚染されない。
また酸化膜12とp+型又はp++型のポリシリコン層1
4との間にはp-型のポリシリコン層16が形成されて
いるため、このp-型のポリシリコン層16の厚さをデ
バイス設計に合わせて変えることにより、シリコン層1
1bに形成された素子動作時における空乏層の広がりへ
の影響を抑制することができる。
The invention according to claim 1 is
As shown in FIG. 1, a step of forming an oxide film 12 on the surface of a p-type first silicon substrate 11,
Implanting hydrogen ions from the surface of the first silicon substrate 11
A step of forming a hydrogen ion implanted region 11a therein and a step of forming p + on one surface of a p-type second silicon substrate 13 serving as a support substrate;
Forming a p-type or p ++ -type polysilicon layer 14;
Forming a type polysilicon layer 16, the p - - p on p + -type or p ++ type polysilicon layer 14 of the second silicon substrate 13 and the step of mirror polishing the polysilicon layer 16 of the mold A step of superimposing the second silicon substrate 13 on the first silicon substrate 11 so that the p type polysilicon layer 16 is in close contact with the oxide film 12, and attaching the first silicon substrate 11 to the second silicon substrate 13. The first silicon substrate 11 is separated from the second silicon substrate 13 in the hydrogen ion implanted region 11a by performing a heat treatment at a predetermined temperature with
An SOI substrate manufacturing method includes a step of forming a silicon layer 11b on the surface of a silicon substrate 13 and a step of further heat-treating the second silicon substrate 13 having the silicon layer 11b on the surface. As shown in FIG. 1, a p type polysilicon layer 16 and a p + type or p ++ type polysilicon layer 14 are formed below and in close contact with the oxide film 12. Even if the layer 11b is contaminated by heavy metal impurities during the device process, the p - type polysilicon layer 16
And the p + type or p ++ type polysilicon layer 14 functions as a gettering layer. This is because the silicon grain boundaries in the polysilicon layer getter heavy metal impurities. Further, defects are likely to occur in the p + type or p ++ type polysilicon layer. This defect increases gettering ability. Further, since boron forms a stable iron-boron pair with heavy metal impurities such as iron, the gettering ability with respect to heavy metal impurities is also high in the p + type or p ++ type polysilicon layer having a high boron concentration. high.
That is, the heavy metal impurities in the silicon layer 11b
Through the p - type polysilicon layer 16 and the p + type or p
The silicon layer 11b is trapped by the ++ type polysilicon layer 14 and is not contaminated with heavy metal impurities even if the heat treatment proceeds.
Also, an oxide film 12 and a p + type or p ++ type polysilicon layer 1 are formed.
Since the type polysilicon layer 16 is formed, the p - - is between 4 p by changing combined thickness of the type polysilicon layer 16 in device design, silicon layer 1
The effect on the expansion of the depletion layer during operation of the device formed in 1b can be suppressed.

【0005】請求項2に係る発明は、図2に示すよう
に、p型の第1シリコン基板11の表面に酸化膜12を
形成する工程と、第1シリコン基板11の表面から水素
イオンを注入して第1シリコン基板11内部に水素イオ
ン注入領域11aを形成する工程と、支持基板となるp
型の第2シリコン基板13の表面からリンをイオン注入
して第2シリコン基板13内部にリン注入層13aを形
成する工程と、酸化膜12に上記リンをイオン注入した
表面が密着するように第1シリコン基板11に第2シリ
コン基板13を重ね合わせて密着させる工程と、第1シ
リコン基板11を第2シリコン基板13に密着させたま
ま所定の温度で熱処理して第1シリコン基板11を水素
イオン注入領域11aで第2シリコン基板13から分離
して第2シリコン基板13の表面にシリコン層11bを
形成する工程と、表面にシリコン層11bを有する第2
シリコン基板13を更に熱処理する工程とを含むSOI
基板の製造方法である。図2に示すように、酸化膜12
の下側の第2シリコン基板13の内部にはリン注入層1
3aが形成されているため、シリコン層11bがデバイ
スプロセス中に重金属不純物により汚染されても、リン
注入層13aがゲッタリング層として作用する。これ
は、リン注入により発生した欠陥、及びリンを導入した
ことにより金属元素の固溶限が増大したことによる作用
である。即ちシリコン層11b中の重金属不純物が酸化
膜12を通過してリン注入層13aに捕捉され、熱処理
が進行してもシリコン層11bは重金属不純物で汚染さ
れない。
According to a second aspect of the present invention, as shown in FIG. 2, a step of forming an oxide film 12 on the surface of a p-type first silicon substrate 11 and implanting hydrogen ions from the surface of the first silicon substrate 11 Forming a hydrogen ion implanted region 11a inside the first silicon substrate 11 by using
Forming a phosphorus-implanted layer 13a in the second silicon substrate 13 by ion-implanting phosphorus from the surface of the second silicon substrate 13 of the mold; A step of superimposing the second silicon substrate 13 on the first silicon substrate 11 and bringing the second silicon substrate 13 into close contact therewith, and performing a heat treatment at a predetermined temperature while keeping the first silicon substrate 11 in close contact with the second silicon substrate 13 so that the first silicon substrate 11 is exposed to hydrogen ions. Forming a silicon layer 11b on the surface of the second silicon substrate 13 separated from the second silicon substrate 13 in the implantation region 11a, and forming a second layer having the silicon layer 11b on the surface.
Further heat-treating the silicon substrate 13.
This is a method for manufacturing a substrate. As shown in FIG.
Inside the second silicon substrate 13 below the
Since the layer 3a is formed, even if the silicon layer 11b is contaminated with heavy metal impurities during the device process, the phosphorus injection layer 13a functions as a gettering layer. This is due to the defect generated by the phosphorus implantation and the increase in the solid solubility limit of the metal element due to the introduction of phosphorus. That is, the heavy metal impurities in the silicon layer 11b pass through the oxide film 12 and are captured by the phosphorus implantation layer 13a, and the silicon layer 11b is not contaminated by the heavy metal impurities even if the heat treatment proceeds.

【0006】請求項3に係る発明は、図3に示すよう
に、p型の第1シリコン基板11の表面に酸化膜12を
形成する工程と、第1シリコン基板11の表面から水素
イオンを注入して第1シリコン基板11内部に水素イオ
ン注入領域11aを形成する工程と、支持基板となるp
型の第2シリコン基板13の表面からリンをイオン注入
して第2シリコン基板13内部にリン注入層13aを形
成する工程と、リン注入層13aを形成した第2シリコ
ン基板13の表面にp-型のポリシリコン層16を形成
する工程と、この前記p-型のポリシリコン層16鏡面
研磨する工程と、酸化膜12に鏡面研磨したp-型のポ
リシリコン層16が密着するように第1シリコン基板1
1に第2シリコン基板13を重ね合わせて密着させる工
程と、第1シリコン基板11を第2シリコン基板13に
密着させたまま所定の温度で熱処理して第1シリコン基
板11を水素イオン注入領域11aで第2シリコン基板
13から分離して第2シリコン基板13の表面にシリコ
ン層11bを形成する工程と、表面にシリコン層11b
を有する第2シリコン基板13を更に熱処理する工程と
を含むSOI基板の製造方法である。図3に示すよう
に、酸化膜12の下側の第2シリコン基板13の内部に
はリン注入層13aが形成されているため、シリコン層
11bがデバイスプロセス中に重金属不純物により汚染
されても、P-型のポリシリコン層16及びリン注入層
13aがゲッタリング層として作用する。即ちシリコン
層11b中の重金属不純物が酸化膜12を通過してリン
注入層13aに捕捉され、熱処理が進行してもシリコン
層11bは重金属不純物で汚染されない。また酸化膜1
2とリン注入層13aとの間にはp-型のポリシリコン
層16が形成されているため、このp-型のポリシリコ
ン層16の厚さをデバイス設計に合わせて変えることに
より、シリコン層11bに形成された素子動作時におけ
る空乏層の広がりへの影響を抑制することができる。
According to a third aspect of the present invention, as shown in FIG. 3, a step of forming an oxide film 12 on the surface of a p-type first silicon substrate 11 and implanting hydrogen ions from the surface of the first silicon substrate 11 Forming a hydrogen ion implanted region 11a inside the first silicon substrate 11 by using
Forming a phosphorus-implanted layer 13a within the second silicon substrate 13 by phosphorus ion implantation from the surface of the second silicon substrate 13 of the mold, p on the surface of the second silicon substrate 13 formed with phosphorus implantation layer 13a - Forming the p - type polysilicon layer 16, mirror-polishing the p - type polysilicon layer 16, and forming the first polysilicon layer 16 so that the mirror-polished p - type polysilicon layer 16 adheres to the oxide film 12. Silicon substrate 1
1. a step of superimposing the second silicon substrate 13 on the first silicon substrate 13 and a step of heat-treating the first silicon substrate 11 at a predetermined temperature while keeping the first silicon substrate 11 in close contact with the second silicon substrate 13 so as to bring the first silicon substrate 11 into the hydrogen ion implanted region 11a. Forming a silicon layer 11b on the surface of the second silicon substrate 13 by separating the silicon layer 11b from the second silicon substrate 13;
And a step of further heat-treating the second silicon substrate 13 having the following. As shown in FIG. 3, since the phosphorus implantation layer 13a is formed inside the second silicon substrate 13 below the oxide film 12, even if the silicon layer 11b is contaminated by heavy metal impurities during the device process, The P type polysilicon layer 16 and the phosphorus implantation layer 13a function as gettering layers. That is, the heavy metal impurities in the silicon layer 11b pass through the oxide film 12 and are captured by the phosphorus implantation layer 13a, and the silicon layer 11b is not contaminated by the heavy metal impurities even if the heat treatment proceeds. Oxide film 1
Since the type polysilicon layer 16 is formed, the p - - p is between 2 and phosphorus injection layer 13a by changing the combined thickness of the type polysilicon layer 16 in device design, silicon layer The effect on the expansion of the depletion layer during the operation of the element formed in 11b can be suppressed.

【0007】[0007]

【発明の実施の形態】次に本発明の実施の形態を図面に
基づいて説明する。図1に示すように、本発明の第1の
実施形態のSOI基板を製造するには、先ずp型の第1
単結晶シリコン基板11を用意する。この第1単結晶基
板11はドーパントとしてボロン(B)を使用すること
により作製される。第1単結晶基板11の表面に熱酸化
により絶縁層である酸化膜12を形成する(図1
(a))。この酸化膜12は0.1〜2μm、好ましく
は0.1〜0.5μmの厚さになるように形成される。
次いで、酸化膜12を有するp型単結晶基板11の表面
から水素イオンを1〜10×1016/cm2のドーズ量
及び50〜200keVの加速エネルギーでイオン注入
する。その結果、単結晶基板11内部にイオン注入領域
11aが形成される(図1(b))。次いで上記単結晶
基板11と同一表面積を有し、支持基板となるp型の第
2単結晶シリコン基板13を用意し、この第2単結晶基
板13の表面にCVD法によりp+型又はp++型のポリ
シリコン層14を形成する(図1(c))。p+型又は
++型のポリシリコン層14はp型の第1単結晶基板1
1よりもドーパントであるボロンの濃度を高くして形成
される。このポリシリコン層14は0.5〜3μm、好
ましくは0.5〜2μmの厚さになるように形成され
る。次いでこのp+型又はp++型のポリシリコン層14
上にp-型のポリシリコン層16を形成する(図1
(d))。このp-型のポリシリコン層16は0.5〜
3μm、好ましくは0.5〜2μmの厚さになるように
形成される。p-型のポリシリコン層16は、p+型又は
++型のポリシリコン層14よりもボロン濃度を低くし
て形成される。好ましくは、第1単結晶基板11と同等
とする。次いで、p-型ポリシリコン層16を鏡面研磨
し平坦化する。次いで第1単結晶基板11と第2単結晶
基板13をそれぞれ洗浄した後、酸化膜12にp-型の
ポリシリコン層16が密着するように第1単結晶基板1
1に第2単結晶基板13を重ね合わせて密着させる(図
1(e))。次いで第1単結晶基板11を第2単結晶基
板13に密着させたまま窒素雰囲気中で500〜800
℃の範囲に昇温し、5〜30分保持して薄膜分離熱処理
を行う。これにより第1単結晶基板11が水素イオンの
注入ピーク位置に相当するイオン注入領域11aのとこ
ろで割れて上部の厚肉部11cと下部の薄い半導体層1
1bに分離する(図1(f))。次に温度を下げて厚肉
部11cを取除く(図1(g))。次いで表面にp+
又はp++型のポリシリコン層14、p-型のポリシリコ
ン層16、酸化膜12及び半導体層11bが順次積層さ
れた第2単結晶基板13を酸素又は窒素雰囲気中におい
て900〜1200℃で30〜120分間熱処理して、
半導体層11bと第2単結晶基板13とをp+型又はp
++型のポリシリコン層14、p-型のポリシリコン層1
6及び酸化膜12を介して強固に貼り合わせる(図1
(h))。最後に半導体層11bの分離面及び厚肉部1
1cの分離面をそれぞれ研磨(タッチポリッシング)し
て平滑化する(図1(i)及び図1(j))。これによ
り第2単結晶基板13はSOI基板となり、厚肉部11
cは新たな半導体基板として再びSOI基板の製造に利
用できる。
Embodiments of the present invention will now be described with reference to the drawings. As shown in FIG. 1, in order to manufacture the SOI substrate according to the first embodiment of the present invention, first, a p-type first
A single crystal silicon substrate 11 is prepared. The first single crystal substrate 11 is manufactured by using boron (B) as a dopant. An oxide film 12 as an insulating layer is formed on the surface of the first single crystal substrate 11 by thermal oxidation.
(A)). This oxide film 12 is formed to have a thickness of 0.1 to 2 μm, preferably 0.1 to 0.5 μm.
Next, hydrogen ions are implanted from the surface of the p-type single crystal substrate 11 having the oxide film 12 with a dose of 1 to 10 × 10 16 / cm 2 and an acceleration energy of 50 to 200 keV. As a result, an ion implantation region 11a is formed inside the single crystal substrate 11 (FIG. 1B). Next, a p-type second single-crystal silicon substrate 13 having the same surface area as the single-crystal substrate 11 and serving as a support substrate is prepared, and the surface of the second single-crystal substrate 13 is p + -type or p + A + type polysilicon layer 14 is formed (FIG. 1C). The p + -type or p ++ -type polysilicon layer 14 is a p-type first single crystal substrate 1.
It is formed with a higher concentration of boron as a dopant than 1. This polysilicon layer 14 is formed to have a thickness of 0.5 to 3 μm, preferably 0.5 to 2 μm. Then, the p + type or p ++ type polysilicon layer 14 is formed.
A p - type polysilicon layer 16 is formed thereon (FIG. 1).
(D)). The p - type polysilicon layer 16 has a thickness of 0.5 to
It is formed to have a thickness of 3 μm, preferably 0.5 to 2 μm. The p type polysilicon layer 16 is formed with a lower boron concentration than the p + type or p ++ type polysilicon layer 14. Preferably, it is equivalent to the first single crystal substrate 11. Next, the p type polysilicon layer 16 is mirror-polished and flattened. Next, after cleaning the first single crystal substrate 11 and the second single crystal substrate 13 respectively, the first single crystal substrate 1 is so bonded that the p type polysilicon layer 16 is in close contact with the oxide film 12.
The second single crystal substrate 13 is superimposed on and adhered to the substrate 1 (FIG. 1E). Then, the first single crystal substrate 11 is kept in close contact with the second single crystal substrate 13 in a nitrogen atmosphere at 500 to 800
The temperature is raised to the range of ° C., and the film is held for 5 to 30 minutes to perform the heat treatment for thin film separation. As a result, the first single crystal substrate 11 is broken at the ion implantation region 11a corresponding to the peak position of hydrogen ion implantation, and the upper thick portion 11c and the lower thin semiconductor layer 1 are separated.
1b (FIG. 1 (f)). Next, the temperature is lowered to remove the thick portion 11c (FIG. 1 (g)). Next, a second single crystal substrate 13 having a p + -type or p ++ -type polysilicon layer 14, a p -type polysilicon layer 16, an oxide film 12, and a semiconductor layer 11b sequentially laminated on the surface thereof is placed in an oxygen or nitrogen atmosphere. Heat treatment at 900-1200 ° C. for 30-120 minutes,
The semiconductor layer 11b and the second single crystal substrate 13 are p + -type or p-type
++ type polysilicon layer 14, p type polysilicon layer 1
6 and the oxide film 12 (FIG. 1)
(H)). Finally, the separation surface and the thick portion 1 of the semiconductor layer 11b
The separation surfaces 1c are polished (touch polished) and smoothed (FIGS. 1 (i) and 1 (j)). Thereby, the second single crystal substrate 13 becomes an SOI substrate, and the thick portion 11
c can be used again as a new semiconductor substrate in the manufacture of an SOI substrate.

【0008】図2に示すように、本発明の第2の実施形
態のSOI基板を製造するには、図1に基づく第1形態
の場合と同じ工程を繰返して、p型の第1単結晶シリコ
ン基板11の表面に酸化膜12を形成する(図2
(a))。次いで、第1形態の場合と同様に酸化膜12
を有する第1単結晶基板11の表面から水素イオン注入
して、基板11内部にイオン注入領域11aを形成する
(図2(b))。次いで第1単結晶シリコン基板11と
同一表面積を有し、支持基板となるp型の第2単結晶シ
リコン基板13を用意し、このp型の第2単結晶基板1
3の表面からリンをイオン注入して第2単結晶基板13
内部にリン注入層13aを形成する(図2(c))。次
に第1基板11と第2基板13の貼合わせ接合強度を高
めるために、リン注入後、第2基板13の表面を研磨し
て基板表面のマイクロラフネスをポリシュドウェーハ程
度にしておくことが好ましい。次いで第1単結晶基板1
1と第2単結晶基板13をそれぞれ洗浄した後、第1単
結晶基板11に酸化膜12を介して第2単結晶基板13
を重ね合わせて密着させる(図2(d))。次いで第1
単結晶基板11を第2単結晶基板13に密着させたまま
第1形態と同様の薄膜分離熱処理を行う。これにより第
1単結晶基板11がイオン注入領域11aのところで割
れて上部の厚肉部11cと下部の薄い半導体層11bに
分離する(図2(e))。次に温度を下げて厚肉部11
cを取除き(図2(f))、表面に酸化膜12及び半導
体層11bが順次積層された第2単結晶基板13を第1
形態の場合と同様に熱処理して半導体層11bと第2単
結晶基板13とを酸化膜12を介して強固に貼り合わせ
る(図2(g))。最後に半導体層11bの分離面及び
厚肉部11cの分離面をそれぞれ研磨して平滑化する
(図2(h)及び図2(i))。これにより表面に酸化
膜12及び半導体層11bが順次積層された第2単結晶
基板13からなるSOI基板を得る(図2(h))。
As shown in FIG. 2, in order to manufacture an SOI substrate according to a second embodiment of the present invention, the same steps as those of the first embodiment based on FIG. 1 are repeated to form a p-type first single crystal. An oxide film 12 is formed on the surface of a silicon substrate 11 (see FIG. 2).
(A)). Next, as in the case of the first embodiment, the oxide film 12 is formed.
Hydrogen ions are implanted from the surface of the first single-crystal substrate 11 having an ion implantation region 11a inside the substrate 11 (FIG. 2B). Next, a p-type second single-crystal silicon substrate 13 having the same surface area as the first single-crystal silicon substrate 11 and serving as a support substrate is prepared.
3 is ion-implanted from the surface of
A phosphorus injection layer 13a is formed inside (FIG. 2C). Next, in order to increase the bonding strength between the first substrate 11 and the second substrate 13, the surface of the second substrate 13 is polished after phosphorus implantation to reduce the micro roughness of the substrate surface to about a polished wafer. preferable. Next, the first single crystal substrate 1
After cleaning the first and second single crystal substrates 13 respectively, the second single crystal substrate 13 is placed on the first single crystal substrate 11 via the oxide film 12.
Are overlapped and adhered (FIG. 2D). Then the first
While the single crystal substrate 11 is kept in close contact with the second single crystal substrate 13, the same thin film separation heat treatment as in the first embodiment is performed. As a result, the first single crystal substrate 11 is broken at the ion implantation region 11a and separated into an upper thick portion 11c and a lower thin semiconductor layer 11b (FIG. 2E). Next, the temperature is lowered and the thick portion 11
c (FIG. 2 (f)), and the second single crystal substrate 13 on which the oxide film 12 and the semiconductor layer 11b are sequentially laminated is placed on the first single crystal substrate 13.
The semiconductor layer 11b and the second single crystal substrate 13 are firmly bonded to each other through the oxide film 12 by performing a heat treatment in the same manner as in the embodiment (FIG. 2G). Finally, the separation surface of the semiconductor layer 11b and the separation surface of the thick portion 11c are polished and smoothed, respectively (FIGS. 2 (h) and 2 (i)). Thus, an SOI substrate including the second single crystal substrate 13 on which the oxide film 12 and the semiconductor layer 11b are sequentially stacked is obtained (FIG. 2H).

【0009】図3に示すように、本発明の第3の実施形
態のSOI基板を製造するには、図1に基づく第1形態
の場合と同じ工程を繰返して、p型の第1単結晶シリコ
ン基板11の表面に酸化膜12を形成する(図3
(a))。次いで第1形態の場合と同様に酸化膜12を
有する第1単結晶基板11の表面から水素イオン注入し
て、基板11内部にイオン注入領域11aを形成する
(図3(b))。次いで第1単結晶シリコン基板11と
同一表面積を有し、支持基板となるp型の第2単結晶シ
リコン基板13を用意し、このp型の第2単結晶基板1
3の表面からリンをイオン注入して第2単結晶基板13
内部にリン注入層13aを形成する(図3(c))。次
いでリン注入層13aを形成した第2単結晶基板13の
表面にp-型のポリシリコン層16を形成する(図3
(d))。このp-型のポリシリコン層16は0.5〜
3μm、好ましくは0.5〜2μmの厚さになるように
形成する。p-型のポリシリコン層16のボロン濃度は
第1単結晶基板11と同等であることが好ましい。次い
で、p-型のポリシリコン層16を鏡面研磨し平坦化す
る。次いで第1単結晶基板11と第2単結晶基板13を
それぞれ洗浄した後、酸化膜12にp-型のポリシリコ
ン層16が密着するように第1単結晶基板11に第2単
結晶基板13を重ね合わせて密着させる(図3
(e))。次いで第1単結晶基板11を第2単結晶基板
13に密着させたまま第1形態と同様の薄膜分離熱処理
を行う。これにより第1単結晶基板11がイオン注入領
域11aのところで割れて上部の厚肉部11cと下部の
薄い半導体層11bに分離する(図3(f))。次に温
度を下げて厚肉部11cを取除き(図3(g))、表面
にp-型ポリシリコン層16、酸化膜12及び半導体層
11bが順次積層された第2単結晶基板13を第1形態
の場合と同様に熱処理して半導体層11bと第2単結晶
基板13とを酸化膜12及びp-型ポリシリコン層16
を介して強固に貼り合わせる(図3(h))。最後に半
導体層11bの分離面及び厚肉部11cの分離面をそれ
ぞれ研磨して平滑化する(図3(i)及び図3
(j))。これにより表面にp-型ポリシリコン層1
6、酸化膜12及び半導体層11bが順次積層された第
2単結晶基板13からなるSOI基板を得る(図3
(i))。
As shown in FIG. 3, in order to manufacture an SOI substrate according to a third embodiment of the present invention, the same steps as those of the first embodiment based on FIG. 1 are repeated to form a p-type first single crystal. An oxide film 12 is formed on the surface of a silicon substrate 11 (FIG. 3)
(A)). Next, as in the case of the first embodiment, hydrogen ions are implanted from the surface of the first single crystal substrate 11 having the oxide film 12 to form an ion implantation region 11a inside the substrate 11 (FIG. 3B). Next, a p-type second single-crystal silicon substrate 13 having the same surface area as the first single-crystal silicon substrate 11 and serving as a support substrate is prepared.
3 is ion-implanted from the surface of
A phosphorus injection layer 13a is formed inside (FIG. 3C). Next, a p type polysilicon layer 16 is formed on the surface of the second single crystal substrate 13 on which the phosphorus implantation layer 13a is formed (FIG. 3).
(D)). The p - type polysilicon layer 16 has a thickness of 0.5 to
It is formed to have a thickness of 3 μm, preferably 0.5 to 2 μm. The boron concentration of the p type polysilicon layer 16 is preferably equal to that of the first single crystal substrate 11. Next, the p type polysilicon layer 16 is mirror-polished and flattened. Next, after cleaning the first single crystal substrate 11 and the second single crystal substrate 13 respectively, the second single crystal substrate 13 is placed on the first single crystal substrate 11 so that the p type polysilicon layer 16 is in close contact with the oxide film 12. And put them together (Fig. 3
(E)). Next, a thin film separation heat treatment similar to that of the first embodiment is performed while the first single crystal substrate 11 is kept in close contact with the second single crystal substrate 13. As a result, the first single crystal substrate 11 is broken at the ion implantation region 11a and separated into an upper thick portion 11c and a lower thin semiconductor layer 11b (FIG. 3F). Next, the temperature is lowered to remove the thick portion 11c (FIG. 3 (g)), and the second single crystal substrate 13 on which the p - type polysilicon layer 16, the oxide film 12, and the semiconductor layer 11b are sequentially laminated is removed. The semiconductor layer 11b and the second single-crystal substrate 13 are subjected to a heat treatment in the same manner as in the first embodiment to form the oxide film 12 and the p - type polysilicon layer 16
(FIG. 3 (h)). Finally, the separation surface of the semiconductor layer 11b and the separation surface of the thick portion 11c are respectively polished and smoothed (FIG. 3 (i) and FIG.
(J)). As a result, the p - type polysilicon layer 1
6. An SOI substrate including a second single crystal substrate 13 in which an oxide film 12 and a semiconductor layer 11b are sequentially stacked is obtained (FIG. 3).
(I)).

【0010】[0010]

【実施例】次に本発明の具体的態様を示すために、本発
明の実施例を比較例とともに説明する。 <実施例1>図1(a)に示すように、p型単結晶シリ
コン基板11の表面に熱酸化により厚さ400nmの酸
化膜12を形成した。次いで単結晶シリコン基板11に
70keVの電圧を印加して水素イオンを7×1016
cm2のドーズ量でイオン注入して単結晶基板11内部
にイオン注入領域11aを形成した(図1(b))。次
いで単結晶基板11と同一表面積を有する支持基板とな
るp型の第2単結晶シリコン基板13を用意し、この第
2単結晶基板13の表面にCVD法により厚さ1μmの
+型又はp++型のポリシリコン層14を形成した(図
1(c))。次いでこのp+型又はp++型のポリシリコ
ン層14上に厚さ1μmのp-型のポリシリコン層16
を形成した(図1(d))。次いで、p-型のポリシリ
コン層16を鏡面研磨し平坦化した。次いで第1単結晶
基板11と第2単結晶基板13をSC1洗浄液でそれぞ
れ洗浄した後、酸化膜12にp-型のポリシリコン層1
6が密着するように第1単結晶基板11に第2単結晶基
板13を重ね合わせて密着さた(図1(e))。次いで
第1単結晶基板11を第2単結晶基板13に密着させた
まま窒素雰囲気中で600℃の温度で30分間熱処理を
行った。その結果、第1単結晶基板11がイオン注入領
域11aのところで割れて上部の厚肉部11cと下部の
薄い半導体層11bに分離した(図1(f))。次に温
度を下げて厚肉部11cを取除き(図1(g))、表面
にp+型又はp++型のポリシリコン層14、p-型のポリ
シリコン層16、酸化膜12及び半導体層11bが順次
積層された第2単結晶基板13を窒素雰囲気中において
1100℃で2時間熱処理した(図1(h))。最後に
半導体層11bの分離面を研磨して平滑化して実施例1
のSOI基板を製造した(図1(i))。
EXAMPLES Next, examples of the present invention will be described together with comparative examples in order to show specific embodiments of the present invention. <Example 1> As shown in FIG. 1A, an oxide film 12 having a thickness of 400 nm was formed on the surface of a p-type single crystal silicon substrate 11 by thermal oxidation. Next, a voltage of 70 keV was applied to the single crystal silicon substrate 11 to convert hydrogen ions into 7 × 10 16 /
Ion implantation was performed at a dose of cm 2 to form an ion implantation region 11a inside the single crystal substrate 11 (FIG. 1B). Next, a p-type second single-crystal silicon substrate 13 serving as a support substrate having the same surface area as the single-crystal substrate 11 is prepared, and a 1 μm-thick p + -type or p-type A ++ type polysilicon layer 14 was formed (FIG. 1C). Next, a 1 μm thick p type polysilicon layer 16 is formed on the p + type or p ++ type polysilicon layer 14.
Was formed (FIG. 1D). Next, the p - type polysilicon layer 16 was mirror-polished and flattened. Next, after cleaning the first single crystal substrate 11 and the second single crystal substrate 13 with the SC1 cleaning liquid, the p type polysilicon layer 1 is formed on the oxide film 12.
The second single crystal substrate 13 was superimposed on the first single crystal substrate 11 so that the substrates 6 were in close contact with each other (FIG. 1E). Next, a heat treatment was performed at a temperature of 600 ° C. for 30 minutes in a nitrogen atmosphere while keeping the first single crystal substrate 11 in close contact with the second single crystal substrate 13. As a result, the first single crystal substrate 11 was broken at the ion-implanted region 11a and separated into an upper thick portion 11c and a lower thin semiconductor layer 11b (FIG. 1 (f)). Next, the temperature is lowered to remove the thick portion 11c (FIG. 1 (g)), and the p + type or p ++ type polysilicon layer 14, the p type polysilicon layer 16, the oxide film 12, and the The second single crystal substrate 13 on which the semiconductor layers 11b were sequentially laminated was heat-treated at 1100 ° C. for 2 hours in a nitrogen atmosphere (FIG. 1 (h)). Finally, the separation surface of the semiconductor layer 11b was polished and smoothed to obtain a first embodiment.
Was manufactured (FIG. 1 (i)).

【0011】<実施例2>図2(a)〜図2(b)に示
すように、実施例1と同じ工程を繰返して、表面に厚さ
400nmの酸化膜12を有するp型の第1単結晶シリ
コン基板11の内部にイオン注入領域11aを形成し
た。次いで第1単結晶基板11と同一表面積を有し、支
持基板となるp型の第2単結晶シリコン基板13を用意
し、このp型の第2単結晶基板13の表面からリンをイ
オン注入して第2単結晶基板13内部にリン注入層13
aを形成した(図2(c))。次に第1基板11と第2
基板13の貼合わせ接合強度を高めるために、リン注入
後、第2基板13の表面を研磨した。次いで第1単結晶
基板11と第2単結晶基板13をSC1洗浄液でそれぞ
れ洗浄した後、第1単結晶基板11に酸化膜12を介し
て第2単結晶基板13を重ね合わせて密着させた(図2
(d))。次いで第1単結晶基板11を第2単結晶シリ
コン基板13に密着させたまま窒素雰囲気中で600℃
の温度で30分間熱処理を行った。その結果、第1単結
晶基板11がイオン注入領域11aのところで割れて上
部の厚肉部11cと下部の薄い半導体層11bに分離し
た(図2(e))。次に温度を下げて厚肉部11cを取
除き(図2(f))、表面に酸化膜12及び半導体層1
1bが順次積層された第2単結晶シリコン基板13を窒
素雰囲気中において1100℃で2時間熱処理した(図
2(g))。最後に半導体層11bの分離面を研磨して
平滑化して実施例2のSOI基板を製造した(図2
(h))。
<Embodiment 2> As shown in FIGS. 2A and 2B, the same steps as those of Embodiment 1 are repeated to form a p-type first film having an oxide film 12 with a thickness of 400 nm on its surface. An ion implanted region 11a was formed inside the single crystal silicon substrate 11. Next, a p-type second single-crystal silicon substrate 13 having the same surface area as the first single-crystal substrate 11 and serving as a support substrate is prepared, and phosphorus is ion-implanted from the surface of the p-type second single-crystal substrate 13. The phosphorus injection layer 13 inside the second single crystal substrate 13
a was formed (FIG. 2C). Next, the first substrate 11 and the second
After phosphorus was injected, the surface of the second substrate 13 was polished to increase the bonding strength of the substrate 13. Next, after cleaning the first single crystal substrate 11 and the second single crystal substrate 13 with the SC1 cleaning liquid, the second single crystal substrate 13 is overlapped on the first single crystal substrate 11 with the oxide film 12 therebetween and adhered thereto ( FIG.
(D)). Then, the first single crystal substrate 11 is kept in contact with the second single crystal silicon substrate 13 at 600 ° C. in a nitrogen atmosphere.
At 30 ° C. for 30 minutes. As a result, the first single crystal substrate 11 was broken at the ion-implanted region 11a and separated into an upper thick portion 11c and a lower thin semiconductor layer 11b (FIG. 2E). Next, the temperature is lowered to remove the thick portion 11c (FIG. 2 (f)), and the oxide film 12 and the semiconductor layer 1 are formed on the surface.
The second single-crystal silicon substrate 13 on which 1b was sequentially laminated was heat-treated at 1100 ° C. for 2 hours in a nitrogen atmosphere (FIG. 2G). Finally, the separation surface of the semiconductor layer 11b was polished and smoothed to manufacture the SOI substrate of Example 2 (FIG. 2).
(H)).

【0012】<実施例3>図3(a)〜図3(b)に示
すように、実施例1と同じ工程を繰返して、表面に厚さ
400nmの酸化膜12を有するp型の第1単結晶シリ
コン基板11の内部にイオン注入領域11aを形成し
た。次いで第1単結晶シリコン基板11と同一表面積を
有し、支持基板となるp型の第2単結晶シリコン基板1
3を用意し、このp型の第2単結晶基板13の表面から
リンをイオン注入して第2単結晶基板13内部にリン注
入層13aを形成した(図3(c))。次いでリン注入
層13aを形成した第2単結晶基板13の表面に厚さ1
μmのp-型のポリシリコン層16を形成した(図3
(d))。次いで、p−型のポリシリコン層16を鏡面
研磨し平坦化した。次いで第1単結晶基板11と第2単
結晶基板13をSC1洗浄液でそれぞれ洗浄した後、酸
化膜12にp-型のポリシリコン層16が密着するよう
に第1単結晶基板11に第2単結晶シリコン基板13を
重ね合わせて密着させた(図3(e))。次いで第1単
結晶基板11を第2単結晶基板13に密着させたまま窒
素雰囲気中で600℃の温度で30分間熱処理を行っ
た。その結果、第1単結晶基板11がイオン注入領域1
1aのところで割れて上部の厚肉部11cと下部の薄い
半導体層11bに分離した(図3(f))。次に温度を
下げて厚肉部11cを取除き(図3(g))、表面にp
-型のポリシリコン層16、酸化膜12及び半導体層1
1bが順次積層された第2単結晶基板13を窒素雰囲気
中において1100℃で2時間熱処理した(図3
(h))。最後に半導体層11bの分離面を研磨して平
滑化して実施例3のSOI基板を製造した(図3
(i))。
<Embodiment 3> As shown in FIGS. 3A and 3B, the same steps as those of Embodiment 1 are repeated to form a p-type first film having a 400 nm-thickness oxide film 12 on its surface. An ion implanted region 11a was formed inside the single crystal silicon substrate 11. Next, a p-type second single-crystal silicon substrate 1 having the same surface area as the first single-crystal silicon substrate 11 and serving as a support substrate
3 was prepared, and phosphorus was ion-implanted from the surface of the p-type second single-crystal substrate 13 to form a phosphorus-implanted layer 13a inside the second single-crystal substrate 13 (FIG. 3C). Next, a thickness of 1 is formed on the surface of the second single crystal substrate 13 on which the phosphorus implantation layer 13a is formed.
A p - type polysilicon layer 16 of μm was formed (FIG. 3).
(D)). Next, the p − type polysilicon layer 16 was mirror-polished and flattened. Next, the first single-crystal substrate 11 and the second single-crystal substrate 13 are each washed with the SC1 cleaning liquid, and then the second single-crystal substrate 11 is attached to the first single-crystal substrate 11 such that the p type polysilicon layer 16 is in close contact with the oxide film 12. The crystalline silicon substrate 13 was overlapped and adhered (FIG. 3E). Next, a heat treatment was performed at a temperature of 600 ° C. for 30 minutes in a nitrogen atmosphere while keeping the first single crystal substrate 11 in close contact with the second single crystal substrate 13. As a result, the first single crystal substrate 11 is
It was split at 1a and separated into an upper thick portion 11c and a lower thin semiconductor layer 11b (FIG. 3 (f)). Next, the temperature was lowered to remove the thick portion 11c (FIG. 3 (g)), and p
- type polysilicon layer 16, oxide film 12 and the semiconductor layer 1
The second single crystal substrate 13 on which 1b was sequentially laminated was heat-treated at 1100 ° C. for 2 hours in a nitrogen atmosphere (FIG. 3).
(H)). Finally, the separation surface of the semiconductor layer 11b was polished and smoothed to manufacture the SOI substrate of Example 3 (FIG. 3).
(I)).

【0013】<比較例1>支持基板となるp型の第2単
結晶シリコン基板13の表面にp+型又はp++型のポリ
シリコン層14及びp-型のポリシリコン層16を形成
しなかったことを除いては実質的に実施例1の方法を繰
返して比較例1のSOI基板を製造した。
Comparative Example 1 A p + -type or p ++ -type polysilicon layer 14 and a p -- type polysilicon layer 16 are formed on the surface of a p-type second single-crystal silicon substrate 13 serving as a support substrate. An SOI substrate of Comparative Example 1 was manufactured by substantially repeating the method of Example 1 except that no SOI substrate was provided.

【0014】<比較評価>実施例1、実施例2、実施例
3及び比較例1のそれぞれのSOI基板において、10
00ppmの銅標準液を用いてスピンコート法によりそ
の基板表面を強制的に汚染し、窒素雰囲気中で900
℃、1時間の熱処理を行った後、半導体層11bにおけ
る銅濃度(atoms/cm3)を原子吸光法により調べた。
その結果を図4に示す。
<Comparative Evaluation> In each of the SOI substrates of Example 1, Example 2, Example 3, and Comparative Example 1, 10
The substrate surface was forcibly contaminated by a spin coating method using a copper standard solution of 00 ppm, and 900 ppm in a nitrogen atmosphere.
After heat treatment at 1 ° C. for 1 hour, the copper concentration (atoms / cm 3 ) in the semiconductor layer 11b was examined by an atomic absorption method.
FIG. 4 shows the results.

【0015】図4から明らかなように実施例1〜3のS
OI層中の銅濃度(atoms/cm3)は比較例1に比べ低
い。これは実施例1〜3のSOI基板が大きなゲッタリ
ング能力を有するため、比較例1のSOI基板に比べ半
導体層11bが重金属不純物で汚染され難いことを示し
ている。
As is apparent from FIG.
The copper concentration (atoms / cm 3 ) in the OI layer is lower than that in Comparative Example 1. This indicates that the semiconductor layers 11b are less likely to be contaminated with heavy metal impurities than the SOI substrates of Comparative Example 1 because the SOI substrates of Examples 1 to 3 have a large gettering ability.

【0016】[0016]

【発明の効果】以上述べたように、本発明によれば、半
導体層が酸化膜を介して半導体基板上に重ね合わされて
いるSOI基板において、半導体基板となるp型の単結
晶シリコン基板の片面にp+型又はp++型のポリシリコ
ン層を形成し、このポリシリコン層上にp-型のポリシ
リコン層を形成するか、又は支持基板となるp型の単結
晶シリコン基板の表面からリンをイオン注入して基板内
部にリン注入層を形成するか、又は上記リン注入層が形
成された支持基板の表面にp-型のポリシリコン層を形
成するようにしたから、上記半導体層がデバイスプロセ
ス中に重金属不純物により汚染されても、上記p-及び
+型又はp++型のポリシリコン層又は上記リン注入層
がゲッタリング層として作用して上記半導体層中の重金
属不純物を捕捉し、その結果、熱処理が進行しても上記
シリコン層が重金属不純物で汚染されず、SOI基板の
品質劣化を防止できる。
As described above, according to the present invention, in an SOI substrate in which a semiconductor layer is overlaid on a semiconductor substrate via an oxide film, one side of a p-type single crystal silicon substrate serving as a semiconductor substrate is provided. A p + -type or p ++ -type polysilicon layer, and a p -- type polysilicon layer is formed on the polysilicon layer, or from the surface of a p-type single-crystal silicon substrate serving as a support substrate. Since a phosphorus-implanted layer is formed inside the substrate by ion-implanting phosphorus or a p - type polysilicon layer is formed on the surface of the support substrate on which the phosphorus-implanted layer is formed, the semiconductor layer is be contaminated by heavy metal impurities during the device process, the p - capture and p + -type or p ++ type of heavy metal impurities in the semiconductor layer acts polysilicon layer or the phosphorus injection layer as a gettering layer And then As a result, even if the heat treatment proceeds, the silicon layer is not contaminated with heavy metal impurities, and deterioration of the quality of the SOI substrate can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態の第1のSOI基板の製造方
法を工程順に示す図。
FIG. 1 is a view showing a method for manufacturing a first SOI substrate according to an embodiment of the present invention in the order of steps;

【図2】本発明の実施形態の第2のSOI基板の製造方
法を工程順に示す図。
FIG. 2 is a diagram showing a method for manufacturing a second SOI substrate according to the embodiment of the present invention in the order of steps.

【図3】本発明の実施形態の第3のSOI基板の製造方
法を工程順に示す図。
FIG. 3 is a diagram showing a method for manufacturing a third SOI substrate according to the embodiment of the present invention in the order of steps.

【図4】実施例1〜3及び比較例1のSOI基板におい
て、半導体層11b中の銅濃度を示す図。
FIG. 4 is a view showing the copper concentration in a semiconductor layer 11b in the SOI substrates of Examples 1 to 3 and Comparative Example 1.

【符号の説明】[Explanation of symbols]

11 p型第1シリコン基板 11a イオン注入領域 11b シリコン層 11c 厚肉部 12 酸化膜 13 p型第2シリコン基板 13a リン注入層 14 p+型又はp++型のポリシリコン層 16 p-型のポリシリコン層Reference Signs List 11 p-type first silicon substrate 11 a ion-implanted region 11 b silicon layer 11 c thick portion 12 oxide film 13 p-type second silicon substrate 13 a phosphorus-implanted layer 14 p + -type or p ++ -type polysilicon layer 16 p -- type Polysilicon layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 p型の第1シリコン基板(11)の表面に酸
化膜(12)を形成する工程と、 前記第1シリコン基板(11)の表面から水素イオンを注入
して前記第1シリコン基板(11)内部に水素イオン注入領
域(11a)を形成する工程と、 支持基板となるp型の第2シリコン基板(13)の片面にp
+型又はp++型のポリシリコン層(14)を形成する工程
と、 前記第2シリコン基板(13)のp+型又はp++型のポリシ
リコン層(14)上にp-型のポリシリコン層(16)を形成す
る工程と、 前記p-型のポリシリコン層(16)鏡面研磨する工程と、 前記酸化膜(12)に鏡面研磨した前記p-型のポリシリコ
ン層(16)が密着するように前記第1シリコン基板(11)に
前記第2シリコン基板(13)を重ね合わせて密着させる工
程と、 前記第1シリコン基板(11)を第2シリコン基板(13)に密
着させたまま所定の温度で熱処理して前記第1シリコン
基板(11)を前記水素イオン注入領域(11a)で前記第2シ
リコン基板(13)から分離して前記第2シリコン基板(13)
の表面にシリコン層(11b)を形成する工程と、 表面にシリコン層(11b)を有する前記第2シリコン基板
(13)を更に熱処理する工程とを含むSOI基板の製造方
法。
Forming an oxide film on a surface of a p-type first silicon substrate; implanting hydrogen ions from a surface of the first silicon substrate to form the first silicon substrate; Forming a hydrogen ion implanted region (11a) inside the substrate (11), forming a p-type second silicon substrate (13) serving as a support substrate on one side of the substrate;
Of + type or p ++ type forming polysilicon layer (14), p on the p + -type or p ++ type polysilicon layer (14) of the second silicon substrate (13) - of the type forming a polysilicon layer (16), wherein the p - type polysilicon layer (16) wherein p is mirror polished to a step of mirror polishing, the oxide film (12) - type polysilicon layer (16) Superimposing the second silicon substrate (13) on the first silicon substrate (11) so that the first silicon substrate (11) is in close contact with the first silicon substrate (11); and bringing the first silicon substrate (11) into close contact with the second silicon substrate (13). The first silicon substrate (11) is separated from the second silicon substrate (13) in the hydrogen ion implantation region (11a) by performing a heat treatment at a predetermined temperature while keeping the second silicon substrate (13).
Forming a silicon layer (11b) on the surface of the second silicon substrate, the second silicon substrate having a silicon layer (11b) on the surface
(13) a method of manufacturing an SOI substrate, further comprising a step of performing a heat treatment.
【請求項2】 p型の第1シリコン基板(11)の表面に酸
化膜(12)を形成する工程と、 前記第1シリコン基板(11)の表面から水素イオンを注入
して前記第1シリコン基板(11)内部に水素イオン注入領
域(11a)を形成する工程と、 支持基板となるp型の第2シリコン基板(13)の表面から
リンをイオン注入して前記第2シリコン基板(13)内部に
リン注入層(13a)を形成する工程と、 前記酸化膜(12)に前記リンをイオン注入した表面が密着
するように前記第1シリコン基板(11)に前記第2シリコ
ン基板(13)を重ね合わせて密着させる工程と、 前記第1シリコン基板(11)を第2シリコン基板(13)に密
着させたまま所定の温度で熱処理して前記第1シリコン
基板(11)を前記水素イオン注入領域(11a)で前記第2シ
リコン基板(13)から分離して前記第2シリコン基板(13)
の表面にシリコン層(11b)を形成する工程と、 表面にシリコン層(11b)を有する前記第2シリコン基板
(13)を更に熱処理する工程とを含むSOI基板の製造方
法。
2. A step of forming an oxide film (12) on a surface of a p-type first silicon substrate (11); and implanting hydrogen ions from the surface of the first silicon substrate (11) to form the first silicon substrate. Forming a hydrogen ion-implanted region (11a) inside the substrate (11); and ion-implanting phosphorus from the surface of a p-type second silicon substrate (13) serving as a support substrate to form the second silicon substrate (13). A step of forming a phosphorus implantation layer (13a) therein; and a step of forming the second silicon substrate (13) on the first silicon substrate (11) such that a surface of the oxide film (12) into which the phosphorus is ion-implanted adheres. Superimposing the first silicon substrate (11) on the second silicon substrate (13) and performing a heat treatment at a predetermined temperature while keeping the first silicon substrate (11) in close contact with the second silicon substrate (13). In the region (11a), the second silicon substrate (13) is separated from the second silicon substrate (13).
Forming a silicon layer (11b) on the surface of the second silicon substrate, the second silicon substrate having a silicon layer (11b) on the surface
(13) a method of manufacturing an SOI substrate, further comprising a step of performing a heat treatment.
【請求項3】 p型の第1シリコン基板(11)の表面に酸
化膜(12)を形成する工程と、 前記第1シリコン基板(11)の表面から水素イオンを注入
して前記第1シリコン基板(11)内部に水素イオン注入領
域(11a)を形成する工程と、 支持基板となるp型の第2シリコン基板(13)の表面から
リンをイオン注入して前記第2シリコン基板(13)内部に
リン注入層(13a)を形成する工程と、 前記リン注入層(13a)を形成した第2シリコン基板(13)
の表面にp-型のポリシリコン層(16)を形成する工程
と、 前記p-型のポリシリコン層(16)鏡面研磨する工程と、 前記酸化膜(12)に鏡面研磨した前記p-型のポリシリコ
ン層(16)が密着するように前記第1シリコン基板(11)に
前記第2シリコン基板(13)を重ね合わせて密着させる工
程と、 前記第1シリコン基板(11)を第2シリコン基板(13)に密
着させたまま所定の温度で熱処理して前記第1シリコン
基板(11)を前記水素イオン注入領域(11a)で前記第2シ
リコン基板(13)から分離して前記第2シリコン基板(13)
の表面にシリコン層(11b)を形成する工程と、 表面にシリコン層(11b)を有する前記第2シリコン基板
(13)を更に熱処理する工程とを含むSOI基板の製造方
法。
3. A step of forming an oxide film (12) on the surface of a p-type first silicon substrate (11); and implanting hydrogen ions from the surface of the first silicon substrate (11) to form the first silicon substrate. Forming a hydrogen ion-implanted region (11a) inside the substrate (11); and ion-implanting phosphorus from the surface of a p-type second silicon substrate (13) serving as a support substrate to form the second silicon substrate (13). Forming a phosphorus injection layer (13a) therein; and a second silicon substrate (13) having the phosphorus injection layer (13a) formed thereon
Type - forming type polysilicon layer (16), the p - - p on the surface of the p type and steps of the polysilicon layer (16) mirror-polishing, which were mirror-polished to said oxide film (12) Superposing the second silicon substrate (13) on the first silicon substrate (11) so that the polysilicon layer (16) is in close contact with the first silicon substrate (11); The first silicon substrate (11) is separated from the second silicon substrate (13) in the hydrogen ion implanted region (11a) by heat treatment at a predetermined temperature while being kept in close contact with the substrate (13). Board (13)
Forming a silicon layer (11b) on the surface of the second silicon substrate, the second silicon substrate having a silicon layer (11b) on the surface
(13) a method of manufacturing an SOI substrate, further comprising a step of performing a heat treatment.
JP11159698A 1998-04-22 1998-04-22 Method for manufacturing SOI substrate Expired - Fee Related JP3452123B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11159698A JP3452123B2 (en) 1998-04-22 1998-04-22 Method for manufacturing SOI substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11159698A JP3452123B2 (en) 1998-04-22 1998-04-22 Method for manufacturing SOI substrate

Publications (2)

Publication Number Publication Date
JPH11307471A true JPH11307471A (en) 1999-11-05
JP3452123B2 JP3452123B2 (en) 2003-09-29

Family

ID=14565373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11159698A Expired - Fee Related JP3452123B2 (en) 1998-04-22 1998-04-22 Method for manufacturing SOI substrate

Country Status (1)

Country Link
JP (1) JP3452123B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001048825A1 (en) * 1999-12-24 2001-07-05 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
JP2005064340A (en) * 2003-08-18 2005-03-10 Shin Etsu Handotai Co Ltd Soi wafer and its manufacturing method
WO2005124865A1 (en) * 2004-06-17 2005-12-29 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
KR100571572B1 (en) * 2000-09-06 2006-04-14 주식회사 실트론 Method for manufacturing bonded S.O.wafer with improved ability to remove metal impurities
EP1840951A2 (en) * 2006-03-27 2007-10-03 Okmetic Oyj A gettering method and a wafer using the same
JP2007318102A (en) * 2006-04-24 2007-12-06 Shin Etsu Handotai Co Ltd Method of manufacturing soi wafer
JP2015050429A (en) * 2013-09-04 2015-03-16 信越半導体株式会社 Soi wafer manufacturing method, soi wafer and semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001048825A1 (en) * 1999-12-24 2001-07-05 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
EP1187216A1 (en) * 1999-12-24 2002-03-13 Shin-Etsu Handotai Company, Limited Method for manufacturing bonded wafer
US6566233B2 (en) 1999-12-24 2003-05-20 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
EP1187216A4 (en) * 1999-12-24 2008-09-24 Shinetsu Handotai Kk Method for manufacturing bonded wafer
KR100571572B1 (en) * 2000-09-06 2006-04-14 주식회사 실트론 Method for manufacturing bonded S.O.wafer with improved ability to remove metal impurities
JP2005064340A (en) * 2003-08-18 2005-03-10 Shin Etsu Handotai Co Ltd Soi wafer and its manufacturing method
JP4525892B2 (en) * 2003-08-18 2010-08-18 信越半導体株式会社 Manufacturing method of SOI wafer
WO2005124865A1 (en) * 2004-06-17 2005-12-29 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
EP1840951A2 (en) * 2006-03-27 2007-10-03 Okmetic Oyj A gettering method and a wafer using the same
EP1840951A3 (en) * 2006-03-27 2009-07-08 Okmetic Oyj A gettering method and a wafer using the same
JP2007318102A (en) * 2006-04-24 2007-12-06 Shin Etsu Handotai Co Ltd Method of manufacturing soi wafer
JP2015050429A (en) * 2013-09-04 2015-03-16 信越半導体株式会社 Soi wafer manufacturing method, soi wafer and semiconductor device

Also Published As

Publication number Publication date
JP3452123B2 (en) 2003-09-29

Similar Documents

Publication Publication Date Title
JP5706391B2 (en) Manufacturing method of SOI wafer
US6251754B1 (en) Semiconductor substrate manufacturing method
JP3395661B2 (en) Method for manufacturing SOI wafer
US20010016399A1 (en) Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
KR101340002B1 (en) SOI Wafer Manufacturing Method
JP5183958B2 (en) Manufacturing method of SOI wafer
JPH1187668A (en) Manufacture of soi board
JP2002184960A (en) Manufacturing method of soi wafer and soi wafer
KR101380514B1 (en) Method for manufacturing semiconductor substrate
JP3522482B2 (en) Method for manufacturing SOI substrate
JP3864495B2 (en) Manufacturing method of semiconductor substrate
JP3582566B2 (en) Method for manufacturing SOI substrate
JP3452123B2 (en) Method for manufacturing SOI substrate
JPH0878644A (en) Manufacture of semiconductor integrated circuit device
JPH11191617A (en) Manufacture of soi substrate
JP5292810B2 (en) Manufacturing method of SOI substrate
JP3412449B2 (en) Method for manufacturing SOI substrate
JP3484961B2 (en) Method for manufacturing SOI substrate
JP2006165061A (en) Method of manufacturing soi wafer
JP3452122B2 (en) Method for manufacturing SOI substrate
US7799660B2 (en) Method for manufacturing SOI substrate
JP2000124091A (en) Manufacture of soi wafer and soi wafer
JP3810168B2 (en) Manufacturing method of semiconductor substrate
JPH0472631A (en) Semiconductor substrate and manufacture thereof
JP5096780B2 (en) Manufacturing method of SOI wafer

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080718

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090718

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090718

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100718

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100718

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110718

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110718

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120718

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120718

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130718

Year of fee payment: 10

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees