JP2000124091A - Manufacture of soi wafer and soi wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an SOI(silicon-on-insulator) wafer and the SOI wafer which has high gettering effect and high productivity. SOLUTION: This method of manufacturing an SOI wafer having a gettering site formed on a base wafer comprises forming openings reaching an embedded oxide film on the surface of an SOI layer, etching the exposed embedded oxide film through the openings to form overhang parts of the SOI layer, and heat treating to form SOI layer-substrate coupling regions piercing the embedded oxide film. Further the method comprises forming a pattern of openings on the SOI layer surface, implanting silicon ions through the openings, to partly form silicon-rich regions piercing them in the embedded oxide film, thus forming SOI layer-substrate coupling regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI wafer, and more particularly to an SOI wafer having a very small amount of heavy metal impurities in an SOI layer.
The present invention relates to a wafer manufacturing method and an SOI wafer.

[0002]

2. Description of the Related Art A single crystal silicon layer (S
SOI (Silico) in which an OI layer is formed on a buried oxide film
n on insulator) Since the wafers can be completely separated from each other, characteristics such as withstand voltage and latch-up resistance can be easily improved, and the parasitic capacitance between the elements and the substrate can be reduced, so that device operation can be performed at high speed. It has excellent characteristics such as Therefore, the importance of SOI wafers is expected to increase in the future due to the demand for higher integration and higher speed of today's highly integrated semiconductor devices.

When heavy metal impurities are present in an active SOI layer of an SOI wafer used for such a highly integrated semiconductor device, the characteristics of the semiconductor device may be deteriorated. In particular, it is considered that the cleanness required for the most advanced devices has a heavy metal impurity concentration of 1 × 10 ⁹ atoms / cm ² or less, and the heavy metal impurities present in the SOI layer must be reduced as much as possible. As one of the techniques for reducing such heavy metal impurities, the importance of the gettering technique is increasing more and more.

[0004] Gettering is a technique in which a gettering site such as a crystal defect is formed in a region other than an element forming region, and heavy metal impurities are captured and fixed in the site. Various proposals have been made in the past to apply this gettering technique to SOI wafers.

First, a method of forming a gettering site on a buried oxide film below an SOI layer has been considered. That is, a polycrystalline silicon (polysilicon) layer serving as a gettering site is formed between the SOI layer and the buried oxide film to try to getter heavy metal impurities in the SOI layer (Japanese Patent No. 2,535,596; Kaihei 6-2
No. 75525).

However, in this method, since the gettering site is located in the vicinity of the SOI layer which is a device active layer, there is a risk that impurities once gettered are re-emitted to the SOI layer by heat treatment such as a device process. There is. In particular, in the case of a wafer having a thin SOI layer, the risk is high, which is a problem.

Therefore, a method of forming a gettering site on the support substrate side below the buried oxide film, not between the SOI layer and the buried oxide film, has been considered. That is, a gettering layer is formed between the buried oxide film and the support substrate, or on the back surface of the support substrate, or an IG is formed on the support substrate.
(Intrinsic gettering) This is a method in which oxygen precipitate nuclei and oxygen precipitates serving as gettering sites are deposited by applying a heat treatment (JP-A-8-116038, JP-A-9-3).
26396).

However, in order to getter the heavy metal impurities taken in the SOI layer, it is necessary to pass through the buried oxide film. According to recent research, heavy metals such as Ni hardly diffuse in the oxide film. Turned out, you can not get through. Moreover, gettering, in which a gettering site is provided on the supporting substrate side, has become more difficult as the temperature of the device process has been lowered in recent years.

Therefore, in order to form a gettering site on the support substrate side and getter impurities in the SOI layer, a through hole is provided in the buried oxide film to form a connection region between the SOI layer and the support substrate. (See JP-A-5-129309 and JP-A-6-216136). According to such a method, it is possible to effectively getter heavy metal impurities in the SOI layer from the gettering site on the supporting substrate side.

[0010]

Conventionally, such SO
The SOI wafer in which the connection region between the I layer and the support substrate is formed has been manufactured by, for example, the following method. That is, as shown in FIG. 3, first, a base wafer 1 serving as a support substrate and a bond wafer 2 serving as an SOI layer are prepared (FIG. 3A). A polysilicon layer 4 serving as a gettering site is deposited on the surface of a base wafer 1 serving as a supporting substrate (FIG. 3B). Next, S is applied to the surface of the base wafer 1.
An i ₃ N ₄ film 11 is formed (FIG. 3 (3)), and is selectively etched and removed by photolithography to use it as a selective oxidation mask (FIG. 3 (4)). Next, Si
_{Using the 3} N ₄ film 11 as a mask, an oxide film 3 to be a buried oxide film is formed on the surface of the base wafer 1 (FIG. 3).
(5)). Then, the Si ₃ N ₄ film 11 of the mask is removed (FIG. 3 (6)). Next, the base wafer 1 is flattened by mechanical polishing (FIG. 3 (7)). Then, the bond wafer 2 serving as the SOI layer is bonded (FIG. 3 (8)). Finally, the bond wafer 2 is thinned by a grinding / polishing process, a hydrogen ion implantation peeling method, etc.
The SOI wafer 6 having the I layer 12 is completed (FIG. 3
(9)).

However, SO manufactured by such a method is
The I wafer had a problem. That is, in the above method, since the surface on which both the oxide film (SiO ₂ ) and silicon are exposed is flattened by polishing, a step due to the difference in the polishing rate between the two is likely to occur at the boundary. However, bonding to the bond wafer in a state where the step is generated causes voids and lowers the bonding strength. Therefore, the productivity of the SOI wafer by this manufacturing method is low,
A more appropriate manufacturing method has been desired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its main object to provide a method of manufacturing an SOI wafer having a high gettering effect and having a small amount of heavy metal impurities in an SOI layer and having high productivity, and an SOI wafer. And

[0013]

In order to solve the above-mentioned problems, the invention described in claim 1 of the present invention provides a base wafer which is a substrate on which a gettering site is formed, and an SOI.
The bond wafer to be a layer is bonded via an oxide film to be a buried oxide film, and the bond wafer is formed into a thin film to form S
In the method for manufacturing an SOI wafer having an OI layer, an opening reaching the buried oxide film is formed on the surface of the SOI layer, and the buried oxide film exposed at the opening is etched to form an overhang portion of the SOI layer. A method for manufacturing an SOI wafer, characterized by forming a connection region between an SOI layer penetrating a buried oxide film and a substrate by performing heat treatment later.

As described above, in the method of manufacturing an SOI wafer in which a gettering site is formed on a base wafer, an opening reaching the buried oxide film is formed on the surface of the SOI layer, and the buried oxide film exposed on the opening is etched. After forming an overhang portion of the SOI layer by performing heat treatment, the SOI layer penetrating the buried oxide film is formed.
If a connection region between the layer and the substrate is formed, heavy metal impurities in the SOI layer can be effectively gettered from this connection region, and once gettering is performed by heat treatment such as a device process later. No impurities are re-emitted. Further, according to this method, voids are generated between the base wafer and the bond wafer,
Since the bonding strength between the two wafers does not decrease, the productivity does not decrease.

In this case, it is preferable that the heat treatment is performed in a reducing atmosphere containing hydrogen by using a rapid heating / cooling device. As described above, if the heat treatment is performed in a reducing atmosphere containing hydrogen using a rapid heating / cooling device, reflow of silicon is likely to occur, so that the overhang portion easily adheres to the base wafer side. Further, since the heat treatment time can be shortened, there is no problem that hydrogen in the atmosphere enters from a crystal defect in the SOI layer and the buried oxide film is etched. Here, the rapid heating / rapid cooling refers to a method of immediately performing a heat treatment using a lamp heater or the like, a method of immediately putting a wafer into a heat treatment furnace, and immediately removing the wafer, such as a method of moving a wafer into and out of a heat treatment furnace. This is a method of heating in a very short time.

According to a third aspect of the present invention, a base wafer serving as a substrate on which a gettering site is formed and a bond wafer serving as an SOI layer are bonded via an oxide film serving as a buried oxide film. Then, in the method for manufacturing an SOI wafer in which the bond wafer is thinned to form an SOI layer, a pattern having an opening in the surface of the SOI layer is formed, and silicon is ion-implanted from the opening,
A method for manufacturing an SOI wafer, characterized in that a silicon-rich region penetrating the buried oxide film is partially formed in the buried oxide film to form a connection region between the SOI layer and the substrate.

As described above, in the method for manufacturing an SOI wafer in which a gettering site is formed on a base wafer, a pattern having an opening is formed on the surface of the SOI layer.
If silicon is ion-implanted from the opening and a silicon-rich region penetrating the buried oxide film is partially formed in the buried oxide film to form a connecting region between the SOI layer and the substrate, The heavy metal impurities in the SOI layer can be effectively gettered, and the impurities once gettered are not re-emitted by a heat treatment such as a device process later. Furthermore, according to this method, no void is generated between the base wafer and the bond wafer, and the bonding strength between the two wafers is not reduced, so that the productivity is not reduced.

In this case, the gettering site can be formed by subjecting the base wafer to IG heat treatment to precipitate oxygen precipitation nuclei or oxygen precipitates. If the gettering site is formed by depositing oxygen precipitation nuclei or oxygen precipitates by performing IG (Intrinsic gettering) heat treatment on the base wafer, the gettering process itself does not introduce new impurities, and the It has the advantage that heat treatment can be performed in a clean room.

In this case, the gettering site can be formed by depositing a polysilicon layer on at least one surface of the base wafer. If the gettering site is formed by depositing a polysilicon layer on at least one surface of the base wafer as described above, the gettering effect is maintained even if heat treatment such as a device process is performed a plurality of times, and the polysilicon is further formed. Since the silicon layer promotes oxygen precipitation, the IG effect can also be enhanced.

Further, in this case, the gettering site can be formed by providing a damage layer on at least one surface of the base wafer. If the gettering site is formed by providing the damaged layer on at least one surface of the base wafer in this manner, the step of forming the gettering site becomes simple, and the SOI wafer can be manufactured at low cost.

Further, as described in claim 7, it is preferable that a connection region between the SOI layer penetrating the buried oxide film and the substrate is formed so as to coincide with a scribe line. If the connection region is formed so as to correspond to the scribe line at the time of device fabrication, a complete SOI structure can be obtained by separating each chip after device fabrication.

Further, the SOI wafer manufactured by the manufacturing method of the present invention (claim 8) may be, for example, a semiconductor device having a gettering site formed as described in claim 9 of the present invention and an SOI layer. Consisting of a buried oxide film of
An SOI wafer having a connection region between an SOI layer penetrating the buried oxide film and a substrate, wherein the connection region is formed of S
An opening reaching the buried oxide film is formed on the surface of the OI layer, the buried oxide film exposed at the opening is etched to form an overhang portion of the SOI layer, and then heat-treated. An SOI wafer characterized in that: Further, in this case, claim 1
0, the heat treatment may be performed in a reducing atmosphere containing hydrogen using a rapid heating / cooling device.

Alternatively, as described in claim 11 of the present invention, the substrate comprises a gettering site-formed substrate, an SOI layer, and a buried oxide film between the two, and the SOI layer penetrating the buried oxide film, SO having a connection region of
An SOI wafer, wherein the connection region is formed by ion-implanting silicon from the surface of the SOI layer and partially providing a silicon-rich region penetrating the buried oxide film. It is a wafer.

In the case of such an SOI wafer, the SOI wafer on which the device is formed has a high gettering ability.
An SOI wafer having very few heavy metal impurities in the layer and having high bonding strength between the SOI layer and the supporting substrate is obtained.

In this case, the gettering site can be formed by depositing oxygen precipitate nuclei or oxygen precipitates by subjecting the base wafer to IG heat treatment as described in claim 12. Item 15 may be formed by depositing a polysilicon layer on at least one surface of the base wafer as described in Item 13, and as described in Item 14 on at least one surface of the base wafer. It can be formed by providing a damaged layer.

Further, as described in claim 15 and claim 16, the connecting region may be formed so as to coincide with the scribe line. Such S
In the case of an OI wafer, a complete SOI structure can be obtained by separating each chip after device fabrication.

Hereinafter, the present invention will be described in more detail.
The present invention is not limited to these. The present invention
In order to obtain a high gettering ability, a gettering site is formed on the side of the base wafer serving as a support substrate, and when manufacturing an SOI wafer in which a connection region between the SOI layer penetrating the buried oxide film and the substrate is formed, the base wafer is manufactured. It has been found that an SOI substrate having high gettering ability and high productivity can be obtained by a method of forming a connection region between an SOI layer and a substrate after bonding the SOI layer and the bond wafer, and specific conditions. It was completed after careful examination.

That is, a conventional SOI having a connection region
The disadvantage of the wafer manufacturing method is that before bonding the base wafer serving as the substrate and the bond wafer serving as the SOI layer,
The object is to form a portion serving as a connection region in the buried oxide film. In such a method, the buried oxide film SiO
₂ and the Si in the connection region have different polishing rates and the like, so it was difficult to obtain a completely flat surface even by polishing, for example. Therefore, when this surface is used as a bonding surface to bond the base wafer and the bond wafer, voids are generated or the bonding strength is reduced, resulting in a reduction in wafer productivity.

Therefore, the present inventor has conceived of forming a connection region between the SOI layer and the substrate after bonding the base wafer and the bond wafer. In this way, the bonding itself between the base wafer and the bond wafer is not affected at all, and therefore, there is no reduction in the productivity or quality of the wafer due to the defective bonding of the wafer. Therefore, the present inventor has developed the present invention by diligently studying a specific method for forming a connection region between the SOI layer and the substrate after bonding the base wafer and the bond wafer.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flow chart showing an example of the manufacturing method of the present invention. An opening reaching the buried oxide film is formed on the surface of the SOI layer, and the buried oxide film exposed in the opening is etched to form an overlying SOI layer. This shows a method of forming a connection region between an SOI layer penetrating a buried oxide film and a substrate by performing a heat treatment after a hang portion is formed.

First, a base wafer 1 and a bond wafer 2 are prepared (FIG. 1 (1)). On the surface of the bond wafer 2, a thermal oxide film 3 to be a buried oxide film later is formed (FIG. 1 (2)), and then hydrogen ions are implanted into the bond wafer from above the oxide film to form a microbubble layer (encapsulation). A layer 5 is formed (FIG. 1C). On the other hand, a polysilicon layer 4 serving as a gettering site is deposited on the surface of the base wafer 1 (FIG. 1 (4)). Then, the ion-implanted surface of the bond wafer 2 is brought into close contact with the base wafer 1 on which the polysilicon layer 4 has been formed at room temperature via the oxide film 3 (FIG. 1).
(5)). Next, the bond wafer 2 is peeled off by the encapsulation layer 5 by a heat treatment at 500 ° C. or more to make it thinner (FIG. 1 (6)). The SOI wafer 6 having the above is manufactured (FIG. 1 (7)).

Next, a connection region between the SOI layer penetrating the buried oxide film and the substrate is formed. First, a thermal oxide film 13 is formed on the surface of the SOI layer (FIG. 1 (8)), and a photoresist 7 is formed.
Is applied (FIG. 1 (9)), and is exposed and developed to form a pattern partially having an opening 8 (FIG. 1 (10)). Then, after removing the oxide film 13 in the opening 8 with an aqueous HF solution (FIG. 1 (11)), the photoresist 7 is removed with an aqueous solution of sulfuric acid and hydrogen peroxide (FIG. 1 (12)). Furthermore, KO
The SOI layer 12 in the opening 8 is removed with an H solution (FIG. 1 (13)). Then, the HF aqueous solution is used for SOI
The oxide film 13 on the surface of the layer is removed, and the buried oxide film 3 exposed in the opening 8 is over-etched.
An overhang portion 9 of the I layer is formed (FIG.
4)). Finally, for example, high-temperature hydrogen annealing is performed to attach the overhang portion 9 to the base wafer 1 side, and the SOI
A connection region 10 between the layer and the substrate is formed (FIG.
5)).

Further, in the above-described embodiment, the ion implantation separation method (a so-called smart cut technique) is used for thinning the bond wafer.
The thickness of the bond wafer may be reduced by a generally used method such as polishing, vapor phase etching, or ordinary etching.

Further, the heat treatment for attaching the overhang portion to the base wafer side may be performed in a reducing atmosphere containing hydrogen by using a rapid heating / cooling device. In this case, silicon reflow easily occurs, and the overhang portion easily adheres to the base wafer side. Further, when a rapid heating / cooling device is used, the heat treatment time is extremely short, so that hydrogen in the atmosphere does not enter from the crystal defects in the SOI layer and etch the buried oxide film. In addition, such SO
As an apparatus capable of rapidly heating and rapidly cooling an I wafer under a reducing atmosphere, an apparatus such as a lamp heater using heat radiation can be cited. As commercially available products, for example, SHS-2800 manufactured by AST
Such devices are not particularly complicated and expensive.

Next, another example of the production method of the present invention will be described. FIG. 2 shows a pattern in which an opening is formed on the surface of an SOI layer, silicon is ion-implanted from the opening, and a silicon-rich region penetrating the buried oxide film is partially formed in the buried oxide film. 9 illustrates a method of forming a connection region between a layer and a substrate.

First, a base wafer 1 and a bond wafer 2 are prepared (FIG. 2A). On the surface of the bond wafer 2, a thermal oxide film 3 to be a buried oxide film later is formed (FIG. 2B), and on the surface of the base wafer 1, a polysilicon layer 4 to be a gettering site is deposited (FIG. 2).
(3)). The bond wafer 2 on which the oxide film 3 is formed and the base wafer 1 on which the polysilicon layer 4 is formed are brought into close contact with each other at room temperature (FIG. 2 (4)), and a heat treatment at, for example, 1100 ° C. or more is performed to firmly bond the two wafers. Join (Fig. 2
(5)). Next, after grinding and polishing the bond wafer 2,
It is thinned by performing a gas phase etching to obtain SO
An II layer 12 is formed, and an SOI wafer 6 having a gettering site on the supporting substrate side is manufactured (FIG. 2 (6)).

Next, a connection region between the SOI layer and the substrate is formed. First, a photoresist 7 is applied to the SOI layer 12 (FIG. 2 (7)), and is exposed and developed to form a pattern partially having an opening 8 (FIG. 2 (8)). Silicon is ion-implanted from the opening 8 (FIG. 2 (9)). Opening 8
The implantation depth is adjusted so that the silicon implanted from the silicon is implanted into the buried oxide film 3. The silicon ions are trapped in the photoresist 7 in the portions that are not opened. Next, the photoresist 7 is removed with sulfuric acid and an aqueous solution of hydrogen peroxide (FIG. 2 (10)). Finally, annealing is performed in a nitrogen atmosphere to activate the ion-implanted silicon, and a silicon-rich region penetrating the buried oxide film is partially formed in the buried oxide film, thereby forming a connection region 10 between the SOI layer 12 and the substrate. (FIG. 2 (11)).

In the above embodiment, the thinning of the bond wafer is performed by performing gas phase etching from grinding and polishing. However, as described above, another method such as an ion implantation separation method is used. It doesn't matter. Further, when a pattern having a partial opening is formed, the method is not limited to a method of applying a photoresist, but may be a method of forming an oxide film, for example.

In the method shown in FIGS. 1 and 2, the gettering site formed on the base wafer side is formed by depositing a polysilicon layer on the surface of the base wafer.
When the gettering site is formed in this manner, even if heat treatment such as a device process is performed a plurality of times, a small stacking fault serving as a gettering site is supplied from the polysilicon layer for each heat treatment, so that the gettering effect is maintained. There is an advantage of doing. Further, since the polysilicon layer promotes oxygen precipitation, the IG effect can be enhanced.

Also, a gettering site can be formed by providing a damage layer on at least one surface of the base wafer by sandblasting or the like. Forming the gettering site in this way has the advantage that the gettering site can be formed very easily and at low cost.

On the other hand, gettering sites may be formed by subjecting the base wafer to IG heat treatment to precipitate oxygen precipitation nuclei and oxygen precipitates. By forming the gettering site in this manner, there is an advantage that the IG heat treatment can be performed in a clean room without introducing a new impurity in the gettering process itself.

If the connection region between the SOI layer penetrating the buried oxide film and the substrate is formed so as to coincide with the scribe line at the time of device fabrication, the device is separated from the scribe line into chips after device fabrication. Thus, a complete SOI structure can be obtained. Alternatively, even if the connection area and the scribe line do not always match, if a part that does not require the SOI structure is arranged so as to be the connection area in the device configuration, the necessary part can be made to have the SOI structure, And a high gettering effect can be obtained.

[0043]

EXAMPLES The present invention will now be described specifically with reference to examples and comparative examples, but the present invention is not limited to these examples. (Example 1) An SOI wafer was manufactured by the method shown in FIG. First, each has a diameter of 200 mm, a P type, and an orientation <10
0>, a base wafer 1 and a bond wafer 2 having a resistivity of 10 Ω · cm are prepared (FIG. 1A), and an oxide film 3 having a thickness of 75 nm is formed on the surface of the bond wafer 2 by thermal oxidation (FIG. 1). (2)) Hydrogen ions were implanted at an implantation energy of 31 keV so as to have a density of 8 × 10 ¹⁶ atoms / cm ² to form an encapsulation layer 5 (FIG. 1 (3)). On the other hand, a 1 μm polysilicon layer was deposited on the surface of the base wafer 1 (FIG. 1 (4)).

The ion-implanted surface of the bond wafer 2 and the base wafer 1 were brought into close contact with each other at room temperature (FIG. 1).
(5)). Next, a peeling heat treatment was applied at 500 ° C. for 30 minutes in a nitrogen atmosphere to peel and thin the bond wafer 2 to obtain an SOI layer 12 having a thickness of 200 nm (FIG. 1).
(6)). A bonding heat treatment at 1100 ° C. for 2 hours is performed in a nitrogen atmosphere to firmly bond the SOI layer 12 (FIG. 1).
(7)) An SOI wafer 6 in which the polysilicon layer 4 was formed on the base wafer 1 was produced.

Next, a connecting portion between the SOI layer and the buried oxide film was formed. After a thermal oxide film 13 having a thickness of 200 nm is formed on the surface of the SOI layer (FIG. 1 (8)), a photoresist 7 is formed.
Was applied (FIG. 1 (9)), and exposed and developed to form a pattern partially having an opening 8 (FIG. 1 (10)). 5%
After removing the oxide film 13 in the opening 8 with an aqueous HF solution (FIG. 1 (11)), the photoresist 7 was removed with an aqueous solution of sulfuric acid and hydrogen peroxide (FIG. 1 (12)). The SOI layer 12 in the opening 8 is removed with a 10% KOH aqueous solution (60 ° C.) (FIG. 1 (13)), and the buried oxide film exposed in the opening 8 is over-etched with a 5% HF aqueous solution, and
The overhang portion 9 of the I layer was formed (FIG. 1 (1)
4)). Finally, hydrogen annealing was performed by a rapid heating and rapid cooling device at 1200 ° C. for 60 seconds to attach an overhang portion to the base wafer 1 side, thereby forming a connection portion 10 between the SOI layer and the buried oxide film (FIG. 1 (15) )).

The surface of the SOI layer of this SOI substrate has a 5 ×
Deliberately apply 10 ¹² atoms / cm ² of copper and nickel.
After oxidation in an oxygen atmosphere containing water vapor at 100 ° C., the crystal defect density on the surface was measured by a general selective etching technique. As a result, the crystal defect density on the SOI layer surface was 10 / cm ² or less, and it was found that the SOI layer had a high gettering effect. Also, there is no problem in the bonding strength between the base wafer and the bond wafer.
The non-defective rate when the OI wafer was manufactured was 100%.

Example 2 An SOI wafer was manufactured by the method shown in FIG. First, each has a diameter of 200 mm, P
A base wafer 1 and a bond wafer 2 having a mold, an orientation <100>, and a resistivity of 10Ω · cm were prepared (FIG. 2A).
500 nm thick by thermal oxidation on the surface of the bond wafer 2
Oxide film 3 is formed (FIG. 2 (2)), and base wafer 1 is formed.
1 .mu.m of a polysilicon layer 4 was deposited on the surface of FIG.
(3)). Then, the bond wafer 2 and the base wafer 1 were brought into close contact with each other at room temperature (FIG. 2D), and a bonding heat treatment was applied at 1100 ° C. for 2 hours in a nitrogen atmosphere (FIG. 2).
(5)). Furthermore, the bond wafer 2 is ground and polished.
The thickness of the SOI wafer 6 having a 0.3 μm-thick SOI layer 12 was manufactured by performing a gas phase etching described in Japanese Patent No. 25656517 called PACE processing (FIG. 2 (6)).

Next, a connecting portion between the SOI layer and the buried oxide film was formed. Photoresist 7 on the surface of SOI layer 12
Was applied (FIG. 2 (7)), and exposed and developed to form a pattern partially having an opening 8 (FIG. 2 (8)). Si
Ions are implanted into the buried oxide film 3 (FIG. 2 (9)), and the resist 7 is removed with an aqueous solution of sulfuric acid and hydrogen peroxide (FIG. 2).
(10)). Finally, annealing was performed in a nitrogen atmosphere to activate the ion-implanted silicon, and a silicon-rich region penetrating the buried oxide film was partially formed in the buried oxide film, thereby forming a connection region 10 between the SOI layer and the substrate. (FIG. 2 (11)).

On the surface of the SOI layer 12 of this SOI substrate,
Apply 5 × 10 ¹² atoms / cm ² of copper and nickel, and apply 11
After oxidation in an oxygen atmosphere containing water vapor at 00 ° C.,
The crystal defect density on the surface was measured by a general selective etching technique. As a result, the crystal defect density on the SOI layer surface was 10
Particles / cm ² or less, indicating a high gettering effect. Also, there is no problem in the bonding strength between the base wafer and the bond wafer.
The yield rate when wafers were manufactured was 100%.

(Comparative Example) An SOI wafer was manufactured by the method shown in FIG. First, each 200mm in diameter, P type,
Base wafer 1 with azimuth <100> and resistivity 10 Ω · cm
And a bond wafer 2 were prepared (FIG. 3A). A 1 μm polysilicon layer 4 was deposited on the surface of the base wafer 1 (FIG. 3B). Next, S is applied to the surface of the base wafer 1.
An i ₃ N ₄ film 11 was formed (FIG. 3 (3)), and selectively etched away by photolithography to use it as a selective oxidation mask (FIG. 3 (4)). Next, Si ₃ N ₄
Using the film 11 as a mask, an oxide film 3 having a thickness of 500 nm was formed on the surface of the bond wafer 2 by thermal oxidation.
(5)). Then, the Si ₃ N ₄ film 11 of the mask is removed (FIG. 3 (6)). Next, the base wafer 1 is flattened by mechanical polishing (FIG. 3 (7)). Then, the bond wafer 2 and the base wafer 1 were brought into close contact with each other at room temperature, and a bonding heat treatment was applied at 1100 ° C. for 2 hours in a nitrogen atmosphere (FIG. 3 (8)). Further, the bond wafer 2 was made 4 μm in thickness by grinding and polishing, and an SOI wafer having an SOI layer 12 having a thickness of 0.3 μm was produced by PACE processing (FIG. 3 (9)).

The surface of the SOI layer of this SOI substrate has 5 ×
Apply copper and nickel of 10 ¹² atoms / cm ² ,
After oxidation in an oxygen atmosphere containing water vapor at 2 ° C. for 2 hours, the crystal defect density on the surface was measured by a general selective etching technique. As a result, the crystal defect density on the SOI layer surface was 10 / cm ² or less, and it was found that the SOI layer had a high gettering effect. However, a void (unbonded portion) was generated between the base wafer and the bond wafer, and the bonding strength at that portion was low. Therefore, when 100 SOI wafers were manufactured by this method, the non-defective rate was only 60%.

The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the scope of the claims of the present invention. It is included in the technical scope of the invention.

For example, the manufacturing steps shown in the above embodiment are not limited to those listed above, and there may be various other steps such as cleaning, heat treatment, and the like. The process can be appropriately changed and used.

[0054]

As described above, by using the method of the present invention, an SOI wafer having a high gettering effect and containing few heavy metal impurities in the SOI layer can be produced with high productivity.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an example of a manufacturing method of the present invention, in which an opening reaching a buried oxide film is formed on the surface of an SOI layer, and the buried oxide film exposed in the opening is etched to form the SOI layer. By performing heat treatment after forming the overhang portion, SOI penetrating the buried oxide film is formed.
FIG. 4 is a diagram illustrating a method of forming a connection region between a layer and a substrate.

FIG. 2 is a flowchart showing another example of the manufacturing method of the present invention, in which a pattern having an opening is formed on the surface of an SOI layer, silicon is ion-implanted from the opening, and FIG. 4 is a diagram illustrating a method of forming a connection region between an SOI layer and a substrate by partially forming a silicon-rich region penetrating through the substrate.

FIG. 3 is a flowchart showing a conventional method for manufacturing an SOI wafer in which a connection region between an SOI layer and a support substrate is formed.

[Explanation of symbols]

1: Base wafer, 2: Bond wafer, 3, 1
DESCRIPTION OF SYMBOLS 3 ... Oxide film, 4 ... Polysilicon layer, 5 ... Microbubble layer (encapsulation layer), 6 ... SOI wafer, 7 ... Photoresist, 8 ... Opening, 9 ... Overhanging part, 10 ... Connection area, 11 ... Si ₃ N ₄ film, 12 ... SOI layer.

Claims (16)

[Claims] 1. A base wafer serving as a substrate on which a gettering site is formed and a bond wafer serving as an SOI layer are bonded via an oxide film serving as a buried oxide film, and the bond wafer is formed into a thin film to form an SOI layer. Forming an opening reaching the buried oxide film on the surface of the SOI layer, etching the buried oxide film exposed in the opening to form an overhang portion of the SOI layer, and then performing a heat treatment. , The SOI penetrating through the buried oxide film
Forming a connection region between the layer and the substrate;
A method for manufacturing an I wafer. 2. The method for producing an SOI wafer according to claim 1, wherein the heat treatment is performed in a reducing atmosphere containing hydrogen using a rapid heating / rapid cooling device. 3. A base wafer serving as a substrate on which a gettering site is formed and a bond wafer serving as an SOI layer are bonded via an oxide film serving as a buried oxide film, and the bond wafer is thinned to form an SOI layer. Forming a pattern having an opening on the surface of the SOI layer;
Silicon is ion-implanted from the opening and a silicon-rich region penetrating through the buried oxide film is partially formed in the buried oxide film to form a connection region between the SOI layer and the substrate; Method. 4. The method according to claim 1, wherein the gettering site is formed by subjecting a base wafer to IG heat treatment to precipitate oxygen precipitation nuclei or oxygen precipitates. SOI wafer manufacturing method. 5. The SOI wafer according to claim 1, wherein the gettering site is formed by depositing a polysilicon layer on at least one surface of the base wafer. Manufacturing method. 6. The method according to claim 1, wherein the gettering site is formed by providing a damage layer on at least one surface of the base wafer.
The method for producing an SOI wafer according to any one of the above items. 7. A connection region between an SOI layer penetrating the buried oxide film and a substrate is formed so as to coincide with a scribe line.
The method for producing an SOI wafer according to any one of the above items. 8. An SOI wafer manufactured by the method according to any one of claims 1 to 7. 9. A substrate having a gettering site formed thereon and S
An SOI wafer comprising an OI layer and a buried oxide film between the two, and having a connection region between the SOI layer and the substrate penetrating the buried oxide film, wherein the connection region is formed on the surface of the SOI layer by the buried oxide film. An SOI wafer formed by forming an opening reaching the opening, etching a buried oxide film exposed in the opening to form an overhang portion of the SOI layer, and then performing a heat treatment. 10. The SOI wafer according to claim 9, wherein the heat treatment is performed in a reducing atmosphere containing hydrogen using a rapid heating / cooling device. 11. An SOI wafer comprising a substrate on which a gettering site is formed, an SOI layer, and a buried oxide film between the two, and having a connection region between the SOI layer and the substrate penetrating the buried oxide film, The SOI wafer is characterized in that the connection region is formed by ion-implanting silicon from the surface of the SOI layer and partially providing a silicon-rich region penetrating the buried oxide film. 12. The method according to claim 9, wherein the gettering site is formed by subjecting a base wafer to IG heat treatment to precipitate oxygen precipitation nuclei or oxygen precipitates. Item 2. The SOI wafer according to item 1. 13. The method according to claim 9, wherein the gettering site is formed by depositing a polysilicon layer on at least one surface of the base wafer. SOI described
Weeha. 14. The gettering site according to claim 9, wherein the gettering site is formed by providing a damage layer on at least one surface of the base wafer.
The SOI wafer according to claim 11. 15. The SOI wafer according to claim 9, wherein the connection region is formed so as to coincide with a scribe line. 16. An SOI wafer comprising a substrate on which a gettering site is formed, an SOI layer, and a buried oxide film between the two, and having a connection region between the SOI layer and the substrate penetrating the buried oxide film, SOI wafer characterized in that the connection area is formed so as to coincide with the scribe line.