JP2006005341A - Laminating soi substrate and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminating SOI substrate, capable of treating a metal dopant of SOI layer in gettering at heat treatment time in device process, and its manufacturing method. <P>SOLUTION: A crystal defect R is formed in a resistive layer 10b of a wafer 10 for active layer. This can make the metal dopant existing in a SOI layer 10A be caught by the crystal defect R at the heat treating time in the device process. As a result, nonconformity making the properties of a device deteriorate can be suppressed, in such a way that the crystal defects or electric rank order caused by heavy metal contamination occurs near the front surface of the SOI layer 10A. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bonded SOI substrate and a manufacturing method thereof, and more particularly to a bonded SOI substrate in which a gettering site is formed in an SOI layer and a manufacturing method thereof.

A bonded SOI (Silicon on Insulator) substrate is known as a kind of bonded substrate formed by bonding two silicon wafers. This is an insulating film (silicon oxide film) embedded between an SOI layer (active layer) on which a device is formed on the front surface and a support substrate wafer that supports the device from the back side. Conventionally, a bonded SOI substrate in which a high-concentration n ⁺ layer is ion-implanted in an n-type SOI layer has also been developed.
Hereinafter, a conventional method for manufacturing a bonded SOI substrate having an n ⁺ layer will be described with reference to the flow sheet of FIG.

  As shown in this figure, a single crystal silicon ingot doped with a predetermined amount of arsenic or antimony is pulled up by the CZ method. Thereafter, block cutting, notching, slicing, chamfering, mirror polishing on the surface, and the like are sequentially performed on the obtained single crystal silicon ingot. Thus, an n-type active layer wafer (CZ wafer) 101 having a mirror finish of 8 inches in diameter is obtained (FIG. 5A). On the other hand, a similar support substrate wafer 102 having a mirror-finished surface is prepared by the same manufacturing method as this active layer wafer 101 (FIG. 5B). Thereafter, the support substrate wafer 102 is inserted into a thermal oxidation furnace, where it is thermally oxidized to form an insulating silicon oxide film 102a on the surface thereof.

Next, the active layer wafer 101 is implanted from the wafer surface with arsenic or antimony, which is an n-type dopant, at an implantation energy of 80 KeV and a dose of 2 × 10 ¹⁵ atoms / cm ² using the inside of the medium current ion implantation apparatus. . Thereby, the ion implantation layer I is formed at a predetermined depth of the surface layer of the active layer wafer 101.
Thereafter, the mirror surfaces of both wafers 101 and 102 are superposed at room temperature in a clean room. Thereby, the bonded wafer 103 is produced. By this bonding, the portion of the silicon oxide film 102a interposed between the active layer wafer 101 and the support substrate wafer 102 becomes the buried silicon oxide film 102b.

Next, the bonded wafer 103 is inserted into a bonding thermal oxidation furnace, and bonded and heat-treated in an oxygen gas atmosphere. The temperature of the bonding heat treatment is 1100 ° C., and the heat treatment time is 2 hours (FIG. 5C). As a result, a silicon oxide film is formed on the entire exposed surface of the bonded wafer 103. At this time, arsenic or antimony of the ion implantation layer I is thermally diffused in the vicinity of the surface on the bonding side of the active layer wafer 101 to form an n ⁺ layer (high concentration impurity layer) 101a. As a result, when the active layer wafer 101 includes the buried silicon oxide film (SiO ₂ ) 102b, the active layer wafer 101 has an n / n ⁺ / SiO ₂ structure.

  Next, a void inspection by ultrasonic irradiation is performed. For the non-defective bonded wafer 103, the bonding failure area due to the outer peripheral shape of both the chamfered wafers 101 and 102 is removed. Specifically, the outer peripheral portion of the active layer wafer 101 is subjected to outer peripheral grinding from the device forming surface side with a # 800 to # 1500 metal bond grinding wheel (FIG. 5D). The peripheral grinding is stopped at a depth that does not reach the bonding interface.

Subsequently, the uncut portion 101c is removed by alkali etching (FIG. 5E). That is, the bonded wafer 103 is immersed in an alkaline etching solution such as KOH, and the uncut portion 101c is melted (peripheral etching). In this manner, the outer peripheral region of the support substrate wafer 102, specifically, the outer peripheral portion of the buried silicon oxide film 102b is exposed.
Next, the active layer wafer 101 is ground and polished from the device forming surface side. Thus, a bonded SOI substrate having the n / n ⁺ / SiO ₂ structure and having the SOI layer 101A formed thereon is manufactured. (FIG. 5 (f)).

By the way, in the device process for forming a semiconductor device on the SOI layer 101A of the bonded SOI substrate, the degree of contamination of metal impurities (iron, copper, nickel, etc.) on the SOI layer 101A having the n ⁺ layer 101a is regarded as important. In addition, as a problem specific to the bonded SOI substrate with ion implantation, metal contamination occurs in the ion implantation process and the subsequent high-temperature annealing process (for example, thermal oxidation and bonding heat treatment), which is a problem.

  If metal contamination in these steps remains in the SOI layer 101A even after product shipment, defects and electrical levels are formed in the vicinity of the surface of the SOI layer 101A, and device characteristics deteriorate. This problem also occurs when metal contamination occurs in the device process. As a result, the device yield decreases. Therefore, in recent years, there is a demand for a bonded SOI substrate that exhibits a gettering effect that can be continued from ion implantation to a device process without forming defects or electrical levels in the vicinity of the surface of the SOI layer 101A.

Conventionally, for example, a method described in Patent Document 1 is known as a countermeasure against such metal contamination. In this method, oxygen precipitates serving as gettering sites for metal impurities are formed in substantially the entire area of the support substrate wafer, and dislocation groups are formed in the vicinity of the buried oxide film of the support substrate wafer. These oxygen precipitates and dislocation groups are all IG (Intrinsic Gettering) layers formed in the support substrate wafer.
JP-A-8-293589

  However, according to the conventional method for manufacturing a bonded SOI substrate, since the IG layer is formed on the support substrate wafer in this way, the diffusion rate in the buried oxide film is slow (cannot penetrate the buried oxide film). Iron, nickel, etc. in the layer could not be gettered to the IG layer of the support substrate wafer.

  Further, in the CZ method, when the ingot is pulled up, segregation in which the dopant is biased easily occurs in a part of the single crystal silicon ingot. Due to this segregation, a variation in resistance value of about 25% (non-uniform dopant concentration) occurred between sliced silicon wafers (active layer wafers). In addition, even within the surface of a single silicon wafer, a variation in resistance value of about 10% occurred. Therefore, in the device factory, as a pretreatment for forming a device on the SOI layer of the bonded SOI substrate, a predetermined amount of dopant is ion-implanted into the SOI layer, and the resistance value of the SOI layer between wafers and in the wafer surface is adjusted. It was. As a result, the manufacturing cost of the bonded SOI substrate has increased.

On the other hand, as another method for eliminating variations in the resistance value of the SOI layer between the wafers and within the wafer surface, for example, the SOI layer is formed by epitaxially growing silicon on the surface of the support substrate wafer on which the silicon oxide film is formed. Methods for filming are known.
However, even in this method, in order to perform epitaxial growth, an active layer wafer and a support substrate wafer are simply bonded together, and then the active layer wafer is ground and polished from the back side to form a thin film. Compared to general-purpose products, the manufacturing cost was increased.

Therefore, as a result of intensive studies, the inventors have previously formed a gettering site in the n ⁺ layer (high-concentration impurity layer / resistance layer formed by ion implantation) of the active layer wafer, so that heat treatment in the device process is performed. At this time, it was discovered that metal impurities such as iron and nickel that exist in the SOI layer and have a low diffusion rate (cannot penetrate) in the buried insulating film can be collected at the gettering site, and the present invention is completed. I let you.

In addition, as a result of earnest research, the inventors have formed an oxide film on the active layer wafer after ion implantation of a predetermined amount of dopant into the active layer wafer, and further bonded the active layer wafer to the support substrate wafer. It was conceived that the ion-implanted dopant was thermally diffused to the periphery by heat treatment, and the active layer wafer after bonding was thinned to form an SOI layer composed of a dopant diffusion layer. As a result, the inventors have found that it is possible to reduce variations in the resistance value of the SOI layer between wafers and within the wafer surface and to form a gettering site in the SOI layer, thereby completing the present invention.
In this way, if a gettering site is formed on the buried oxide film side of the SOI layer, metal impurities attached to the surface of the SOI layer, metal impurities existing in the SOI layer, and the like are removed during the heat treatment in the device process. It can be collected directly on the buried oxide film.

An object of the present invention is to provide a bonded SOI substrate capable of gettering metal impurities in an SOI layer during heat treatment in a device process, and a method for manufacturing the same.
The present invention also provides a method for manufacturing a bonded SOI substrate that can getter metal contaminants that contaminate the surface layer of an active layer wafer during ion implantation.
An object of the present invention is to provide a method for manufacturing a bonded SOI substrate capable of preventing the SOI layer from being thickened due to the spread of a resistance layer (n ⁺ layer) formed by ion implantation.
The present invention provides a bonded SOI substrate capable of reducing variations in resistance values of SOI layers between wafers and within a wafer surface, and at the same time, gettering metal impurities in SOI layers during heat treatment in a device process. The purpose is to provide.

  According to the first aspect of the present invention, there is provided an SOI layer having a low-concentration impurity layer in which a dopant is present at a low concentration and a high-concentration impurity layer in which a dopant is present at a high concentration, and a support substrate wafer that supports the SOI layer. A bonded SOI substrate in which a gettering site is formed in the high-concentration impurity layer in a bonded SOI substrate bonded through a buried insulating film.

  According to the first aspect of the present invention, the gettering site is formed in the high concentration impurity layer of the SOI layer. As a result, during heat treatment in the device process, metal impurities such as iron and nickel that cannot penetrate the buried insulating film present in the SOI layer are collected at the gettering site of the high concentration impurity layer. As a result, it is possible to prevent deterioration of device characteristics caused by the formation of crystal defects and electrical levels near the surface of the SOI layer due to metal contamination due to metal impurities in the SOI layer. Therefore, the device yield increases.

As the dopant, an n-type dopant such as arsenic, antimony, and phosphorus or a p-type dopant such as boron can be employed.
For example, a silicon wafer can be used as the active layer wafer (for forming the SOI layer) and the support substrate wafer bonded to the active layer wafer via a buried insulating film. The active layer wafer and the support substrate wafer may be n-type silicon wafers doped with n-type impurities in advance, or p-type silicon wafers containing p-type impurities.
The bonding surface of the active layer wafer and the support substrate wafer is the surface on the high concentration impurity layer side.

As the buried insulating film, for example, a buried silicon oxide film or a buried silicon nitride film can be employed.
The thickness of the SOI layer is not limited. For example, it is 1-50 micrometers, Preferably it is 5 micrometers or more. The concentration difference between the dopant concentration of the high concentration impurity layer and the dopant concentration of the low concentration impurity layer is not limited. For example, the dopant concentration of the high concentration impurity layer is 1 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ . The low concentration impurity layer and the high concentration impurity layer are of the same electrode type.
As the gettering site, for example, a crystal defect can be employed. Crystal defects include point defects, line defects, surface defects, and body defects.
In order to form a high concentration layer on a substrate having a low impurity concentration (active layer wafer), there are methods such as epitaxial growth and thermal diffusion of impurities.

According to a second aspect of the present invention, there is provided an SOI layer having a low-concentration impurity layer having a low concentration of dopant and a high-concentration impurity layer obtained by heat-treating an ion-implanted layer into which a dopant is ion-implanted at a high concentration, A bonded SOI substrate in which a support substrate wafer that supports an SOI layer is bonded via a buried insulating film, wherein a gettering site is formed in the high-concentration impurity layer.
In the bonded SOI substrate according to the second aspect of the present invention, gettering sites are formed in the high concentration impurity layer formed by ion implantation. Metal impurities are collected at this gettering site.

  According to a third aspect of the present invention, there is provided a bonded SOI substrate in which an SOI layer in which a dopant is present at a predetermined concentration and a support substrate wafer that supports the SOI layer are bonded via a buried insulating film. The variation of the resistance value of the SOI layer during the period and the variation of the resistance value of the SOI layer within the wafer surface were 5% or less, respectively, and a gettering site was formed on the buried insulating film side of the SOI layer. This is a bonded SOI substrate.

According to the invention of claim 3, after ion implantation of a predetermined amount of dopant into the active layer wafer, the active layer wafer is subjected to an oxidation heat treatment to form an oxide film. During the formation of this oxide film, the amorphous layer that has become amorphous by ion implantation is recrystallized. However, since interstitial oxygen and interstitial silicon are supplied to the amorphous layer, single crystallization of the active layer wafer is hindered, and crystal defects such as dislocations and stacking faults are generated. Moreover, the ion-implanted dopant is thermally diffused in the active layer wafer by heat during the oxidation heat treatment.
Next, the active layer wafer is bonded to the support substrate wafer to form a bonded wafer. Then, a bonding heat treatment is performed on the bonded wafer. At this time, the ion-implanted dopant is further thermally diffused to the periphery. Subsequently, the active layer wafer is thinned (for example, ground or polished) to form an SOI layer formed of a dopant diffusion layer. Note that the thinning process may be performed before the bonding heat treatment.

  With this configuration, variation in the resistance value (dopant concentration) of the SOI layer between wafers and within the wafer surface can be reduced to 5% or less. In addition, gettering sites are formed on the buried oxide film side of the SOI layer. Therefore, metal impurities adhering to the surface of the SOI layer and metal impurities existing in the SOI layer (especially iron, nickel, etc., in which the embedded oxide film is difficult to penetrate) are removed from the SOI layer during heat treatment in the device process. Can be collected.

The variation in the resistance value of the SOI layer between the wafers means that two arbitrarily selected bonded substrates are bonded on a large number of bonded SOI substrates manufactured based on a large number of wafers obtained from one single crystal ingot. It means variation in resistance value between SOI layers of the SOI substrate.
The variation in the resistance value of the SOI layer in the wafer surface is the number of bonded SOI substrates manufactured based on a large number of wafers obtained from one single crystal ingot, and the SOI layer of each bonded SOI substrate. This is the variation in resistance value distribution across the entire surface.
If the variation in resistance value exceeds 5%, an optimization process in the device process is required. If the variation in resistance value is 5% or less, an effect of stabilizing the quality of the bonded SOI substrate can be obtained.
As the gettering site, for example, the crystal defects (dislocations, stacking faults, etc.) can be employed.

The invention described in claim 4 is the bonded SOI substrate according to any one of claims 1 to 3, wherein the gettering site is a dislocation or a stacking fault.
When the stress (compression, tension, shear) generated inside the crystal exceeds the yield point of elastic deformation of the crystal, the partial region of the crystal is displaced by the distance of the repeating unit of the crystal lattice along the slip surface, and the stress is relaxed To do. At the end of the boundary surface (slip surface) between the displaced region and the non-displaced region, mismatching between atoms occurs. A linear region where this mismatch occurs is a dislocation. Generally, it is a complex dislocation. The size of the dislocation is about 0.01 to 0.10 μm.
In addition, the {111} plane of the silicon crystal having a diamond crystal structure forms a crystal in which repeating units are sequentially overlapped in a plane arrangement relationship. A stacking fault is one in which an extra atomic plane is interrupted in this arrangement, or one in which an atomic plane is missing from this arrangement.
The dislocation density and stacking fault density are, for example, 1 × 10 ⁰ to 1 × 10 ⁷ pieces / cm ² . 1 In × 1 × 10 than ⁰ / cm ^2, insufficient gettering occurs. Further, when the dislocation density is high when it exceeds 1 × 10 ⁷ pieces / cm ² , the dislocation changes to slip dislocation when the trench groove is formed in the SOI layer in the device process.

  The invention according to claim 5 is a bonded SOI in which an SOI layer in which an ion-implanted dopant is thermally diffused over the entire area and a support substrate wafer that supports the SOI layer are bonded together via a buried insulating film. The substrate is a bonded SOI substrate in which variations in the resistance value of the SOI layer between wafers and variations in the resistance value of the SOI layer in the wafer surface are each 5% or less.

  The invention according to claim 6 is a step of providing a high concentration impurity layer containing a dopant at a high concentration on the surface side of the active layer wafer containing a dopant at a low concentration, and a surface of the high concentration impurity layer of the active layer wafer. Manufacturing a bonded SOI substrate comprising a step of generating dislocations or stacking faults in the vicinity, and a bonding step of bonding the active layer wafer and a support substrate wafer supporting the active layer wafer through a buried insulating film Is the method.

According to the invention described in claim 6, since dislocations or stacking faults as gettering sites are formed in the high-concentration impurity layer of the SOI layer, it exists in the SOI layer due to heat during the heat treatment in the device process. Metal impurities that collect are collected in dislocations or stacking faults. As a result, due to metal contamination of the SOI layer, crystal defects and electrical levels are formed in the vicinity of the surface of the SOI layer, and deterioration of device characteristics can be suppressed. Therefore, the device yield increases.
The high concentration impurity layer is formed by, for example, an epitaxial growth method or a thermal diffusion method.

  The invention according to claim 7 is an ion implantation step of forming an ion implantation layer by ion implantation of a dopant on the surface side of an active layer wafer containing a dopant at a low concentration. Heat treatment is performed on the wafer to make the ion implantation layer a high concentration impurity layer, and an oxide film is formed on the ion implantation surface of the wafer for the active layer to generate dislocations or stacking faults near the surface of the high concentration impurity layer. A heat treatment step, an oxide film removal step for removing the oxide film, and a bonding step for bonding the active layer wafer and a support substrate wafer for supporting the wafer through a buried insulating film. This is a method for manufacturing a laminated SOI substrate.

  According to the seventh aspect of the present invention, since dislocations or stacking faults as gettering sites are formed in the high concentration impurity layer of the SOI layer, the buried insulating film existing in the SOI layer cannot be transmitted during the heat treatment in the device process. Metal impurities such as iron and nickel are diffused by heat, and the metal impurities present in the diffused SOI layer are collected by dislocations or stacking faults. As a result, it is possible to suppress degradation of device characteristics due to formation of crystal defects and electrical levels near the surface of the SOI layer due to metal contamination of the SOI layer. Therefore, the device yield increases.

Further, an oxide film is formed on the ion implanted surface of the wafer for active layer, since in the step of generating dislocations or stacking faults, which are heat-treated in the presence of oxygen in the surface and or the interface of the oxide film, Si-SiO ₂ A large amount of interstitial Si is generated at the interface. This collects in the damaged portion of the ion implantation, and dislocations or stacking faults occur.
Furthermore, for example, when the surface of the active layer wafer is contaminated with contaminants such as boron and aluminum due to cross-contamination during ion implantation, by oxidizing the ion implantation surface, metal contaminants, etc. It can be taken into the oxide film. Thus, by removing the oxide film in the subsequent oxide film removal step, these metal impurities and the like are also removed from the surface layer of the active layer wafer.

The ion implantation is a method in which an n-type or p-type dopant is ionized in a gaseous state using an ion implantation apparatus, accelerated by an electric field, and implanted into the wafer from the exposed surface of the wafer. Impurity atoms ionized by the high frequency discharge of the ion generator are given energy of about 10 to 200 KeV by the acceleration system, and then only desired ions are selected by the mass spectrometry system and scanned in the XY directions by the deflection system. The wafer is driven into the active layer wafer. For example, according to the medium current ion implantation apparatus, a medium dose amount and a low dose amount of 1 × 10 ¹⁴ atoms / cm ² or less can be implanted with high productivity with high productivity in an energy region of several KeV to several hundred KeV. .

  The ion implantation apparatus is classified based on the beam current obtained for each ion. For example, a medium current ion implanter, a large current ion implanter, a high energy ion implanter, and the like can be given. These ion implantation apparatuses mainly include an ion source, a mass analyzer, an acceleration tube, an ion deflection system, and an ion implantation chamber. These are operated in a high vacuum system. In ion implantation by an ion implantation apparatus, specific ions are extracted and accelerated by a mass analyzer. However, it may be separated after acceleration.

  If there is a risk of metal contamination due to cross contamination during ion implantation, screen oxide may be formed in advance on the active layer wafer, and then ion implantation may be performed. In that case, after ion implantation, it is necessary to remove the screen oxide from the active layer wafer, and then perform SC-1 cleaning and SC-2 cleaning. If there is no risk of cross contamination, it is not necessary to form screen oxide, and the active layer wafer may be subjected to SC-1 cleaning and SC-2 cleaning even after ion implantation.

  For example, the buried insulating film may be formed by forming an insulating film (for example, a silicon oxide film) on the active layer wafer and / or the supporting substrate wafer, and bonding the two wafers together. In that case, the insulating layer may be formed on either the active layer wafer or the support substrate wafer. Furthermore, both wafers may be used. The method for forming the insulating film is not limited. For example, when the insulating film is an oxide film, dry oxidation, wet oxidation, or the like can be employed.

The bonding process is performed, for example, after the oxide film removing process.
The bonding of both wafers is performed at room temperature, for example. Thereafter, a bonding heat treatment may be performed on the obtained bonded wafer. The heating temperature of the bonding heat treatment is 800 ° C. or higher, for example, 1100 ° C. The bonding heat treatment time is, for example, 2 hours. Examples of the atmospheric gas include oxygen. During the bonding heat treatment, the dopant in the ion implantation layer of the active layer wafer may be thermally diffused to form a high concentration impurity layer.
The bonded wafer is then subjected to a surface treatment that reduces the thickness of the active layer wafer. Specifically, grinding and polishing can be employed. Etching may also be used.

The temperature of the heat treatment for generating dislocations or stacking faults is 400 to 1200 ° C, preferably 800 to 1000 ° C. Below 400 ° C., the growth rate of the oxide film is slow. On the other hand, if it exceeds 1200 ° C., the high-concentration impurity layer becomes too thick.
The atmosphere for forming the oxide film is a dry atmosphere or a pyrotechnic atmosphere.
The ion implantation surface on which the oxide film is formed is the ion implantation surface (wafer surface) of the active layer wafer.
The oxide film is formed on the ion implantation surface side of the active layer wafer so as to be continuous with the ion implantation layer in the thickness direction of the active layer wafer.
The thickness of the oxide film is preferably 10 to 500 nm. The thickness of the oxide film can be appropriately selected according to the type of dopant, implantation energy, and dose.
When the dislocation density is high, the dislocation may change into slip dislocation when a trench groove is formed in the SOI layer in the device process.

The invention according to claim 8 is the method for manufacturing a bonded SOI substrate according to claim 6 or 7, wherein the insulating film to be the buried insulating film is formed only on the support substrate wafer.
When an insulating film is formed on the ion implantation surface (bonding surface) of the active layer wafer, the heat treatment time becomes longer. Therefore, the dopant diffuses in the active layer wafer, and the high concentration impurity layer becomes thick.

Further, when an insulating film is formed on the active layer wafer and the support substrate wafer, it is necessary to perform heat treatment at a high temperature during the bonding heat treatment. Therefore, the high concentration impurity layer becomes thicker.
As a result, when the insulating film is formed only on the support substrate wafer and the two wafers are bonded together, the increase in the thickness of the high-concentration impurity layer in the subsequent heat treatment step can be suppressed. As a result, the trench groove formation time in the device process can be shortened. Therefore, the manufacturing cost of the device can be reduced.

  The invention according to claim 9 is a step of ion-implanting a dopant from the surface of the active layer wafer into the active layer wafer containing non-doped or dopant at a low concentration, and after the ion implantation, the active layer wafer is A step of heat-treating in an oxygen atmosphere to form an oxide film on the surface of the active layer wafer and thermally diffusing the ion-implanted dopant, and after the ion implantation, the oxide film is formed on the active layer wafer. The formed surface is bonded to a support substrate wafer as a bonding surface, and an oxide film interposed between both wafers is used as a buried oxide film. After the bonding, the active layer wafer and the support substrate A bonding heat treatment for increasing the bonding strength with the wafer, and after this bonding, the active layer wafer is It treated thinned from the back side of the wafer, of the wafer for active layer, which is the ion-implanted step and method for producing a bonded SOI substrate having a a diffusion portion and the SOI layer of dopant.

  According to the ninth aspect of the present invention, after a predetermined amount of dopant is ion-implanted into the active layer wafer, an oxide film is formed on the active layer wafer. When this oxide film is formed, the amorphous layer is recrystallized. However, since interstitial oxygen and interstitial silicon are supplied to the amorphous layer, single crystallization of the active layer wafer is hindered, and crystal defects such as dislocations and stacking faults are generated. Moreover, the ion-implanted dopant is thermally diffused in the active layer wafer by heat during the oxidation heat treatment. Then, the active layer wafer is bonded to the support substrate wafer and heat-treated. At this time, the ion-implanted dopant is thermally diffused. However, the amorphous layer cannot be completely crystallized under the conditions during the bonding heat treatment. Therefore, a part of the amorphous layer remains as a crystal defect on the buried silicon oxide film side of the SOI layer. Subsequently, the active layer wafer is thinned to form an SOI layer including a dopant diffusion layer. As a result, variations in the resistance value of the SOI layer between wafers and within the wafer surface can be reduced to 5% or less, respectively. In addition, a gettering site is formed on the buried oxide film side of the SOI layer. Therefore, metal impurities attached to the surface of the SOI layer and metal impurities present in the SOI layer can be collected in the SOI layer during the heat treatment in the device process. In particular, the effect is remarkable when the metal impurities in the SOI layer are iron, nickel, or the like that does not penetrate the buried oxide film even when thermally diffused. The thinning process may be performed before the bonding heat treatment.

The non-doped active layer wafer refers to an active layer wafer having no dopant.
The active layer wafer containing a dopant at a low concentration refers to an active layer wafer containing a dopant that does not affect the desired concentration. In this case, the dopant contained in the active layer wafer at a low concentration may be different from the dopant to be ion-implanted.
The oxygen atmosphere for forming the oxide film is a dry oxygen atmosphere or a pyrotechnic atmosphere.

The formation temperature of the oxide film is 800 to 1200 ° C. If it is less than 800 ° C., it takes time to form an oxide film, and it takes more time because the diffusion rate of the dopant is slow. Further, if it exceeds 1200 ° C., slipping and metal contamination are likely to occur.
The oxide film is formed to a desired thickness.

The bonding heat treatment temperature between the active layer wafer and the support substrate wafer is 1000 to 1200 ° C. If it is less than 1000 degreeC, adhesive strength is weak and the diffusion rate of a dopant is also slow. Moreover, when it exceeds 1200 degreeC, it will become easy to occur a slip and metal contamination. A preferable bonding heat treatment temperature is 1150 ° C to 1200 ° C.
The method for thinning the active layer wafer from the back side (surface treatment method for reducing the thickness of the active layer wafer) is not limited. For example, the back surface side of the active layer wafer may be ground and then polished. Alternatively, etching (various dry etching or various wet etching) may be used.

The invention according to claim 10 is the method for manufacturing a bonded SOI substrate according to claim 9, wherein an oxide film is formed on the support substrate wafer before bonding to the active layer wafer.
The invention according to claim 11 is a step of ion-implanting a dopant into the active layer wafer containing non-doped or dopant at a low concentration from the surface of the active layer wafer, and the ion-implanted activity after the ion implantation. The surface of the layer wafer is bonded to the support substrate wafer having an oxide film formed on the surface as a bonding surface, and the oxide film interposed between both wafers is used as a buried oxide film, and after this bonding, The step of thermally diffusing the ion-implanted dopant by performing a bonding heat treatment for increasing the bonding strength between the active layer wafer and the support substrate wafer, and after the bonding, the active layer wafer Thinning treatment is performed from the back side of the active layer wafer, and the diffused portion of the ion-implanted dopant in the active layer wafer. Which is a method for manufacturing the bonded SOI substrate and a step of the SOI layer.

  According to the bonded SOI substrate according to claim 1, claim 2, and claim 3, and the bonded SOI substrate manufacturing method according to claim 6, the high-concentration impurity layer of the SOI layer is formed. Since the gettering site is formed, metal impurities existing in the SOI layer are collected in the gettering site during the heat treatment in the device process. As a result, it is possible to suppress deterioration of device characteristics due to the formation of crystal defects and electrical levels near the surface of the SOI layer due to metal contamination of the SOI layer. Therefore, the device yield can be increased.

In particular, according to the invention described in claim 7, in the step of forming an oxide film on the ion implantation surface of the wafer for active layer and generating dislocations or stacking faults, oxygen is present on the surface and / or interface of the oxide film. Heat treated in the state. Therefore, a large amount of interstitial Si is generated at the Si—SiO ₂ interface. These interstitial Si gather in the damaged portion of the ion implantation, and dislocations or stacking faults occur.
Furthermore, for example, when the surface of the active layer wafer is contaminated with contaminants such as boron and aluminum due to cross-contamination during ion implantation, by oxidizing the ion implantation surface, metal contaminants, etc. It can be taken into the oxide film. Thus, by removing the oxide film in the subsequent oxide film removing step, metal impurities and the like are also removed from the surface layer of the active layer wafer.

  According to the eighth aspect of the present invention, since the insulating film is formed only on the support substrate wafer, it is possible to suppress an increase in the thickness of the high concentration impurity layer during the subsequent heat treatment. As a result, the trench groove formation time in the device process can be shortened. Therefore, the manufacturing cost of the device can be reduced.

  Furthermore, according to the manufacturing method of the bonded SOI substrate according to claim 9, after forming an oxide film on the active layer wafer into which the dopant is ion-implanted, the active layer wafer is bonded to the support substrate wafer and heat treatment is performed. In addition, since the SOI layer composed of the diffusion layer of the dopant is formed by thinning the active layer wafer, variation in the resistance value of the SOI layer between wafers and within the wafer surface can be reduced to 5% or less. it can. In addition, gettering sites such as metal impurities can be formed in the SOI layer.

  Embodiments of the present invention will be described below with reference to the drawings.

  As shown in FIG. 1, a single crystal silicon ingot doped with a predetermined amount of arsenic or antimony is pulled up by CZ method (or FZ method may be used). Thereafter, the obtained single crystal silicon ingot is subjected to block cutting, notching, slicing, chamfering, mirror polishing on the surface, and the like. In this way, an n-type active layer wafer 10 having a mirror finish of 8 inches in diameter is prepared (FIG. 1A). On the other hand, a similar support substrate wafer 20 having a mirror-finished surface is prepared by the same manufacturing method as the active layer wafer 10 (FIG. 1B). Thereafter, the support substrate wafer 20 is inserted into a thermal oxidation furnace and subjected to a thermal oxidation treatment at 1050 ° C. for 4 hours in an atmosphere of water vapor gas. Thereby, a silicon oxide film (insulating film) 20a having a thickness of 1.0 μm is formed.

Next, arsenic or antimony, which is an n-type dopant, is implanted from the surface of the active layer wafer 10 at an implantation energy of 80 KeV and a dose amount of 2 × 10 ¹⁵ atoms / cm ² , for example. Thereby, the ion implantation layer I is formed in the predetermined depth of the surface layer of the wafer 10 for active layers.
Then, the active layer wafer 10 is inserted into a thermal oxidation furnace and subjected to a thermal oxidation treatment at 1000 ° C. for 0.5 hours in an oxygen gas atmosphere. As a result, a silicon oxide film 10a having a thickness of 0.05 μm is formed on the active layer wafer 10 (FIG. 1C). At this time, arsenic or antimony of the ion implantation layer I is thermally diffused near the surface of the active layer wafer 10 to form a resistance layer (high concentration impurity layer / n ⁺ layer) 10b formed by ion implantation. Moreover, crystal defects (dislocations, stacking faults) R, which are gettering sites, occur between the silicon oxide film 10a and the resistance layer (hereinafter referred to as resistance layer) 10b formed by this ion implantation. That is, since the silicon oxide film 10a is formed in an atmosphere of oxygen gas, the Si-SiO ₂ near the interface caused a large amount of interstitial Si, these interstitial Si gather the damaged portions of the ion implantation, crystal defects R (FIGS. 2 and 3).

Thereafter, the active layer wafer 10 is immersed in a 10 wt% hydrofluoric acid solution (room temperature) for 10 minutes. At this time, the silicon oxide film 10a is removed together with metal contaminants attached to the surface (FIG. 1D). That is, the surface of the active layer wafer 10 is contaminated with boron, aluminum, or the like due to, for example, cross contamination during ion implantation. These metal contaminants and the like are taken into the silicon oxide film 10a when the silicon oxide film 10a is formed. As a result, by removing the silicon oxide film 10a, metal impurities and the like are also removed from the active layer wafer 10. A part of the crystal defect R remains at the Si—SiO ₂ interface of the active layer wafer 10. Then, the active layer wafer 10 is SC-1 cleaned and SC-2 cleaned to clean the surface of the active layer wafer 10.

Thereafter, the surface of the active layer wafer 10 (the surface on the crystal defect R side) and the mirror surface of the support substrate wafer 20 are superposed at room temperature in a clean room (FIG. 1E). In this way, the bonded wafer 30 is formed. At this time, the portion of the silicon oxide film 20a interposed between the wafers 10 and 20 becomes the buried silicon oxide film (buried insulating film) 20b.
Next, the bonded wafer 30 is inserted into a thermal oxidation furnace for bonding, and a bonding heat treatment is performed at 1100 ° C. for 2 hours in an oxygen gas atmosphere (FIG. 1E).

  Then, a void inspection by ultrasonic irradiation is performed. For the non-defective bonded wafer 30, the outer peripheral portion of the active layer wafer 10 is removed from the device forming surface side in order to remove the bonding failure region caused by the outer peripheral shape of both the chamfered wafers 10 and 20. The outer periphery is ground by a metal bond grinding wheel of 800 to # 1500 (FIG. 1 (f)). If there is a bonding failure region, the defective portion is peeled off during subsequent cleaning or polishing, and the surface of the SOI layer 10A is contaminated or damaged. The peripheral grinding is stopped at a depth that does not reach the bonding interface. The thickness of the uncut portion 10c on the outer periphery of the wafer is about 30 μm.

Subsequently, the uncut portion 10c is removed by alkali etching (FIG. 1 (g)). That is, the bonded wafer 30 is immersed in an alkaline etching solution such as KOH, and the uncut portion 10c is melted. In this way, the outer peripheral region of the support substrate wafer 20, specifically, the outer peripheral portion of the buried silicon oxide film 20 b is exposed.
Next, the active layer wafer 10 is ground from the device forming surface side by a # 360 to # 2000 resinoid grinding wheel (FIG. 1H). The grinding amount is 650 to 700 μm, and the thickness of the SOI layer 10A after grinding is about 20 μm.

Then, the ground surface of the active layer wafer 10 is polished (also FIG. 1 (h)). Specifically, the bonded wafer 30 is held on the lower surface of a polishing head of a single wafer polishing apparatus (not shown) with the active layer wafer 10 side facing downward. Next, the polishing head rotating at 60 rpm is gradually lowered, and the ground surface of the active layer wafer 10 is pressed against the polishing cloth on the polishing platen rotating at 60 rpm with a predetermined polishing pressure to polish. The polishing cloth is a soft non-woven pad, Suba600 (Asker hardness 80 °) manufactured by Rodel. The polishing amount is about 10 to 15 μm.
Thus, a bonded SOI substrate 40 on which the SOI layer 10A having an n / n ⁺ (including crystal defects) / SiO ₂ structure is formed is manufactured (FIG. 1H).
Thereafter, the obtained bonded SOI substrate 40 is cleaned, packed in a wafer case or the like, and then shipped to a device manufacturer.

Thus, since the crystal defect R is formed in the resistance layer 10b of the SOI layer 10A, the metal impurities present in the SOI layer 10A are collected in the crystal defect R such as dislocation or stacking fault during the heat treatment in the device process. As a result, it is possible to suppress the deterioration of device characteristics due to the formation of crystal defects and electrical levels near the surface of the SOI layer 10A due to metal contamination of the SOI layer 10A. Therefore, the device yield can be increased.
In addition, since the silicon oxide film 20a for the buried silicon oxide film 20b is formed only on the support substrate wafer 20, an increase in the thickness of the resistance layer 10b can be suppressed during the subsequent heat treatment. As a result, it is possible to shorten the trench groove formation time (not shown) in the device process. Therefore, the manufacturing cost of the device can be reduced.
Although the ion implantation method has been described as the method for forming the high concentration impurity layer, it is needless to say that the method is not limited to this. For example, a method of growing a high concentration epitaxial layer on the surface of a low concentration silicon substrate can be employed. Thus, the gettering site can be formed by an arbitrary method.

Next, with reference to FIG. 4, a bonded SOI substrate and a manufacturing method thereof according to Embodiment 2 of the present invention will be described.
As shown in FIG. 4, a single crystal silicon ingot not doped with a dopant is pulled up by the CZ method. Thereafter, the obtained single crystal silicon ingot is subjected to block cutting, notching, slicing, chamfering, mirror polishing on the surface, and the like. Thus, a mirror-finished non-doped active layer wafer 10 having a diameter of 8 inches is prepared (FIG. 4A). On the other hand, a similar support substrate wafer 20 having a mirror-finished surface is prepared by the same manufacturing method as the active layer wafer 10 (FIG. 4B).

Next, arsenic or antimony is implanted from the surface of the active layer wafer 10 at an implantation energy of 60 KeV and a dose of 1 × 10 ¹⁵ atoms / cm ² , for example. Thereby, the ion implantation layer I is formed in the predetermined depth of the surface layer of the wafer 10 for active layers. At this time, the active layer wafer 10 of the ion implantation layer I is amorphized.
Then, the active layer wafer 10 is inserted into a thermal oxidation furnace and subjected to thermal oxidation treatment at 1150 ° C. for 2 hours in an oxygen gas atmosphere. As a result, a silicon oxide film 10a having a thickness of 1 μm is formed on the active layer wafer 10 (FIG. 4C). At this time, arsenic or antimony of the ion implantation layer I is thermally diffused near the surface of the active layer wafer 10 to form the n layer 10b. In addition, a crystal defect R as a gettering site is generated between the silicon oxide film 10a and the n layer 10b. That is, since the silicon oxide film 10a is formed in an atmosphere of oxygen gas, the Si-SiO ₂ near the interface caused a large amount of interstitial oxygen and interstitial Si, these interstitial oxygen and interstitial Si is ion-implanted The crystal defects R are collected at the damaged portion (FIGS. 2 and 3).
Then, the active layer wafer 10 is SC-1 cleaned and SC-2 cleaned to clean the surface of the active layer wafer 10.

Thereafter, the surface of the active layer wafer 10 and the mirror surface of the support substrate wafer 20 are overlaid at room temperature in a clean room (FIG. 4D). In this way, the bonded wafer 30 is formed. At this time, the portion of the silicon oxide film 10a interposed between the wafers 10 and 20 becomes the buried silicon oxide film 10c.
Next, the bonded wafer 30 is inserted into a thermal oxidation furnace for bonding, and a bonding heat treatment is performed at 1100 ° C. for 2 hours in an oxygen gas atmosphere (FIG. 4D).

  Then, a void inspection by ultrasonic irradiation is performed. For the non-defective bonded wafer 30, the outer peripheral portion of the active layer wafer 10 is subjected to outer peripheral grinding from the device forming surface side with a # 800 to # 1500 metal bond grinding wheel in order to remove the defective bonding region ( FIG. 4 (e)). The thickness of the uncut portion 10d on the outer periphery of the wafer is about 50 μm.

Subsequently, the uncut portion 10d is alkali-etched with an alkaline etchant such as KOH (FIG. 4 (f)). In this way, the outer peripheral region of the support substrate wafer 20 is exposed.
Next, the active layer wafer 10 is ground from the device forming surface side by a # 360 to # 2000 resinoid grinding wheel (FIG. 4G). The thickness of the SOI layer 10A after grinding is about several tens of μm.

Then, the ground surface of the active layer wafer 10 is polished (also FIG. 4G). Specifically, the bonded wafer 30 is held on the lower surface of a polishing head of a single wafer polishing apparatus (not shown) with the active layer wafer 10 side facing downward. Next, the polishing head rotating at 60 rpm is gradually lowered, and the ground surface of the active layer wafer 10 is pressed against the polishing cloth on the polishing platen rotating at 60 rpm with a predetermined polishing pressure to polish. The polishing cloth is a soft non-woven pad, Suba600 (Asker hardness 80 °) manufactured by Rodel. The polishing amount is about 10 μm.
Thus, a bonded SOI substrate 40 on which the SOI layer 10A having an n (including crystal defect R) / SiO ₂ structure is formed is manufactured (FIG. 4G).
Thereafter, the obtained bonded SOI substrate 40 is cleaned, packed in a wafer case or the like, and then shipped to a device manufacturer.

  Thus, since the crystal defect R is formed in the n layer 10b which is the SOI layer 10A, the metal impurities existing in the SOI layer 10A are collected in the crystal defect R such as dislocation or stacking fault during the heat treatment in the device process. As a result, it is possible to suppress the deterioration of device characteristics due to the formation of crystal defects and electrical levels near the surface of the SOI layer 10A due to metal contamination of the SOI layer 10A. Therefore, the device yield can be increased.

  Further, during the oxidation heat treatment of the active layer wafer 10 into which the dopant is ion-implanted, the amorphous layer generated in the active layer wafer 10 due to the ion implantation is recrystallized due to the heat at that time. However, since the active layer wafer 10 is heat-treated in an oxygen atmosphere, interstitial oxygen and interstitial silicon are supplied to the amorphous layer. As a result, single crystallization of the active layer wafer 10 is inhibited, and crystal defects R such as dislocations and stacking faults are generated. In addition, when the oxide film is formed, the ion-implanted dopant is thermally diffused in the active layer wafer 10. This thermal diffusion is promoted during the subsequent bonding heat treatment. However, the amorphous layer cannot be completely crystallized under the conditions during the bonding heat treatment. Therefore, a part of the amorphous layer remains as a crystal defect R on the buried silicon oxide film 10c side of the SOI layer 10A.

As a result, the variation in the resistance value of the SOI layer 10A between wafers and within the wafer surface is conventionally equal to 150% of the variation in the resistance value of the SOI layer between wafers, and the resistance value of the SOI layer within the wafer surface. Any variation of 10% can be reduced to 5% or less (here 3%).
Further, a gettering site is formed on the SOI layer 10A on the buried silicon oxide film 10c side. Therefore, metal impurities adhering to the surface of the SOI layer 10A and metal impurities existing in the SOI layer 10A can be collected in the SOI layer 10A during the heat treatment in the device process. The effect is particularly remarkable when the metal impurity is iron, nickel, or the like that is difficult to thermally diffuse into the buried silicon oxide film 10c.

  Thus, the resistance value of the SOI layer 10 </ b> A is determined by the dopant ion implantation conditions for the active layer wafer 10 and the heat treatment conditions for the bonded wafer 30. Therefore, the bonded SOI substrate 40 with small variations in the resistance value of the SOI layer 10A between wafers and within the wafer surface can be manufactured. Moreover, when the amorphous ion implantation layer I is recrystallized, a crystal defect R is generated. As a result, a gettering site including crystal defects R is formed on the buried silicon oxide film 10c side of the SOI layer 10A.

In the second embodiment, an oxide film may be formed on the support substrate wafer 20 in advance.
In Example 2, arsenic and antimony are employed as dopants. These dopants are difficult to be taken into the silicon oxide film during the thermal oxidation treatment of the active layer wafer 10. For this reason, the dopant concentration in the vicinity of the active layer wafer 10 side of the buried silicon oxide film 10c increases after the thermal oxidation treatment. However, the dopant concentration in the highly concentrated portion of the active layer wafer 10 is leveled by reheating during the bonding heat treatment. Thereby, the resistance value between the wafers of the bonded SOI substrate 40 and within the wafer surface is made uniform.
Further, when boron is employed as the dopant, boron is taken into the buried silicon oxide film 10c during the thermal oxidation process. Thereby, the dopant concentration in the vicinity of the SOI layer 10A side of the buried silicon oxide film 10c is lowered. However, by reheating during the bonding heat treatment, the dopant concentration in the highly concentrated portion of the active layer wafer 10 is leveled, and the resistance value between the wafers of the bonded SOI substrate 40 and within the wafer surface is made uniform. To do.
In any of the dopants, when the dopant concentration is not leveled during the bonding heat treatment, the active layer wafer 10 is thinned after the bonding heat treatment, and then further heat-treated, thereby performing the leveling (each resistance). Value equalization). This heat treatment may be performed in a wafer manufacturing process or a device process.

Further, the active layer wafer 10 to be used may not be a non-doped wafer but may be a low dose wafer in which a dopant is present at a low concentration as in the first embodiment.
Then, a through oxide film (not shown) may be formed on the active layer wafer 10 before ion implantation into the active layer wafer 10. The through oxide film is a silicon oxide film that prevents the active layer wafer from being contaminated with boron, aluminum, or the like due to cross contamination during ion implantation. The through oxide film is removed from the active layer wafer together with contaminants such as boron and aluminum by contacting with a hydrofluoric acid solution after ion implantation.
An oxide film may be formed in advance on the support substrate wafer.
After the bonding, the heat treatment may be performed after the active layer wafer is thinned. In that case, since the SOI layer 10A is thin, the uniform resistance value between the wafers and within the wafer surface is further promoted.
Further, a portion where the dopant for ion implantation is not thermally diffused may be left in the SOI layer 10A. At that time, for example, during the heat treatment in the device process, the resistance values between the wafers and in the wafer surface are made uniform.

It is a flow sheet which shows the manufacturing method of the bonding SOI substrate which concerns on Example 1 of this invention. It is a photomicrograph of the crystal defects generated in the Si-SiO ₂ interface of the active layer of the present invention. It is a schematic diagram of a TEM photograph of the crystal defects generated in the Si-SiO ₂ interface of the active layer of the present invention. It is a flow sheet which shows the manufacturing method of the bonding SOI substrate which concerns on Example 2 of this invention. It is a flow sheet which shows the manufacturing method of the bonding SOI substrate which concerns on the conventional means.

Explanation of symbols

10 Active layer wafer,
10A SOI layer,
10a Silicon oxide film,
10b resistance layer formed by ion implantation,
20 Support substrate wafer,
20a Silicon oxide film (insulating film),
20b embedded silicon oxide film (embedded insulating film),
30 bonded wafers,
40 Bonded SOI substrate,
I ion implantation layer,
R Crystal defect (gettering site; dislocation or stacking fault).

Claims (11)

An SOI layer having a low-concentration impurity layer in which dopant is present at a low concentration and a high-concentration impurity layer in which dopant is present at a high concentration, and a support substrate wafer that supports the SOI layer are bonded together via a buried insulating film. In the bonded SOI substrate,
A bonded SOI substrate in which a gettering site is formed in the high concentration impurity layer. An SOI layer having a high-concentration impurity layer obtained by heat treatment of a low-concentration impurity layer in which a dopant is present at a low concentration and an ion-implanted layer in which the dopant is ion-implanted at a high concentration, and a wafer for a support substrate that supports the SOI layer Are bonded via an embedded insulating film, in a bonded SOI substrate,
A bonded SOI substrate in which a gettering site is formed in the high concentration impurity layer. In a bonded SOI substrate in which an SOI layer in which a dopant is present at a predetermined concentration and a support substrate wafer that supports the SOI layer are bonded together through a buried insulating film,
The variation in the resistance value of the SOI layer between the wafers and the variation in the resistance value of the SOI layer in the wafer surface are 5% or less, respectively.
A bonded SOI substrate in which a gettering site is formed on the buried insulating film side of the SOI layer.   The bonded SOI substrate according to any one of claims 1 to 3, wherein the gettering site is a dislocation or a stacking fault. In a bonded SOI substrate in which an SOI layer in which an ion-implanted dopant is thermally diffused over the entire area and a support substrate wafer that supports the SOI layer are bonded together via a buried insulating film.
A bonded SOI substrate in which variation in resistance value of the SOI layer between wafers and variation in resistance value of the SOI layer in a wafer surface are each 5% or less. Providing a high-concentration impurity layer containing a dopant at a high concentration on the surface side of the active layer wafer containing the dopant at a low concentration;
A step of generating dislocations or stacking faults near the surface of the high-concentration impurity layer of the wafer for active layer;
A method for manufacturing a bonded SOI substrate, comprising: a bonding step of bonding the active layer wafer and a supporting substrate wafer supporting the active layer wafer through a buried insulating film. An ion implantation step of forming an ion implantation layer by ion implantation of the dopant on the surface side of the wafer for active layer containing the dopant in a low concentration;
After the ion implantation, the active layer wafer is subjected to a heat treatment to make the ion implanted layer a high-concentration impurity layer, and an oxide film is formed on the ion implantation surface of the active layer wafer. A heat treatment step for generating dislocations or stacking faults near the surface;
An oxide film removing step for removing the oxide film;
A method for manufacturing a bonded SOI substrate, comprising: a bonding step of bonding the active layer wafer and a supporting substrate wafer supporting the active layer wafer through a buried insulating film.   The method for manufacturing a bonded SOI substrate according to claim 6 or 7, wherein an insulating film to be the embedded insulating film is formed only on the support substrate wafer. A step of ion-implanting a dopant into the active layer wafer containing a non-doped or dopant at a low concentration from the surface of the active layer wafer;
After the ion implantation, the active layer wafer is heat-treated in an oxygen atmosphere to form an oxide film on the surface of the active layer wafer and to thermally diffuse the ion implanted dopant;
After the ion implantation, the active layer wafer is bonded to the support substrate wafer with the surface on which the oxide film is formed as a bonding surface, and the oxide film interposed between the two wafers is used as a buried oxide film. When,
After the bonding, a step of performing a bonding heat treatment for increasing the bonding strength between the active layer wafer and the support substrate wafer;
After the bonding, the active layer wafer is thinned from the back surface side of the active layer wafer, and the ion-implanted dopant diffusion portion of the active layer wafer is used as an SOI layer; and A method for manufacturing a bonded SOI substrate comprising:   The method for manufacturing a bonded SOI substrate according to claim 9, wherein an oxide film is formed on the supporting substrate wafer before bonding to the active layer wafer. A step of ion-implanting a dopant into the active layer wafer containing a non-doped or dopant at a low concentration from the surface of the active layer wafer;
After this ion implantation, the surface of the ion-implanted active layer wafer is bonded to a support substrate wafer having an oxide film formed on the surface, and an oxide film interposed between both wafers is buried and oxidized. A film forming step;
After the bonding, a step of thermally diffusing the ion-implanted dopant by performing a bonding heat treatment for increasing the bonding strength between the active layer wafer and the support substrate wafer;
After the bonding, the active layer wafer is thinned from the back surface side of the active layer wafer, and the ion-implanted dopant diffusion portion of the active layer wafer is used as an SOI layer; and A method for manufacturing a bonded SOI substrate comprising: