WO2007097179A1

WO2007097179A1 - Method for manufacturing soi substrate

Info

Publication number: WO2007097179A1
Application number: PCT/JP2007/051894
Authority: WO
Inventors: Hiroshi Takeno; Nobuhiko Noto
Original assignee: Shin-Etsu Handotai Co., Ltd.
Priority date: 2006-02-21
Filing date: 2007-02-05
Publication date: 2007-08-30
Also published as: JP2007227459A

Abstract

This invention provides a method for manufacturing an SOI substrate, comprising applying a single crystal silicon substrate, into which at least arsenic or antimony as an active impurity has been introduced to form a high-concentration layer, to a high-concentration layer-free single crystal silicon substrate through a silicon oxide film, heat treating the assembly for bonding, and then thinning the high-concentration layer-formed single crystal silicon substrate to form an SOI substrate comprising an SOI layer provided on the silicon oxide film, the SOI layer having an arsenic or antimony-containing high-concentration buried diffusion layer, wherein the active impurity is introduced by ion implantation, the acceleration energy in the ion implantation is brought to not more than 130 keV, and the thickness of the SOI layer is brought to not less than 3 μm. According to the method for manufacturing an SOI substrate, an SOI substrate in which an excellent metal contamination gettering capability has been imparted to an SOI layer having a high-concentration-buried diffusion layer, can be efficiently manufactured with high productivity at low cost.

Description

Specification

Manufacturing method of SOI substrate

Technical field

The present invention relates to a method for manufacturing an SOI (Silicon On Insulator) substrate by a bonding method, and more particularly to a method for manufacturing an SOI substrate having an excellent gettering ability for metal impurities. Background art

As one of semiconductor device substrates, there is an SOI substrate in which an SOI layer (silicon layer) is formed on a silicon oxide film that is an insulating film. In this SOI substrate, the SOI layer on the surface layer of the substrate, which is a device manufacturing region, is electrically isolated from the inside of the substrate by the silicon oxide film (buried oxide film layer (BOX layer)). It has features such as small capacity and high radiation resistance. Therefore, high-speed, low-power consumption operation, soft error prevention, and other effects are expected, and it is promising as a substrate for high-performance semiconductor devices.

As a method for manufacturing this SOI substrate, for example, the following method is known. In other words, prepare two mirror-polished single crystal silicon substrates (single crystal silicon substrate (bonded UENO), which will be the SOI layer, and single crystal silicon substrate (base wafer), which will be the support substrate). A silicon oxide film is formed on the surface of one silicon substrate. These single crystal silicon substrates are bonded together with a silicon oxide film interposed therebetween, and then heat-treated to increase the bond strength. Thereafter, a bond substrate is thinned to obtain an SOI substrate on which an SOI (Silicon on Insulator) layer is formed. Examples of the thin film method include polishing the bond wafer to a desired thickness I ”, a polishing method, a method called ion implantation separation method, and a method of peeling the bond wafer with an ion implantation layer.

[0004] As described above, the SOI substrate has many structural advantages from the viewpoint of electrical characteristics. It has structural disadvantages from the viewpoint of resistance to metal impurity contamination. That is, in many cases, the diffusion rate of metal impurities is slower in the silicon oxide film than in silicon. As a result, if the SOI layer surface force is also contaminated, Since it does not easily pass through the conoxide film (BOX layer), it accumulates in a thin SOI layer. As a result, the adverse effects of metal contamination are greater than in the case of a silicon substrate without an SOI structure. Therefore, in the SOI substrate, one of the more important qualities is to have the ability to capture metal impurities and remove them from the region that becomes the active layer of the semiconductor element (gettering ability).

[0005] Gettering methods (oxygen precipitates, high-concentration boron addition, backside polycrystalline silicon film, etc.) that are generally used in the case of a silicon substrate without an SOI structure are all opposite to the active layer. A gettering layer is introduced into the supporting substrate. However, even if a gettering layer is introduced on the support substrate side using the same method in the SOI substrate, the metal impurities do not easily pass through the silicon oxide film (BOX layer) as described above. This gettering layer does not function sufficiently, and there is a problem that these methods cannot be applied to SOI substrates as they are.

[0006] In order to solve these problems, methods for introducing a gettering region in the vicinity of the SOI layer of the SOI substrate have been proposed several times.

For example, a method of providing a region containing a high concentration of an impurity such as phosphorus or boron as a gettering in a selective region of an SOI layer is disclosed in JP-A-6-163862 and JP-A-10-32209. It has been.

However, such a method has a problem that the number of steps for introducing impurities increases, resulting in an increase in cost and a decrease in productivity. Moreover, if impurities introduced for gettering diffuse and reach the active layer of the semiconductor element due to heat treatment in the SOI substrate manufacturing process or device process, there is a concern about adverse effects on electrical characteristics.

[0007] As another method, Japanese Patent Application Laid-Open No. 6-275525 discloses a method of forming a polycrystalline silicon layer in the SOI layer region near the interface between the SOI layer and the BOX layer, and gettering metal impurities. It is shown. However, in this case as well, there is a problem that the number of steps for forming the polycrystalline silicon layer is increased, the cost is increased, and the productivity is lowered. Further, when the SOI layer is thin, it is very difficult to form a polycrystalline silicon layer.

On the other hand, there is an SOI substrate on which an SOI layer having a high-concentration buried diffusion layer is formed as a three-dimensional structure and a high breakdown voltage of a bipolar IC or the like. As a method for manufacturing such an SOI substrate, for example, active impurities are gas diffused in a single crystal silicon substrate (bondueha). Alternatively, there is a method in which a high concentration layer is formed by introduction by an ion implantation method and bonded to another single crystal silicon substrate (base wafer) having a silicon oxide film formed on the surface.

(See, for example, JP 2000-196047 A).

In the case of an SOI substrate having such a high concentration buried diffusion layer, the high concentration buried diffusion layer is not provided for gettering as described in Japanese Patent Laid-Open No. 10-32209. As the (active element), arsenic antimony, which is not phosphorus or boron as described in JP-A-10-32209, is often used. Therefore, the gettering ability of an SOI substrate having a high concentration buried diffusion layer containing arsenic or antimony has become important.

In order to add sufficient gettering capability to an SOI substrate having such a high concentration buried diffusion layer containing arsenic or antimony, a region containing a high concentration of impurities such as phosphorus and boron is buried in a high concentration. It is conceivable to adopt a method of providing the SOI layer separately from the diffusion layer or a method of forming the polycrystalline silicon layer on the SOI layer. However, if these methods are adopted, additional special new processes such as a process for introducing impurities such as phosphorus and boron and a process for forming a polycrystalline silicon layer will be added, resulting in high costs. As a result, productivity decreases and is inefficient. Disclosure of the invention

[0011] The present invention provides an SOI substrate in which an SOI layer having a high concentration buried diffusion layer and an excellent gettering capability against metal contamination is added. An object is to provide a method for manufacturing a substrate.

In order to achieve the above object, the present invention provides a single crystal silicon substrate in which a high concentration layer is formed by introducing at least arsenic or antimony as active impurities, and a single crystal silicon substrate in which a high concentration layer is not formed Are bonded to each other through a silicon oxide film, and after a bonding heat treatment, the single crystal silicon substrate on which the high-concentration layer is formed is thinned to form 1 X on the silicon oxide film. In a method of manufacturing an SOI substrate having an SOI layer having a high concentration buried diffusion layer containing arsenic or antimony of 10 ¹⁸ atomsZcm ³ or more, the introduction of the active impurity is performed by ion implantation. Acceleration energy at the time of 130keV A method for manufacturing an SOI substrate is provided, which is performed as follows and the thickness of the SOI layer to be formed is 3 m or more.

[0013] In this way, when introducing the active impurity arsenic or antimony by the ion implantation method, the acceleration energy is set to 130 keV or less, so that the SOI layer Z silicon oxide film (BOX Layer) Excellent gettering ability can be added near the interface. It also serves as the formation of a high-concentration buried diffusion layer necessary for the structure, and does not add a special new process. As a result, the SOI substrate can be efficiently manufactured without reducing productivity and increasing the cost and cost.

In addition, since the SOI layer has a thickness of 3 m or more, there is little risk that ion-implanted Sb and As are thermally diffused and overlapped with the active layer of the semiconductor element during heat treatment such as bonding heat treatment. There is also little risk of overlapping of the tulling site and the active layer of the semiconductor element. Therefore, the electrical characteristics of the active layer of the semiconductor device will not be adversely affected!

[0014] In the method for manufacturing an SOI substrate according to the present invention, it is preferable that acceleration energy at the time of ion implantation of the active impurities is 30 keV or more.

[0015] As described above, when the acceleration energy at the time of ion implantation is set to 30 keV or more, arsenic or antimony can be introduced to a certain depth in the single crystal silicon substrate. For this reason, even if the single crystal silicon substrate is cleaned before bonding, the damage layer for forming the gettering site due to the etching action of the cleaning liquid is less likely to be removed.

Furthermore, in the method for manufacturing an SOI substrate of the present invention, it is preferable that acceleration energy at the time of ion implantation of the active impurity is higher than lOOkeV.

As described above, by setting the acceleration energy at the time of ion implantation of the active impurities higher than lOOkeV, arsenic or antimony can be introduced at a sufficiently deep position in the single crystal silicon substrate.

[0018] Further, in the method for manufacturing an SOI substrate of the present invention, the silicon oxide film is formed on a surface of a single crystal silicon substrate on which the high concentration layer is not formed, and the high concentration layer is interposed through the silicon oxide film. It is preferable to bond the single crystal silicon substrate on which the second layer is formed.

[0019] When a silicon oxide film is formed on the surface of a single crystal silicon substrate on which a high concentration layer is formed, If the damaged layer or the high concentration layer formed by the on implantation is consumed by the silicon oxide film, the gettering ability may be lowered. From this, it is preferable to form a silicon oxide film on the surface of the single crystal silicon substrate on which the high concentration layer is not formed as described above, in order to more reliably add an excellent gettering capability.

In the method for manufacturing an SOI substrate of the present invention, the bonding heat treatment is performed at a heat treatment temperature of 1000 ° C. to 1300 ° C. and a heat treatment time of 0.5 hours to 8 hours. Can do.

In the present invention, since the thickness of the SOI layer is 3 μm or more, even if high-temperature and long-time bonding heat treatment is performed in this way, the ion-implanted Sb and As are thermally diffused, and the semiconductor element There is little risk of overlapping with the active layer. Thus, a strong bond is achieved.

As described above, in the present invention, when manufacturing an SOI substrate having a high concentration buried diffusion layer, active impurities are introduced by an ion implantation method, and the acceleration energy at the time of ion implantation is 130 keV or less. The thickness of the SOI layer to be formed is 3 m or more. For this reason, an SOI substrate in which an SOI layer having a high-concentration buried diffusion layer is added with an excellent gettering ability against metal contamination can be efficiently manufactured at a low cost with good productivity without deteriorating electrical characteristics. can do. Brief Description of Drawings

FIG. 1 is a flow sheet showing an example of a method for manufacturing an SOI substrate according to the present invention.

FIG. 2 is a graph showing an example of a measurement result of a depth distribution of Ni concentration.

BEST MODE FOR CARRYING OUT THE INVENTION

[0024] Hereinafter, the present invention will be described more specifically.

As described above, an SOI substrate in which an SOI layer having a high-concentration buried diffusion layer and an excellent gettering ability against metal contamination can be efficiently manufactured at low cost with good productivity. The development of the manufacturing method was awaited.

[0025] Therefore, the present inventors have sufficient gettering ability for the SOI layer without adding any special process such as a process of introducing impurities such as phosphorus and boron and a process of forming a polycrystalline silicon layer. We have been eagerly investigating whether or not. [0026] As a result, the present inventors have focused on performing ion implantation to form a high concentration layer by introducing arsenic or antimony into a single crystal silicon substrate in an SOI substrate having a high concentration buried diffusion layer. The inventors have found that by devising the ion implantation conditions, the gettering ability can be enhanced without adding a special process.

That is, the present inventors have found that the acceleration energy at the time of ion implantation of active impurities is closely related to the gettering ability, and completed the present invention.

[0027] Hereinafter, the present invention will be described in more detail with reference to the drawings. The present invention is not limited to these.

FIG. 1 is a flow sheet showing an example of a method for manufacturing an SOI substrate by a bonding method. An outline of a method for manufacturing an SOI substrate by a bonding method to which the present invention is applied is as follows.

[0028] First, in step (a), a single crystal silicon substrate (Bondeha) 11 as an SOI layer for forming a semiconductor element and a single crystal silicon substrate (base wafer) 12 as a support substrate are prepared.

Next, in step (b), a silicon oxide film 13 to be a BOX layer is formed on the surface of the single crystal silicon substrate 12.

On the other hand, if a silicon oxide film is formed on the surface of a single crystal silicon substrate (Bondueno), on which a high concentration layer is formed, the damage layer and high concentration layer described later are consumed by the silicon oxide film. There is a risk. In this case, the gettering ability may be reduced. For this reason, it is preferable to form a silicon oxide film on the surface of a single crystal silicon substrate (base wafer) that does not form a high-concentration layer as described above in order to more reliably add excellent gettering capability. ,.

Next, in the step (c), an active element arsenic or antimony is introduced near the surface of the single crystal silicon substrate 11 to form the high concentration layer 14.

At this time, in the present invention, active impurities are introduced by ion implantation with an acceleration energy at the time of ion implantation of 130 keV or less. As a result, an excellent gettering capability can be added near the interface of the SOI layer Z silicon oxide film (BOX layer) of the manufactured SOI substrate. It also serves as the formation of a high-concentration buried diffusion layer that is necessary for the structure. It does not add a process. Therefore, it is possible to efficiently manufacture an SOI substrate without reducing productivity and increasing the cost.

[0031] If the acceleration energy at the time of ion implantation is set to 30 keV or more, arsenic or antimony can be introduced to a certain depth deep in the single crystal silicon substrate. For this reason, even if the single crystal silicon substrate is cleaned before bonding, there is little risk that the damage layer for forming the gettering site is removed by the etching operation of the cleaning liquid.

[0032] Furthermore, by increasing the acceleration energy at the time of ion implantation of active impurities to 80 keV or higher, particularly higher than 10 OkeV, arsenic or antimony can be introduced into a sufficiently deep position of the single crystal silicon substrate. .

Incidentally, the dose of the active element, but are not particularly limited, is determined in consideration of the electrical characteristics of a semiconductor element manufactured on the SOI layer, be, for example, 4 X 10 ¹⁵ at _O msZcm ² about Can do.

Further, prior to ion implantation, a screen oxide film (surface protective acid film) may be formed on the surface of a single crystal silicon substrate (Bondeino) on which a high concentration layer is formed. . Also, what is the order of step (b) and step (c)?

Next, in the step (d), the single crystal silicon substrate 11 on which the high concentration layer 14 is formed and the single crystal silicon substrate 12 on which the silicon oxide film 13 is formed and on which the high concentration layer is not formed are high concentration. The layer 14 and the silicon oxide film 13 are adhered and bonded together. In this way, you will get Lamination 15

Next, in the step (e), a bonding heat treatment for increasing the bonding strength is performed. By this combined heat treatment, the elements in the high concentration layer are activated and diffused to form the high concentration buried diffusion layer 17.

In the present invention, this bonding heat treatment is preferably performed at a heat treatment temperature of 1000 ° C. to 1300 ° C. and a heat treatment time of 0.5 hours to 8 hours. More preferably, the heat treatment temperature is from 1050 ° C. to 1200 ° C., and the heat treatment time is from 1 hour to 3 hours. This allows two wafers to be tightly coupled.

Next, in step (f), the single crystal silicon substrate 11 on which the high concentration layer is formed is formed to a desired thickness. The SOI substrate 19 having the SOI layer 16, the high-concentration buried diffusion layer 17, and the silicon oxide film (buried oxide film (BOX layer)) 18 is obtained. The thinning at this time can be performed, for example, by surface grinding, mirror polishing or etching, etc. The high-concentration buried diffusion layer 17 on the silicon oxide film (BOX layer) 18 is 1 × 10 ¹⁸ ato Contains at least ³ msZcm of arsenic or antimony. Since the concentration of arsenic or antimony is appropriately selected according to the standard, the upper limit is not particularly limited, but is, for example, 5 × 10 ¹⁹ atoms Zcm ³ or less.

In the present invention, the thickness of the SOI layer 16 to be formed is 3 m or more by this thin film.

If the thickness of the SOI layer 16 is less than 3 μm, for example, a heat treatment temperature of 1000 ° C or higher and 1300 ° C or lower and a heat treatment time of 0.5 hours or longer and 8 hours or shorter can be used. Due to the heat treatment in the device manufacturing process, ion-implanted Sb and As may thermally diffuse and overlap with the active layer of the semiconductor element. Therefore, the electrical characteristics of the active layer of the semiconductor element can be adversely affected. Also, the gettering site must be separated from the active layer of the semiconductor element to some extent. If the thickness of the SOI layer is less than 3 m, the active layer of the semiconductor element and the gettering site may overlap. This also leads to deterioration of the electrical characteristics of the active layer itself of the semiconductor element.

However, in the present invention, as described above, the thickness of the SOI layer to be formed is set to 3 m or more, so that these problems can be effectively prevented from occurring. The upper limit of the thickness of the SOI layer is not particularly limited as long as it is determined according to the standard. For example, it is as follows.

[0038] (Experimental example)

As described above, the present inventors have found that acceleration energy at the time of ion implantation of active impurities is closely related to gettering ability. Then, we thought that the gettering ability of the finally manufactured SOI substrate could be improved by optimizing the acceleration energy during ion implantation of active impurities. Therefore, the following experiment was conducted to optimize the acceleration energy during ion implantation.

With reference to FIG. 1, one of the experiments conducted by the present inventors will be described. First, two mirror-polished N-type single crystal silicon substrates with a diameter of 200 mm and a plane orientation of {100} were prepared (see step (a) in Fig. 1).

A silicon oxide film 13 having a thickness of about 1 μm to be a BOX layer was formed on the surface of the single crystal silicon substrate 12 to be a support substrate by a thermal acid (see step (b) in FIG. 1).

Next, arsenic was ion-implanted into the entire surface of one surface of the single crystal silicon substrate 11 to be the SOI layer under the following conditions to form a high concentration layer 14 (see step (c) in FIG. 1). That is, the dose was 4E15 atoms / cm ² (4 × 10 ¹⁵ atoms / cm ² ), and the acceleration energy during ion implantation was 60, 100, 110, 130, 140, and 160 keV, respectively.

[0040] After that, the single crystal silicon substrate 11 serving as the SOI layer and the single crystal silicon substrate serving as the support substrate were adhered to each other with the high-concentration layer 14 and the silicon oxide film 13 sandwiched therebetween (step of FIG. 1). (See (d)).

Next, a bonding heat treatment was performed to increase the bonding strength (see step (e) in FIG. 1). This bonding heat treatment was performed at 1150 ° C. for 2 hours using a resistance heating type heat treatment furnace (batch furnace).

After that, the single crystal silicon substrate 11 side on which the high-concentration layer 14 of the bonded wafer 15 was formed was thinned to a thickness of about 12 m by surface grinding and mirror polishing to obtain an SOI substrate 19 ( Step (f)).

[0041] The gettering ability of the SOI substrate thus fabricated was evaluated as follows.

First, Ni was applied to the surface of the SOI layer at a concentration of about 5E12 atoms / cm ² (5 × 10 ¹² atoms / cm ² ), and was diffused inside by heat treatment at 1000 ° C. for 1 hour.

Next, the surface oxide film, SOI layer, and silicon oxide film (BOX layer) were etched stepwise, and the Ni concentration in the solution was measured by ICP-MS (inductively coupled plasma mass spectrometry). This measured the distribution of Ni concentration in the depth direction. Surface oxide film and BOX layer (silicon oxide film) were measured in 1 step each with HF solution, and SOI layer was measured in 6 steps with about 2 m steps.

Here, FIG. 2 shows an example of the measurement result of the Ni concentration in the depth direction.

From this, it can be seen that the Ni concentration is high in the depth region of 10 to 12 m including the surface layer intentionally contaminated with Ni, and the interface region of the silicon oxide film (BOX layer) and SOI layer. That is, Figure 2 The Ni concentration in the depth region of 10 to 12 m (near the bonding interface) in can be regarded as the concentration of Ni gettered near the bonding interface.

[0043] Table 1 below shows each SOI substrate (acceleration energy during ion implantation: 60, 100, 110, 130, 1

40, 160keV) is shown. The Ni concentration in Table 1 is the Ni concentration gettered near the bonding interface.

[0044] [Table 1]

[0045] From the results in Table 1 above, the Ni concentration in the vicinity of the force coupling interface of 60, 100, 110, and 130 keV is higher than when acceleration energy during ion implantation is 140 keV and 160 keV. I understand. In other words, in the ion implantation for forming the high-concentration layer, when the acceleration energy is set to 130 keV or less, a better gettering ability can be added near the bonding interface.

[0046] It should be noted that the higher the acceleration energy at the time of ion implantation, the greater the damage formed in the crystal. Therefore, it is normal to think that the higher the acceleration energy at the time of ion implantation, the higher the gettering ability. . However, looking at the above experimental example, the acceleration energy at the time of ion implantation is lower, and the gettering ability is rather higher.

[0047] Although the details of the reason why the gettering capability near the bonding interface is higher when the acceleration energy during ion implantation is lowered as described above are not clear, the acceleration during ion implantation is not clear. The depth of damage due to low energy ion implantation becomes shallow, and when bonded, the damage layer becomes close to the bonding interface, so that some defect that becomes a gettering site is formed near the bonding interface. Conceivable.

[0048] Hereinafter, the present invention will be described more specifically with reference to Examples and Comparative Examples, but the present invention is not limited thereto.

(Example 1)

Based on the process shown in Fig. 1, an SOI substrate was fabricated as follows.

First, two mirror-polished N-type single crystal silicon substrates with a diameter of 200 mm and a plane orientation of {100} were prepared (see step (a) in Fig. 1).

Next, a silicon oxide film 13 with a film thickness of about 1 μm to be a BOX layer was formed on the surface of the single crystal silicon substrate 12 to be a support substrate by thermal oxidation (see step (b) in FIG. 1). ).

Next, arsenic was ion-implanted under the following conditions on the entire surface of one surface of the single crystal silicon substrate 11 to be the SOI layer, thereby forming a high concentration layer 14 (see step (c) in FIG. 1). That is, the dose amount was 2E15 atoms / cm ² (2 × 10 ¹⁵ atoms / cm ² ), and the acceleration energy was l lOkeV.

[0049] After that, the single crystal silicon substrate 11 serving as the SOI layer and the single crystal silicon substrate serving as the support substrate were adhered to each other with the high-concentration layer 14 and the silicon oxide film 13 sandwiched therebetween (step of FIG. 1). (See (d)).

After that, the active layer side of the bonded wafer 15 was thinned to a thickness of about 12 m by surface grinding or mirror polishing to obtain an SOI substrate 19 (see step (f) in FIG. 1). .

[0050] The gettering ability of the SOI substrate fabricated in this way was evaluated by the same method as in the experimental example (see Table 2 below). However, the contaminating element was Fe. [0051] (Comparative Example 1)

Following the procedure for manufacturing the SOI substrate of Example 1, the SOI substrate was manufactured in the same manner as in Example 1 except that the acceleration energy during ion implantation was 160 keV.

Further, the gettering ability of the SOI substrate manufactured in this way was evaluated by the same method as in Example 1 (see Table 2 below).

The evaluation results of the gettering ability of Example 1 and Comparative Example 1 are shown in Table 2 below.

[0053] [Table 2]

[0054] As shown in Table 2 above, when the acceleration energy at the time of ion implantation is l lOkeV of Example 1, compared with 160 keV of Comparative Example 1, the Fe concentration near the bonding interface is higher. It is powerful to be connected.

That is, it can be seen that a better gettering capability was added in the case of 1 lOkeV, in which the acceleration energy during ion implantation is 130 keV or less.

[0055] In addition, in Example 1, the step of adding gettering capability also serves as the step of forming a high-concentration buried diffusion layer necessary for the structure. Therefore, it is necessary to add a special new step separately. Don't be. For this reason, it can be seen that the SOI substrate can be manufactured efficiently without reducing productivity and increasing the cost.

[0056] Furthermore, in Example 1, it was found that the SOI layer had a thickness of 12 / zm, and Fe gettering was concentrated in a depth region of 10 to 12 m including the bonding interface. Therefore, it can be seen that when a device is fabricated on this SOI substrate, the electrical characteristics of the device region where the active layer, for example, the 1 μm depth region of the surface and the gettering layer do not overlap, may be degraded. I The present invention is not limited to the above embodiment. The above-described embodiment is an example, and has any configuration that is substantially the same as the technical idea described in the claims of the present invention and that exhibits the same operational effects. Are also included in the technical scope of the present invention.

Claims

The scope of the claims

[1] At least a single crystal silicon substrate in which an active impurity arsenic or antimony is introduced to form a high concentration layer and a single crystal silicon substrate in which a high concentration layer is not formed are bonded via a silicon oxide film. In addition, after the bonding heat treatment, the single crystal silicon substrate on which the high-concentration layer is formed is thinned to form arsenic or 1 X 10 ¹⁸ atoms / cm ³ or more on the silicon oxide film. In a method of manufacturing an SOI substrate on which an SOI layer having a high concentration buried diffusion layer containing antimony is formed, the active impurity is introduced by ion implantation with an acceleration energy during ion implantation of 130 keV or less, A method for manufacturing an SOI substrate, wherein the thickness of the SOI layer to be formed is 3 μm or more.

[2] The method for manufacturing an SOI substrate according to [1], wherein an acceleration energy at the time of ion implantation of the active impurity is 30 keV or more.

[3] The method for manufacturing an SOI substrate according to [1] or [2], wherein acceleration energy at the time of ion implantation of the active impurity is set higher than lOOkeV.

[4] The silicon oxide film is formed on the surface of a single crystal silicon substrate on which the high concentration layer is not formed, and is bonded to the single crystal silicon substrate on which the high concentration layer is formed via the silicon oxide film. The method for manufacturing an SOI substrate according to any one of claims 1 to 3, wherein:

[5] The bonding heat treatment is performed at a heat treatment temperature of 1000 ° C to 1300 ° C and a heat treatment time of 0.5 hours to 8 hours. The method for manufacturing an SOI substrate according to claim 1.