JP2004063892A - Soi wafer and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SOI wafer and its manufacturing method by which uniformity of film thickness in a wafer and between wafers is imparted. <P>SOLUTION: After a pattern forming layer 21 is formed on the uppermost layer on a first main surface J of a second substrate 1 made of silicon single crystal, an ion implantation layer 4 for peeling is formed with respect to the second substrate 1. Then, a pattern layer 20 is formed, and according to the pattern, an etch-stopping ion implantation layer 6, whose formation depth position from the first main surface of the second substrate 1 varies, is formed at a position shallower than that of the ion implantation layer 4 for peeling. After the second substrate 1 with two ion implantation layers 4 and 6 formed together is joined with a first substrate 7, a joint silicon single crystal thin film 5 is peeled off from the second substrate 1 by using the ion implantation layer 4 for peeling. Furthermore, the surface layer part of the joint silicon single crystal thin film 5, stuck on the first substrate 7, is etched back upto an etch-stop layer 6' that is formed based on the ion implantation layer 6, through this peeling operation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an SOI wafer and a method for manufacturing the same, and more particularly, to an SOI wafer having a plurality of SOI layers having different thicknesses formed on the surface of a silicon oxide film and a method for manufacturing the same.
[0002]
[Prior art]
Semiconductor devices using SOI (Silicon on Insulator) layers include various types of devices such as MOS-type ICs such as CMOS, high-voltage type ICs, semiconductor memories such as RAMs such as D-RAMs, and system LSIs. Developed and commercialized as electronic components. In order to form such a semiconductor device, a silicon oxide film is formed on a silicon single crystal substrate (hereinafter, also referred to as a base wafer), and another silicon single crystal is stacked thereon as an SOI layer. SOI wafers are used. In the SOI wafer used here, the thickness of the silicon oxide film or the SOI layer is required as appropriate according to the semiconductor device formed thereon, and, for example, changes in gate length, withstand voltage, capacitance, etc. Depending on the required function of a semiconductor device, an SOI layer formed so that the thickness of the SOI layer in the same SOI wafer is different may be required.
[0003]
By the way, recently, even in wireless communication such as a mobile phone, in order to measure the expansion of radio wave resources and the increase in transmission capacity, it is common to handle high-frequency signals of several hundred MHZ or more. Naturally, a semiconductor device using a layer is required to have good high-frequency characteristics. Therefore, when forming such a high-frequency semiconductor device, it is necessary to use a high-resistivity silicon single crystal as a base wafer in an SOI wafer to be used in order to reduce high-frequency loss.
[0004]
In manufacturing the above-described SOI wafer, a typical manufacturing method is a bonding method. In this bonding method, a first substrate serving as a base wafer and a second substrate (hereinafter referred to as a bond wafer) serving as an SOI layer as a device formation region are bonded via a silicon oxide film, and then the bond wafer is bonded. Is reduced to a desired film thickness and thinned to make the bond wafer an SOI layer.
[0005]
Although there are several methods for reducing the thickness of the bond wafer, a smart cut method (trade name) is known as a relatively easy and convenient method for obtaining a uniform film thickness. This is because hydrogen ions are implanted into the bonding surface of the bond wafer (referred to as the first main surface) so that a high-concentration hydrogen layer is formed at a certain depth, and after bonding, the hydrogen-rich layer is applied to the high-concentration hydrogen layer. To peel off the bond wafer.
[0006]
[Problems to be solved by the invention]
However, the above method has the following disadvantages. In the smart cut method, as shown in FIG. 9A, ion implantation is performed on the surface of the SOI layer 8 of the SOI wafer 50 '(reference numeral 7 is a base wafer and reference numeral 2 is a silicon oxide film) obtained after peeling. The damage layer 8a is formed, and the roughness of the peeled surface itself is considerably larger than the mirror surface of a silicon wafer of a normal product level. Conventionally, in order to remove the damaged layer 8a, the surface of the SOI layer 8 after peeling has been flattened by mirror polishing (commonly referred to as touch polishing and used for mechanical chemical polishing) with a small polishing allowance. Has been done. When this method is used, the short-wavelength roughness component of the peeled surface can be relatively easily removed, but non-uniformity of the polishing allowance in the wafer surface is newly added. As a result, as shown in FIG. 9B, a distribution of the thickness t of the obtained SOI layer has a standard deviation σ1 of about 1 to 2 nm in the same wafer. Further, as shown in FIG. 9C, a distribution of about 3 nm or more occurs in the standard deviation value σ2 of the film thickness t (t1, t2, t3) between wafers of the same specification wafer lot.
[0007]
Note that a method of flattening the peeled surface by heat treatment in an inert gas atmosphere is also conceivable. However, since the surface roughness after peeling has considerable unevenness and deep unevenness is likely to be generated partially, 1100 Severe heat treatment conditions of more than several hours at a temperature of 1200 ° C. or more, and more than several hours at a temperature of 1200 ° C. or more, are not practical. In addition, in order to make the finish of the peeled surface as uniform as possible, it is necessary to strictly control processes such as hydrogen ion implantation, which leads to a reduction in manufacturing efficiency and yield.
[0008]
Such a variation in the film thickness is inevitable in view of the current level of the mirror polishing technique, and does not pose a particularly serious problem as long as the film thickness of the SOI layer is not less than 100 nm. However, in recent years, in CMOS-LSIs and the like, which are main applications of SOI wafers, the tendency of miniaturization and high integration of devices has become more and more remarkable. Is no longer surprising. At present, the average thickness required for an ultra-thin SOI layer is much lower than 100 nm, and is several tens of nm (for example, 20 to 50 nm) to about 10 nm in some cases. In this case, the level of non-uniformity of the film thickness as described above reaches 10% to several tens of percent of the target average film thickness, and the functional characteristics of the semiconductor device using the SOI wafer are deteriorated, and the quality variation is increased. Needless to say, this leads directly to a reduction in manufacturing yield. Furthermore, an SOI wafer having such an ultrathin film and an excellent thickness uniformity and having a partially different thickness in the plane of the SOI wafer could not be produced conventionally. .
[0009]
An object of the present invention is to provide an SOI wafer in which SOI layers having different thicknesses are formed on the surface of a silicon oxide film, even when the required thickness level of the SOI layer is extremely small. It is possible to reduce both the uniformity of the film thickness in the inside and the uniformity of the film thickness between the wafers to a sufficiently small level, thereby forming a semiconductor device such as an ultra-fine or highly integrated CMOS-LSI or a system LSI. Even in such a case, an object of the present invention is to provide an SOI wafer capable of improving its functional characteristics and a method of manufacturing an SOI wafer capable of suppressing a variation in quality and improving a manufacturing yield.
[0010]
[Means for Solving the Problems and Functions / Effects]
A method for manufacturing an SOI wafer according to the present invention for solving the above-mentioned problems includes:
A method for manufacturing an SOI wafer in which an SOI layer is formed on a surface of an insulating film so as to have different thicknesses,
An insulating film forming step of forming an insulating film on at least one of the first main surface of the first substrate and the second substrate made of silicon single crystal,
A pattern layer forming step of forming a pattern layer that selectively covers the outermost layer on the first main surface side of the second substrate,
By implanting ions by ion implantation from the first main surface side of the second substrate on the second substrate on which the pattern layer is formed, the first substrate to be an SOI layer as viewed from the first main surface is formed. Etch-stop ions for forming etch-stop ion-implanted layers at different depth positions from the first main surface according to the pattern of the pattern layer at a first depth position separated by the silicon layer portion of An injection layer forming step,
After removing the pattern layer from the second substrate, the second substrate, the first substrate, via the insulating film, a bonding step of bonding the respective first main surfaces,
An etch stop layer forming step of forming the etch stop ion implanted layer as an etch stop layer having a higher oxygen concentration than its surroundings,
In the thickness direction of the second substrate, a portion located on the side opposite to the first silicon layer portion is defined as a second silicon layer, and after the bonding step, at least the etch stop of the second silicon layer is performed. An etching-thinning step of thinning a region in contact with the layer by selective etching based on the oxygen concentration difference;
It is characterized by including.
[0011]
A first feature of the method of the present invention is that an ion implantation layer for etching stop is formed in a second substrate, which is a bond wafer made of silicon single crystal, by an ion implantation method. As shown in the schematic diagram of FIG. 8, the ion implantation layer for etch stop is formed by implanting ions from the first main surface J side of the second substrate 1 on which the pattern layer 20 is formed. Therefore, the ion implantation layer 6 for etch stop to be formed is located at a first depth position across the first silicon layer portion 60 to be an SOI layer when viewed from the first main surface J, and is located at a first depth from the first main surface J. Are formed at different formation depth positions.
[0012]
The formation depth position of the etch stop ion implantation layer can be controlled by appropriately adjusting the ion implantation energy, the thickness of the silicon oxide film, and the thickness of the pattern layer. In addition, the ion implantation layers for etch stop formed at different depth positions are continuously formed in the in-plane direction. In this way, the thickness of the first silicon layer portion to be the SOI layer can be appropriately adjusted as shown in the left and right views of FIGS. 8A and 8B. Here, the right diagrams of FIGS. 8A and 8B show an example in which an SOI wafer including a region having a zero thickness in a part of the SOI layer is manufactured. 8A shows a case where the silicon oxide film 2 and the pattern layer 20 are formed on the first main surface J. FIG. 8B shows a case where the pattern layer 20 is formed on the first main surface J. In this case, the ion implantation is performed in any one of the states.
[0013]
The pattern layer is formed in a predetermined pattern using known photolithography or photoetching. The pattern at this time is reflected on the film thickness pattern of the first silicon layer to be the SOI layer.
[0014]
The etch stop ion-implanted layer formed in the second substrate as described above is then used as an etch stop layer that becomes an oxygen-rich layer having a higher oxygen concentration than its surroundings. Such a high-oxygen-concentration layer in silicon (for example, a silicon oxide layer) has remarkable etching selectivity with respect to an alkaline solution or the like between silicon having a low oxygen concentration, and thus ensures the etching of the bonded silicon single crystal thin film Can be stopped.
[0015]
Since the above-described ion implantation layer for etch stop is formed with reference to the first main surface of the second substrate having good flatness, the ion implantation depth hardly varies. This means that even if a pattern layer or an insulating film is formed on the first main surface, the flatness of the first main surface reflects the flatness of the first main surface. Can hardly occur. Therefore, the resulting etch stop layer has an oxygen concentration profile shape that is steep and has a uniform peak position depth, reflecting the flatness of the first main surface finished by mirror polishing or the like. As a result, by etching back the second silicon layer to the etch stop layer, an SOI layer having an extremely good film thickness distribution can be obtained not only within the wafer but also between the wafers. In addition, it is possible to eliminate the touch polish, which has conventionally been a main cause of the deterioration of the film thickness distribution of the SOI layer, from the process by this etch back, which also greatly contributes to the improvement of the film thickness distribution. Further, since the ion implantation for forming the ion implantation layer for etching stop is performed from the first main surface on the side from which the SOI layer is taken out, the ion implantation depth is small, and the variation is hardly caused. This also contributes to making the obtained oxygen concentration profile shape of the etch stop layer steep and having a uniform peak position depth, and further to making the film thickness distribution of the SOI layer extremely good. As described above, in order to further improve the thickness distribution of the SOI layer, the second substrate is preferably a mirror-polished wafer whose first main surface is a mirror-polished surface. It is suitable in the present invention.
[0016]
In the method for manufacturing an SOI wafer according to the present invention, after the first substrate and the second substrate from which the pattern layer has been removed by etching or the like are bonded together on the first main surfaces via an insulating film, an etch stop is performed. The bonded silicon single crystal thin film which is to be an SOI layer including an etch stop layer formed based on the ion implantation layer for use is reduced in thickness by etching back. That is, the second silicon layer is etched back to the etch stop layer. In this case, the thickness of the second substrate itself may be directly reduced by etching back, but it is advisable to use the following method from the viewpoint of work efficiency and the like.
[0017]
One of them includes a region in contact with an etch stop ion implanted layer or an etch stop layer formed based on the etch stop ion implanted layer after the bonding step and prior to the etching thickness reducing step. A pre-thinning step is performed to reduce the thickness of the second substrate while leaving a portion of the silicon layer. This preliminary thickness reduction step is performed by a method such as mechanical grinding or mechanical chemical polishing using a surface grinder or the like. In this case, the thickness reduction of only the silicon layer of the second silicon layer can be considered. The etching is performed by a method using an etching solution having a higher etching rate than the etching solution used for the etching or a dry etching method having a high etching rate. As a result, by performing this preliminary thickness reduction step, the thickness of the second substrate can be reduced in advance before performing the etching thickness reduction step, and the work efficiency can be increased.
[0018]
As a method of performing the preliminary thickness reduction step, a method applying the principle of the conventional smart cut method can be adopted as one of the effective methods other than the above. First, prior to the bonding step, by implanting ions from the first main surface side of the second substrate, in the ion implantation profile in the depth direction, the second depth deeper than the first depth position described above A stripping ion implantation layer having a concentration peak at a position is formed in advance. Then, after the bonding step, the second substrate is separated at the separation ion-implanted layer. Even by performing such a pre-thinning step, the film thickness of the second substrate can be reduced in advance before the etching-thinning step, and the work efficiency can be increased.
[0019]
When a method applying the principle of the above-described smart cut method is used, the surface of the bonded silicon single crystal thin film serving as the separation surface is once rough as in the conventional smart cut method due to separation in the ion implantation layer for separation. Although it becomes a peeled surface, it is not flattened by touch polishing, but is flattened by etching in an etching thinning step which also serves to reduce the thickness of the bonded silicon single crystal thin film. Therefore, the touch polish is unnecessary even though the conventional smart cut method is used. Further, even if there is some unevenness in the surface roughness of the peeled surface, the history almost disappears by etching, and severe heat treatment conditions are not required at all. Therefore, it is not necessary to strictly control the process of forming the ion-implanted layer for stripping, which contributes to improvement in manufacturing efficiency and yield.
[0020]
Further, the formation of the above-described ion-implanted layer for stripping is desirably performed, for example, in the form shown in the schematic diagram of FIG. FIG. 11A shows an example in which the peeling ion-implanted layer 4 is formed in a state where at least the pattern forming layer 21 to be the pattern layer is formed. The left diagram shows the state where the insulating film 2 is formed, and the right diagram shows the state where the insulating film is not formed. FIG. 11B shows an example in which a pattern layer is formed, first, an etch stop ion implantation layer 6 is formed, and then, in a state where the pattern layer is removed, a separation ion implantation layer 4 is formed. The left diagram shows the state where the insulating film 2 is formed, and the right diagram shows the state where the insulating film is not formed. The reason for forming the separation ion implantation layer in such a form is that, depending on the heating conditions required when forming the pattern formation layer to be a pattern layer, the separation ion implantation layer is formed before the bonding step. This is because there is a case where peeling is performed in an unintended form.
[0021]
By using the method of the present invention, an SOI wafer having an SOI layer having a different thickness formed on the surface of an insulating film as shown in the schematic diagram of FIG. The level of non-uniformity of the thickness of the SOI layer can be reduced more effectively than the conventional one, and the standard deviation of the thickness within the same wafer can be secured to, for example, 0.4 nm or less. . Further, the standard deviation value between wafers having the same specification can be secured to 2 nm or less. As a result, it becomes possible to improve the functional characteristics of the semiconductor device using the SOI wafer to be formed, and to suppress the variation in the quality of the SOI wafer and improve the production yield in the production. Further, even when the SOI layer of the SOI wafer has an ultra-thin film having a maximum thickness of 50 nm or less, or even 20 nm or less, the film thickness variation within the wafer and between wafers can be sufficiently reduced. It can be reduced to a range that can endure. Further, since the film thickness variation can be reduced to the above numerical range, it is possible to significantly improve the functional characteristics of the semiconductor device using the SOI wafer. Note that an SOI layer having a different film thickness here (including a case where the film thickness of some regions is zero as shown in FIG. 10B) is different from that of a SOI layer intentionally having a different film thickness. An SOI layer formed separately and as a result of trying to form a uniform film thickness over the entire surface as in a conventional SOI wafer manufacturing method, an SOI wafer having a partially formed SOI layer formed with a different thickness is formed. Is different from Further, including the present specification, the standard deviation value of the thickness of the SOI layer referred to here is a standard deviation value for each region intentionally formed so that the formed film thickness is the same or an average value thereof. Shall be referred to. That is, using the schematic diagram of FIG. 10, in FIG. 10B, the standard deviation value or the average value of the film thickness of each layer forming the SOI layer is indicated, and in FIG. It indicates the standard deviation of the film thickness of each A region and each B region or the average value thereof.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 1 illustrates a basic embodiment of a method for manufacturing an SOI wafer according to the present invention. First, as shown in step (3), a base wafer 7 as a first substrate and a bond wafer 1 as a second substrate made of a silicon single crystal shown in step (1) are prepared. Here, as shown in step (1), a silicon oxide film 2 as an insulating film is formed on the first main surface J side of the bond wafer 1. The silicon oxide film 2 can be formed by, for example, wet oxidation or dry oxidation, but a method such as CVD (Chemical Vapor Deposition) can also be adopted. The thickness of the silicon oxide film is, for example, about 50 nm or more and about 2 μm or less in consideration of use as an insulating layer of a MOS-FET or the like. In this embodiment, the base wafer 7 (first substrate) is also a silicon single crystal substrate. However, the base wafer 7 (the first substrate) may be formed of an insulating substrate such as a quartz substrate or a sapphire substrate, or a compound semiconductor substrate such as SiC, GaAs, or InP. It is also possible. Further, instead of the silicon oxide film 2, a silicon nitride film, a silicon oxynitride film, or the like can be formed as an insulating film. When an insulating substrate is used for the base wafer 7, the formation of the silicon oxide film 2 may be omitted.
[0023]
Then, as shown in step (1), a pattern forming layer 21 to be a pattern layer 20 described later is formed on the main surface of the silicon oxide film 2 by CVD or the like so as to have a predetermined thickness. Considering that the layer forming the lamination interface with the pattern forming layer 21 is formed of silicon (bond wafer) or silicon oxide (insulating film) such as silicon oxide, For example, it is preferable to use a silicon nitride film. By forming the silicon nitride film as the pattern forming layer 21 by CVD or the like in this manner, its surface can better reflect the good flatness of the first main surface J. Further, when the pattern layer 20 formed based on the pattern forming layer 21 described later is removed, only the pattern layer can be easily and reliably etched away with hot phosphoric acid. Further, as the pattern forming layer 21, a silicon oxide film or a resist film can be used in addition to the silicon nitride film. After the pattern formation layer 21 is formed in this manner, the first main surface J of the bond wafer 1, in this embodiment, the first main surface J on which the silicon oxide film 2 is formed in addition to the pattern formation layer 21, For example, hydrogen ions are implanted by irradiating a hydrogen ion beam to form the ion implantation layer 4 for separation. When the hydrogen concentration profile in the depth direction of the wafer is measured, the peeling ion-implanted layer 4 is formed so that a peak position of the hydrogen concentration is generated at a position of 100 nm or more and 2000 nm or less (second depth position da). Is good. If the first depth position da is less than 100 nm, a combined silicon single crystal thin film 5 (described later) having a sufficient thickness cannot be obtained. If the first depth position da exceeds 2000 nm, it is necessary to increase the energy of the ion implantation apparatus extremely. For example, when the average thickness of the maximum thickness of the SOI layer 15 (step (7)) to be finally obtained is set to about 10 to 50 nm, the separation ion-implanted layer 4 is formed of hydrogen in the depth direction of the wafer. When the concentration profile is measured, a peak position of the hydrogen concentration is generated at a position of 100 to 500 nm (a second depth position da: a depth position from the first main surface J of the bond wafer (second substrate) 1). It is good to form. The ion implantation depth is adjusted by the ion energy (acceleration voltage). For example, when hydrogen ions are used, when the thickness ta of the silicon oxide film is set to 50 nm, the ion implantation depth is set at the second depth position da. It is preferable that the energy of ion implantation for forming the ion implantation layer 4 be adjusted to about 10 kV to 60 keV.
[0024]
Further, in order to perform smooth and smooth peeling, the hydrogen ion implantation amount (dose amount) is set to 2 × 10 5 ¹⁶ Pieces / cm ² ~ 1 × 10 ¹⁷ Pieces / cm ² It is desirable that 2 × 10 ¹⁶ Pieces / cm ² If it is less than 1, normal peeling becomes impossible and 1 × 10 ¹⁷ Pieces / cm ² Exceeding the limit causes an excessive increase in the amount of ion implantation, so that the process is lengthened and it is difficult to avoid a decrease in manufacturing efficiency. Note that as the ions for forming the separation ion-implanted layer with hydrogen ions, one kind selected from the group consisting of hydrogen ions and rare gas (He, Ne, Ar, Kr, and Xe) ions can be used. That is, instead of hydrogen ions, the ion implantation layer 4 for separation may be formed by implanting one kind of ions of these rare gases.
[0025]
Next, as shown in step (2), a pattern layer 20 having a predetermined pattern and a layer thickness, which is the outermost layer, is formed on the first main surface J of the bond wafer 1. The pattern layer 20 can be formed by a patterning process using known photolithography or photoetching. In addition, if the surface of the pattern forming layer 21 is formed to reflect the good flatness of the first main surface J as described above, the pattern layer 20 naturally reflects the flatness. can do.
[0026]
Then, as shown in step (2), for example, a hydrogen ion beam is irradiated from the first main surface J side of the bond wafer 1, that is, in this embodiment, to the respective surfaces of the pattern layer 20 and the silicon oxide film 2. A pattern layer having a concentration peak at each of a first depth position shallower than the second depth position (a depth from the first main surface J similarly to the second depth position). The etch stop ion implantation layer 6 having a different formation depth position from the first main surface J according to the pattern 20 is formed. The difference in the depth at the first depth position and the depth itself for forming the ion implantation layer 6 for etching stop are determined by the thickness of the pattern layer 20, the thickness of the silicon oxide film 2, and the irradiation. It is adjusted by the energy of ions. In this manner, the ion implantation layer 6 for etch stop having various predetermined first depth positions is formed without interruption in the in-plane direction. Further, from the viewpoint of sufficiently securing the formation thickness of the region having the maximum thickness in the finally obtained SOI layer 15, the deepest position at the first depth position is at least 50 nm larger than the second depth position. It is desirable to form it so as to be located in a shallow range. In the present embodiment, the average thickness tc of the region having the maximum thickness in the SOI layer 15 (process {circle around (7)}) to be finally obtained is set to about 10 to 50 nm. It is preferable that the deep position db is formed to be a position of 50 to 300 nm. Note that the ion implantation energy for forming the etch stop ion implantation layer 6 at this depth position db is preferably adjusted to about 5 kV to 40 keV when hydrogen ions are used and ta is set to 50 nm. As described above, since the implantation can be performed at a low energy and shallower than the ion implantation energy at the time of forming the separation ion implantation layer, the variation in the ion implantation depth can be further reduced, and the SOI layer can be further reduced. To improve the film thickness uniformity.
[0027]
The ion implantation amount when forming the etch stop ion implantation layer 6 is 1 × 10 ^Fifteen Pieces / cm ² ~ 4 × 10 ¹⁶ Pieces / cm ² It is better to do. 1 × 10 ^Fifteen Pieces / cm ² If it is less than 5, the formation of an etch stop layer 6 '(step (5)) described later becomes incomplete, and the desired etch stop effect cannot be obtained. Further, the ion implantation amount is 4 × 10 ¹⁶ Pieces / cm ² If the value exceeds the above, undesired peeling of the bond wafer (second substrate) 1 may occur in the ion implantation layer 6 for etch stop. For this reason, it is particularly desirable that the amount of ion implantation when forming the ion implantation layer for etch stop be smaller than the amount of ion implantation when forming the ion implantation layer for stripping.
[0028]
The ion species for forming the etch stop ion implanted layer 6 can be variously selected depending on what method is used to form the etch stop ion implanted layer 6 as an etch stop layer composed of a high oxygen concentration layer. it can. For example, one kind selected from the group consisting of hydrogen ions, rare gas (He, Ne, Ar, Kr, Xe) ions and silicon ions can be used. These ion species mainly serve to form crystal defects (damage) in the bond wafer (second substrate) 1 for capturing oxygen. That is, it has the same function as gettering.
[0029]
In this way, the ion implantation layer 4 for peeling and the ion implantation layer 6 for etch stop are formed in the bond wafer 1. Also, as shown in FIG. 1, when the separation ion implantation layer 4 is first formed in a state where the pattern formation layer 21 is formed, when the separation ion implantation layer is formed, for example, the pattern formation layer 21 is formed. Even if surface contamination due to the attachment of foreign matter or the like to the surface or surface roughness occurs, the pattern layer 20 is finally removed together with the removal. As a result, it is possible to satisfactorily bond the bond wafer and the base wafer to be described later.
[0030]
The bond wafer 1 and the base wafer 7 on which the stripping ion implantation layer 4 and the etch stop ion implantation layer 6 are formed as described above, after removing the pattern layer 20 from the bond wafer 1 by, for example, etching, and then using a cleaning liquid. Washed in. Next, as shown in step (3), the two wafers 1 and 7 are bonded together on the side where the silicon oxide film 2 is formed (that is, on the first main surfaces J and K sides). Then, as shown in step (4), the laminate is heat-treated at a low temperature of 400 to 600 ° C., so that the bond wafer 1 is peeled at a concentration peak position of the above-described peeling ion-implanted layer 4, The portion remaining on the base wafer 1 side becomes the bonded silicon single crystal thin film 5 (preliminary thickness reduction step). On the other hand, since the ion implantation amount of the etch stop ion implantation layer 6 is kept low, the etching implantation ion implantation layer 6 does not peel off due to the heat treatment. In some cases, the peeling heat treatment can be omitted by increasing the ion implantation amount when forming the peeling ion-implanted layer 4 or by activating the surface by performing a plasma treatment on the surfaces to be overlapped in advance. . Further, the remaining bond wafer portion 3 after peeling can be reused as a bond wafer or a base wafer again after re-polishing the peeled surface.
[0031]
Next, as shown in step (5), an etch stop layer 6 'having a higher oxygen concentration than the surrounding portion is formed in the bonded silicon single crystal thin film 5 based on the above-described ion implantation layer 6 for etch stop. (Etch stop layer forming step). In the present embodiment, from the surface of the bonded silicon single crystal thin film 5, that is, from the surface on the second silicon layer 61 side in the thickness direction of the bond wafer (second substrate), toward the ion implantation layer for etch stop. By performing an oxygen diffusion step of diffusing oxygen, a kind of internal oxidation treatment for forming an etch stop layer 6 'by increasing the oxygen concentration of the ion implantation layer 6 for etch stop is performed. According to this method, a certain concentration of crystal defects (damage) is formed in a concentrated manner in the form of the etch stop ion implanted layer 6 by ion implantation with hydrogen ions or the like, so that oxygen diffused from the wafer surface is subjected to the etch. The etch stop layer 6 'can be easily formed as a high oxygen concentration layer by being captured by crystal defects formed in the stop ion implantation layer 6.
[0032]
In the etch stop layer forming step by the above method, the oxygen diffusion step can be specifically performed by a heat treatment in an oxygen-containing atmosphere. As the oxygen-containing atmosphere, for example, an oxygen gas atmosphere, an oxygen mixed gas in which oxygen is mixed with nitrogen or argon, and a gas atmosphere composed of a gas (for example, water vapor) composed of a compound molecule containing an oxygen atom can be adopted.
[0033]
As the heat treatment temperature becomes higher, the diffusion rate of oxygen increases, and the formation of the etch stop layer 6 'can be promoted. However, if the heat treatment temperature is too high, crystal defects (for example, Oxygen-induced Stacking Fault) in the etch stop ion implanted layer 6 grow and penetrate the etch stop layer 6 ′ to form the SOI. There is a possibility of reaching the first silicon layer portion 60 to be a layer. In consideration of these points, the heat treatment temperature for oxygen diffusion is desirably set to 700 ° C. or more and 1000 ° C. or less.
[0034]
Note that a damaged layer 8d due to ion implantation is formed on the bonded silicon single crystal thin film 5 immediately after the separation, as shown in FIG. When the heat treatment temperature for oxygen diffusion is set to a relatively high temperature as described above, the above-described crystal defects are likely to grow from the damaged layer 8d, and the problem of penetrating the SOI layer may be more likely to occur. Therefore, if the outermost layer portion of the bonded silicon single crystal thin film 5 is removed by etching prior to the oxygen diffusion step, such a problem is less likely to occur. The etching allowance dc in this case may be such that the damage layer 8d can be removed, and it is appropriate to set it to, for example, about 0.1 to 0.15 μm. Specifically, the etching can be performed by using a mixed acid etching such as hydrofluoric acid / nitric acid, a chemical etching such as an alkali etching such as KOH or NaOH, or a gas phase etching such as an ion etching.
[0035]
In the present embodiment, the conventional touch polish for removing the damaged layer 8d is not performed. As a result, there is no fear that the thickness distribution of the bonded silicon single crystal thin film 5 after peeling is significantly impaired by touch polishing. Accordingly, it can be said that the etching allowance for removing the damaged layer 8d can be easily secured.
[0036]
The oxygen diffusion heat treatment may be performed alone, but may also be used for another purpose. For example, in order to obtain a final SOI wafer, in the present embodiment, a bonding heat treatment for firmly bonding the bonded silicon single crystal thin film 5 and the base wafer 7 via the silicon oxide film after peeling is required. . Since this bonding heat treatment is usually performed at a high temperature of 1000 ° C. or more and 1300 ° C. or less, it can be used also for oxygen diffusion heat treatment. However, as described above, crystal defects in the ion implantation layer 6 for etch stop are removed. From the viewpoint of growth or prevention of broadening of the resulting etch stop layer 6 ', it can be said that it is desirable to set the temperature of the oxygen diffusion heat treatment somewhat lower than this. For example, prior to the bonding heat treatment, a surface protection oxidation heat treatment (700 ° C. or more and 1000 ° C. or less) of the bonded silicon single crystal thin film, which is performed at a lower temperature, is advantageous in that it is also used for oxygen diffusion heat treatment. . At this time, as shown in step (5), a protective oxide film 5a is formed on the surface of the bonded silicon single crystal thin film.
[0037]
Further, the etch stop layer 6 ′ is formed as a high-oxygen concentration layer, but is finally removed and does not require a high insulating property like the silicon oxide film 2. Therefore, the formation thickness tb of the etch stop layer 6 '((6) in FIG. 1) is set so that the difference in the formation film thickness of the SOI layer is a predetermined value and the range in which the etch stop layer is formed without interruption in the in-plane direction. In this case, any thickness may be used as long as it can sufficiently fulfill the etching stop function. Therefore, when only this etching stop function is considered, it is desirable that the formed thickness of the etch stop layer is, for example, 2 nm or more and 50 nm or less. If the formed thickness is less than 2 nm, the etching stop function may be insufficient. If the formed thickness exceeds 50 nm, the oxygen diffusion treatment tends to be lengthened. When the thickness is in this range, the difference in the thickness of the SOI layer that can be provided also corresponds to this range.
[0038]
The etch stop layer 6 ′ must be able to reliably stop the etching from progressing to the underlying silicon layer to be finally left as the SOI layer 15. For example, as shown in {circle around (1)} in FIG. 2, foreign matter such as particles P is present on the surface on the first main surface J of the bond wafer 1 on the ion implantation side when forming the ion implantation layer 6 for etch stop. If it is attached, ion implantation is hindered in the attachment area, and a large number of pinholes 6h are generated in the obtained etch stop layer, from which the etchant may penetrate and the underlying silicon layer may be affected. In this case, as shown in (2), the step of implanting ions into the first main surface J of the bond wafer (second substrate) 1 and the step of cleaning the surface on the first main surface J are alternately repeated. The method is effective. That is, if ion implantation is repeatedly performed while removing foreign matter such as particles P by cleaning, the possibility that the particles P will re-attach to exactly the same position on the wafer surface after cleaning is extremely small, so that the pinhole 6 is removed. Can be greatly reduced.
[0039]
Returning to FIG. 1, if the etch stop layer 6 'is thus formed, as shown in step (6), the oxide film 5a is removed with hydrofluoric acid, and then the etch stop 6 of the combined silicon single crystal film 5 is formed. The thickness of the combined silicon single crystal thin film 5 is reduced by performing selective etching based on the oxygen concentration difference in a portion closer to the surface layer than ', that is, at least a region of the second silicon layer 61 which is in contact with the etch stop layer 6'. . As the etchant, an alkaline solution, for example, an aqueous solution such as NaOH, KOH, or TMAH (Tetramethylammonium Hydroxide) can be used.
[0040]
The etch stop layer 6 'is formed based on the etch stop ion implantation layer 6 as described above. The etch stop ion implanted layer 6 is formed based on the first main surface J of the bond wafer (second substrate) 1 having good flatness before the bonded silicon single crystal thin film 5 is peeled off. Is formed at a position shallower than the ion-implanted layer 4 for stripping, and therefore, the ion implantation depth hardly varies. Therefore, the etch stop layer 6 ′ has a steep oxygen concentration profile shape reflecting the flatness of the main surface of the substrate finished by mirror polishing or the like and in which the variation of the peak position depth is effectively suppressed. . As a result, it is possible to obtain the SOI layer 15 having an extremely good film thickness distribution not only within the wafer but also between the wafers corresponding to the oxygen concentration profile shape. Specifically, even though the average thickness tc of the region having the maximum thickness in the SOI layer 15 is set to an ultrathin film of about 10 to 50 nm, the uniformity of the thickness of the SOI layer 15 can be improved by the same wafer. For example, 0.4 nm or less can be secured by the standard deviation of the film thickness in FIG. 5, and as shown in FIG. 5, the standard deviation σ2 of the film thickness t (= t1, t2, t3) between wafers of the same specification is 2 nm. The following can be secured. In particular, even when the thickness of the region where the maximum thickness of the SOI layer 15 is extremely thinned to 50 nm or less, or even to 20 nm or less (for example, 10 nm), the variation in the film thickness within the wafer and between the wafers is sufficiently practical. It can be reduced to a range that can endure.
[0041]
After the etching-thinning step by the selective etching, the etch stop layer 6 'remaining on the SOI layer 15 is removed by etching as shown in step (7), whereby the SOI wafer 50 is obtained. The etch stop layer 6 'is a high oxygen concentration layer, for example, a silicon oxide layer, and can be easily removed by etching using hydrofluoric acid. When the SOI layer has a form as shown in FIG. 10B, the etch stop layer 6 'may be in contact with the silicon oxide film 2 in such a case. Then, the etch stop layer 6 'may be removed.
[0042]
After the etching-thinning step (after removing the etch stop layer 6 '), a planarizing heat treatment for further planarizing the surface of the SOI layer 15 can be performed. This flattening heat treatment can be performed in an inert gas such as an argon gas, a hydrogen gas, or a mixed gas thereof at a temperature of about 1100 to 1200 ° C. for a short time of about 1 to 2 hours. Can also be performed. Specifically, it can be performed using a heat treatment furnace of a heater type such as a general batch type vertical furnace or a horizontal furnace, and a single-wafer type heat treatment that completes the heat treatment in several seconds to several minutes by lamp heating or the like. It can also be performed using an RTP device.
[0043]
The SOI wafer manufactured by the above steps has SOI layers having different thicknesses in the plane and has excellent uniformity in film thickness. When a device is manufactured using such an SOI wafer, it is easy to mix SOI layers having different thicknesses in one chip, which can be used for diversification of manufactured devices.
[0044]
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to this, A various deformation | transformation or improvement can be added unless it deviates from the technical range based on description of a claim. . For example, a silicon oxide film may be formed only on the first main surface of the base wafer. Also, a silicon oxide film can be formed on the bonding surfaces (first main surfaces J and K) of both the base wafer and the bond wafer.
[0045]
In the step of forming the ion implantation layer for etch stop, the ion implantation layer for etching stop may be formed in the bonded silicon single crystal thin film using oxygen ions. FIG. 7 shows an example of the process. Step (1) is the same as FIG. Then, in step (2), an ion implantation layer 62 for etch stop is formed using oxygen ions. The etch stop ion implantation layer 62 is preferably formed so that a peak position of the oxygen concentration occurs at a position (depth position db) of 50 nm or more and 500 nm or less. The ion implantation amount is 1 × 10 ^Fifteen Pieces / cm ² ~ 4 × 10 ¹⁷ Pieces / cm ² It is better to do.
[0046]
According to this method, there is an advantage that the ion implantation layer 62 for etch stop can be formed as a high oxygen concentration layer from the beginning by oxygen ion implantation. However, in order to strengthen the chemical bond between silicon and oxygen and obtain an etch stop layer having good selective etching properties, it is desirable to perform heat treatment on the bond wafer including the ion implantation layer 62 for etch stop. This heat treatment temperature is preferably in the range of 900 to 1300 ° C. At 900 ° C. or less, the effect of improving the selective etching property is small, and when it exceeds 1300 ° C., problems of metal contamination and slip dislocation occur. For example, as shown in step (5), the heat treatment can be performed alone at 900 to 1000 ° C. similarly to the oxygen diffusion heat treatment of FIG. At this time, the heat treatment atmosphere may be an inert gas (Ar) atmosphere, or an oxygen diffusion treatment using an oxygen atmosphere (so-called oxygen) in order to further enrich oxygen in the ion implantation layer 60 for etching stop. (This is additional diffusion processing). On the other hand, the above-mentioned heat treatment may be combined with the bonding heat treatment or the above-mentioned surface protection oxidation heat treatment performed at a lower temperature prior to the bonding heat treatment. In this case, the oxygen diffusion heat treatment shown in step (5) may be omitted in FIG. Steps 6 and thereafter are the same as those in FIG.
[0047]
Further, in order to increase the crystal defect density for capturing oxygen ions, as shown in FIG. 12, a preliminary ion-implanted layer 66 is formed by using one kind selected from the group consisting of hydrogen ions, rare gas ions, and silicon. Furthermore, the ion implantation layer 6 for etch stop can be formed by implanting oxygen ions into the preliminary ion implantation layer 66. Thereafter, an oxygen diffusion treatment may be further performed.
[0048]
Furthermore, in the step of forming the ion implantation layer for etch stop, the ion implantation layer for etching stop may be formed in the bonded silicon single crystal thin film using germanium ions. The etch stop ion implanted layer becomes a silicon-germanium layer and can immediately function as an etch stop layer to the silicon layer for a particular etchant. As an etchant for selectively etching the silicon layer with respect to the silicon-germanium layer, KOH and K ₂ CrO ₇ A suitable solution is a mixed solution of phenol and propanol (references; Applied Physics Letters, 56 (1990) 373-375). Further, the etch stop layer made of a silicon-germanium layer can be removed by using an etching solution for selectively etching SiGe with respect to Si, and specifically, HF and H ₂ O ₂ And CH ₃ A mixed solution with COOH can be used (Reference: Journal of Electrochemical Society, 138 (1991) 202-204). It is also possible to perform selective etching using dry etching.
[0049]
In FIG. 1, the stripping ion implantation layer 4 is formed in the step (1), and then the etch stop ion implantation layer 6 is formed in the step (2). Of course, they can be replaced, and an example is shown in FIG. First, in step (1), after forming a pattern forming layer, a pattern layer 20 is formed. Then, first, the ion implantation layer 6 for etch stop is formed. Next, in step (2), after removing the pattern layer 20 by etching or the like, the ion implantation layer 4 for separation is formed. Subsequent steps (3) and thereafter are the same as those in FIG.
[0050]
Further, the mode of forming the ion implantation layer for stripping and the ion implantation layer for etch stop can also be performed as follows. As shown in FIG. 14, in step (1), after forming a pattern forming layer, a pattern layer 20 is formed. Then, an ion implantation layer 6 for etch stop is formed. Thereafter, subsequently, the ion implantation layer 4 for separation is formed. At this time, the separation ion implantation layer 4 also has different formation depth positions from the first main surface J according to the pattern of the pattern layer 20, and the difference between the formation depth positions, that is, If the difference between the desired film thicknesses required for the SOI layer (tb in FIG. 1) is sufficiently small, such as 50 nm or less (for example, 20 to 50 nm), the bond wafer (second substrate) 1 has no problem. Can be separated in the ion-implanted layer 4 for separation. In the case of adopting such a formation mode, the separation ion implantation layer and the etch stop ion implantation layer can be continuously formed, so that the working efficiency can be improved. In the description here, the process of forming the ion implantation layer 6 for etching and then forming the ion implantation layer 4 for stripping is performed, but of course, the order of formation may be reversed.
After forming the etch stop ion implanted layer 6 and the stripping ion implanted layer 4 in the step (1), the steps after the step (2) are the same as the steps after the step (3) in FIG. .
[0051]
In the embodiment described with reference to FIGS. 1 and 7 and the like, the separation ion implantation layer is formed and the separation step is performed using the separation ion implantation layer. Another embodiment having no peeling step will be described below.
[0052]
FIG. 4 illustrates an embodiment of a manufacturing method according to the present invention that does not include a peeling step. First, in step (1), an ion implantation layer 6 for etch stop is formed. However, here, the pattern layer 20 is formed in the following form. First, a silicon oxide film or a known resist film is formed on the first main surface J of the bond wafer 1 as a pattern layer forming layer. Then, the silicon oxide film or the resist film is subjected to patterning processing using photolithography so as to have a predetermined pattern, thereby forming the pattern layer 20. As described above, the working efficiency can be improved by forming the pattern layer 20 directly on the silicon surface (the surface of the bond wafer 1) using a silicon oxide film or a resist film in particular. Next, in step (2), after the pattern layer 20 is removed by etching or the like, an oxygen diffusion step of diffusing oxygen toward the ion implantation layer 6 for etching stop is performed, whereby the ion implantation layer for etching stop is formed. 6 to form an etch stop layer 6 '(etch stop layer forming step). In this step (2), the layer region 5a is formed together with the etch stop layer 6 '. Here, the layer region 5a is a silicon oxide film. Then, the bond wafer 1 on which the etch stop layer 6 'has been formed and the base wafer 7 are cleaned with a cleaning liquid. Next, as shown in step (3), the two wafers 1 and 7 are bonded together on the formation side (that is, the first main surface J and K side) of the layer region 5a which is a substitute layer for the silicon oxide film. A bonding heat treatment is performed at 800 ° C to 1250 ° C. Next, as shown in step (4), the thickness of the bond wafer (second substrate) 1 is reduced while leaving a part of the second silicon layer 61 including a region in contact with the etch stop layer 6 '(preliminary reduction). Thick process). Specifically, the bond wafer 1 is mechanically ground using, for example, a plane grinder, and the silicon wafer 61 ′ for etching is left on the etch stop layer 6 ′ by about 0.1 to 10 μm. Grind. Thus, a silicon single crystal thin film 5 having a thickness similar to that of the bonded silicon single crystal thin film 5 of FIG. 1 is obtained. Thereafter, as shown in step (5), the silicon layer 61 'is etched back to the position of the etching stop layer 6' by selective etching (etching reduction step). This etching thinning step is the same as the step (6) in FIG. 1, and the subsequent steps are also the same.
[0053]
In the embodiment described with reference to FIG. 4, the bonding and bonding heat treatment in step (3) was performed after the oxygen diffusion heat treatment in step (2). ', The bonding and bonding heat treatments in step (3) are performed without performing the oxygen diffusion heat treatment, and a preliminary thickness reduction step by grinding or the like in step (4) is performed, and then the same as step (2). May be performed. In this case, the heat treatment of the oxygen diffusion heat treatment can also serve as the bonding heat treatment. Further, the bonding heat treatment may be performed simultaneously with the heat treatment of the planarization heat treatment performed after the step (6).
[0054]
If the etch stop ion implanted layer 6 can be formed using oxygen ions and can be a layer having a sufficient oxygen concentration, the oxygen diffusion heat treatment in step (2) can be omitted. Of course, an oxygen diffusion heat treatment may be performed to further increase the oxygen concentration. In this case, the heat treatment may be performed in an inert gas atmosphere such as argon. When such a heat treatment is performed, the bonding heat treatment in the step (3) also serves as the heat treatment.
[0055]
Next, the step of reducing the thickness of the bond wafer (second substrate) 1 can also be performed by the well-known ELTRAN (trade name) method disclosed in, for example, Japanese Patent No. 2608351. FIG. 6 shows an example thereof. First, as shown in step (1), after a porous silicon layer 31 is formed on the first main surface side of the bond wafer 1 by a well-known anodizing treatment, a silicon epitaxial layer to be an SOI layer is formed on the porous silicon layer 31. Layer 37 is vapor grown. Further, a pattern layer is formed using a silicon oxide film or the like on the first main surface on the bonding surface side of the epitaxial layer 37, and ions are implanted from the first main surface side, so that an ion implantation layer for etch stop is formed. To form Then, after the pattern layer is removed, an etch stop layer 6 'is formed by oxygen diffusion heat treatment. Then, on the first main surface of the silicon epitaxial layer 37, a bonding heat treatment for the base wafer 7 is performed. Next, as shown in step (2), a portion of the bond wafer 1 located above the porous silicon layer 31 is removed by grinding or the like, or a fluid is sprayed on the porous layer to be separated. Then, as shown in step (3), the remaining porous silicon layer 31 and the portion of the silicon epitaxial layer 37 above the etch stop layer 6 'are selectively etched. The subsequent steps (4) and (5) are the same as steps (6) and (7) in FIG. Even in the case of using the ELTRAN method, the oxygen diffusion heat treatment for forming the etch stop layer 6 ′ can be performed after the bonding heat treatment, with only the porous silicon layer removed and the silicon epitaxial layer 37 exposed. .
[Brief description of the drawings]
FIG. 1 is a process explanatory view showing one embodiment of a method for manufacturing an SOI wafer according to the present invention.
FIG. 2 is a view for explaining the influence of particles on the formation of an etch stop layer, together with a countermeasure method.
FIG. 3 is a diagram schematically showing an example of removing a damaged layer after a peeling step.
FIG. 4 is a process explanatory view showing one embodiment of a method for manufacturing an SOI wafer according to the present invention.
FIG. 5 is an explanatory diagram of an effect of the present invention.
FIG. 6 is a process explanatory view showing one embodiment of a method for manufacturing an SOI wafer according to the present invention.
FIG. 7 is a process explanatory view showing one embodiment of a method for manufacturing an SOI wafer according to the present invention.
FIG. 8 is a schematic view for explaining the manufacturing method of the present invention.
FIG. 9 is a diagram showing a problem of a conventional method relating to the manufacture of an SOI wafer.
FIG. 10 is a schematic diagram for explaining an SOI wafer targeted by the present invention.
FIG. 11 is a schematic diagram for explaining the manufacturing method of the present invention.
FIG. 12 is a process explanatory view showing a modification of the process for forming an ion implantation layer for etch stop.
FIG. 13 is a process explanatory view showing one embodiment of a method for manufacturing an SOI wafer according to the present invention.
FIG. 14 is a process explanatory view showing one embodiment of a method for manufacturing an SOI wafer according to the present invention.
[Explanation of symbols]
1 Bond wafer (second substrate)
2 Insulating film
7 Base wafer (first substrate)
4 Removal ion implantation layer
5 Bonded silicon single crystal thin film
6 Ion implantation layer for etch stop
6 'etch stop layer
15 SOI layer
20 pattern layers
50 SOI wafers
60 First silicon layer part
61 Second silicon layer

Claims (18)

A method for manufacturing an SOI wafer in which an SOI layer is formed on a surface of an insulating film so as to have different thicknesses,
An insulating film forming step of forming an insulating film on at least one of the first main surface of the first substrate and the second substrate made of silicon single crystal,
A pattern layer forming step of forming a pattern layer that selectively covers the outermost layer on the first main surface side of the second substrate,
By implanting ions by ion implantation from the first main surface side of the second substrate on the second substrate on which the pattern layer is formed, the first substrate to be an SOI layer as viewed from the first main surface is formed. Etch-stop ions for forming etch-stop ion-implanted layers at different depth positions from the first main surface according to the pattern of the pattern layer at a first depth position separated by the silicon layer portion of An injection layer forming step,
After removing the pattern layer from the second substrate, the second substrate, the first substrate, via the insulating film, a bonding step of bonding the respective first main surfaces,
An etch stop layer forming step of forming the etch stop ion implanted layer as an etch stop layer having a higher oxygen concentration than its surroundings,
In the thickness direction of the second substrate, a portion located on the side opposite to the first silicon layer portion is defined as a second silicon layer, and after the bonding step, at least the etch stop of the second silicon layer is performed. An etching thickness reducing step of reducing the thickness by selectively etching a region in contact with the layer based on a difference in oxygen concentration. After the bonding step, prior to the etching-thickening step, including a region in contact with the etch stop layer formed based on the etch stop ion implantation layer or the etch stop ion implantation layer, the second 2. The method for manufacturing an SOI wafer according to claim 1, wherein a preliminary thickness reduction step of reducing the thickness of the second substrate is performed while leaving a part of the silicon layer. As the preliminary thickness reduction step, prior to the bonding step, by implanting ions from the first main surface side of the second substrate, in the ion implantation profile in the depth direction, compared to the first depth position. Forming a peeling ion implantation layer having a concentration peak at a deep second depth position,
3. The method for manufacturing an SOI wafer according to claim 2, further comprising, after the bonding step, a step of peeling the second substrate at the ion implantation layer for peeling. 4. The method for manufacturing an SOI wafer according to claim 3, wherein the ion implantation amount at the time of forming the etch stop ion implantation layer is smaller than the ion implantation amount at the time of forming the stripping ion implantation layer. . 5. The method for manufacturing an SOI wafer according to claim 3, wherein ions for forming the ion implantation layer for separation are at least one selected from the group consisting of hydrogen ions and rare gas ions. 6. The method according to claim 1, wherein at least one selected from the group consisting of hydrogen ions, rare gas ions, and silicon ions is used as ions for forming the ion implantation layer for etch stop. 3. The method for producing an SOI wafer according to 1. The etch stop layer forming step includes, after the preliminary thickness reducing step, performing an oxygen diffusion step of diffusing oxygen from the surface on the second silicon layer side toward the etch stop ion implanted layer. 7. The method for manufacturing an SOI wafer according to claim 2, wherein the oxygen concentration of the stop ion implantation layer is increased to form the etch stop layer. 8. The method for manufacturing an SOI wafer according to claim 7, wherein said oxygen diffusion step is performed by a heat treatment in an oxygen atmosphere in said etch stop layer forming step. 6. The method for manufacturing an SOI wafer according to claim 1, wherein oxygen ions are used as ions for forming the ion implantation layer for etch stop. Forming a preliminary ion-implanted layer using at least one selected from the group consisting of hydrogen ions, rare gas ions, and silicon ions, and further implanting the oxygen ions into the preliminary ion-implanted layer to form the etch stop ions; The method for producing an SOI wafer according to claim 9, wherein the method is an injection layer. 11. The SOI wafer according to claim 9, wherein in the etch stop layer forming step, the second substrate including the etch stop ion implantation layer formed using the oxygen ions is heat-treated. Method. 12. The method for manufacturing an SOI wafer according to claim 1, wherein, after the etching thickness reducing step, an etch stop layer remaining on the SOI layer is removed by etching. 13. The method of manufacturing an SOI wafer according to claim 12, wherein after the removal of the etch stop layer, a planarization heat treatment for further planarizing the surface of the SOI layer is performed. 14. The method for manufacturing an SOI wafer according to claim 1, wherein the insulating film is a silicon oxide film. The method for manufacturing an SOI wafer according to claim 1, wherein the first substrate is a silicon single crystal substrate. 16. The method for manufacturing an SOI wafer according to claim 1, wherein the pattern layer is a silicon nitride film. An SOI wafer formed by the manufacturing method according to any one of claims 1 to 16,
The SOI wafer, wherein the SOI wafer has SOI layers having different formed film thicknesses in a plane, and the thickness of the layer having the largest formed film thickness is 50 nm or less. 18. The film thickness uniformity of the SOI layer is set to 0.4 nm or less as a standard deviation value within the same wafer, and set to 2 nm or less as a standard deviation value between wafers having the same specification. The described SOI wafer.

Images