WO2003046992A1

WO2003046992A1 - Soi wafer manufacturing method

Info

Publication number: WO2003046992A1
Application number: PCT/JP2002/011166
Authority: WO
Inventors: Kiyoshi Mitani
Original assignee: Shin-Etsu Handotai Co.,Ltd.
Priority date: 2001-11-29
Filing date: 2002-10-28
Publication date: 2003-06-05
Also published as: JP2003168789A

Abstract

A second Si layer (23), a first SiGe layer (22), and a first Si layer (21) are formed as a multilayer epitaxial layer in this order on a bond wafer (2). A hydrogen high-concentration layer is formed in the second Si layer (23) by hydrogen ion implantation, and a bonding heat treatment and separation are conducted. A multilayer body, as an epitaxial layer to be separated, comprising the first Si layer (21), the first SiGe layer (22), and the separated second Si layer (23) is formed in one bonded piece on a silicon oxide layer (3). The thus separated second Si layer (23) is selectively etched by using the first SiGe layer (22a) as an etch stop layer. Thus, an SOI wafer can be manufactured such that both the film thickness uniformity of a wafer and that of wafers can be reduced to a sufficiently low level even if the required film thickness level of the SOI layer is very low.

Description

Specification

S O I ゥ Yuha manufacturing method

The present invention relates to a method for manufacturing an SOI wafer. Background art

In mobile communications such as mobile phones, it is common to handle high-frequency signals of several hundred MHz or higher, and semiconductor devices with good high-frequency characteristics are required. For example, a semiconductor device such as a CMOS IC or a high withstand voltage IC has a silicon oxide film insulator layer formed on a silicon single crystal substrate (hereinafter also referred to as a base wafer), and another silicon single crystal is formed thereon. So-called SOI wafers, in which layers are stacked as SOI (silicon on insulator) layers, are used. When this is used for high-frequency semiconductor devices, it is necessary to use a high-resistivity silicon single crystal as a base wafer to reduce high-frequency loss.

By the way, there is a bonding method as a typical manufacturing method of SII IHA. In this bonding method, a first silicon single crystal substrate serving as a base wafer is bonded to a second silicon single crystal substrate (hereinafter also referred to as a bond wafer) serving as an SOI layer serving as a device formation region via a silicon oxide film. Then, the bond wafer is reduced to a desired film thickness and thinned to make the bond wafer an SOI layer. The following smart cut method (trade name) is well known as a method for reducing the thickness of bondue. This is because hydrogen or a rare gas is ion-implanted so that an ion-implanted layer (microbubble layer) is formed at a fixed depth position with respect to the bonding surface (referred to as the first main surface) of Bondueha. After the alignment, the bond injection It peels off.

However, the conventional smart cut method described above has the following disadvantages. In other words, the SOI wafer obtained after peeling has a damage layer formed by ion implantation on the surface of the SOI layer, and the roughness of the peeled surface itself is larger than the mirror surface of the Si wafer at the product level. Become. Conventionally, in order to remove this damaged layer, the surface of the SOI layer after peeling has been required to be mirror-finished by mirror polishing with a small polishing allowance (commonly referred to as “touch ball polishing” and using mechanical and chemical polishing). Has been done. When this method is used, the resulting thickness distribution of the SOI layer is about 1.5 to 2 nm with a standard deviation value σ1 within the same range. In addition, a distribution of about 3 nm or more occurs in the standard deviation of the film thickness and the standard σ2 between the aehs of the aha lots of the same specification.

Such a variation in film thickness is inevitable in view of the current level of mirror polishing technology, and becomes a particularly serious problem as long as the thickness of the SOI layer is not more than about 100 nm. Not something. However, in recent years, the trend of miniaturization and high integration of elements in CMOS-LSIs, etc., which are the main applications of SOI wafers, has become more and more remarkable. What used to be called ultra-thin was no longer surprising. At present, the average thickness required for ultra-thin SOI layers is well below 100 nm, ranging from a few 10 nm (for example, 20 to 50 nm) to about 10 nm in some cases. . In this case, the level of non-uniformity of the film thickness as described above reaches 10% to several 10% of the target average film thickness, resulting in quality variation of semiconductor devices using SOI wafers and reduction in manufacturing yield. Needless to say, they are directly connected.

An object of the present invention is to reduce both the film thickness uniformity within a wafer and the film thickness uniformity between wafers to a sufficiently small level even when the required film thickness level of the SOI layer is very small. It is possible to suppress quality variation and improve manufacturing yield even when processing into ultra-fine or highly integrated CMOS LSIs. It is an object of the present invention to provide a method of manufacturing an SOI wafer. Disclosure of the invention

In order to solve the above problems, a method for producing an SOI wafer of the present invention comprises:

Second silicon (corresponding to Bondueha) single crystal substrate first major surface of each _{_{S i X G e! _ Χ}} ( However, 0≤ χ≤ 1) a unit layer consisting of, between the adjacent unit layers An epitaxy growth step of forming a multilayer epitaxy layer laminated so that the crystal ratio X is different from each other;

Of the unit layers forming the multilayer epitaxy layer, the unit layer located at least one side on the substrate side or the inside of the second silicon single crystal substrate as viewed from the unit layer forming the outermost layer portion as a region to be peeled off, Implanting at least one of hydrogen ions or rare gas ions from the outermost surface to form an ion implanted layer in the region to be stripped;

An outermost surface of the multilayer epitaxial layer formed on the second silicon single crystal substrate, and a first main surface of a first silicon single crystal substrate (corresponding to a base wafer) prepared separately from the second silicon single crystal substrate An insulating film is formed on at least one of the above, and the multilayer epitaxy layer and the second silicon single crystal substrate are coupled via the insulating film, and in the ion injection layer, the ion injection layer of the multilayer epitaxy layer is formed. A portion located on the insulating film side (hereinafter, referred to as an epitaxial layer portion to be peeled) is bonded to the first silicon single crystal substrate and is separated from the remaining portion on the second silicon single crystal substrate. A peeling step;

While leaving one or more unit layers, including those located in contact with the insulating layer, of the separated epitaxial layer portion bonded to the first silicon single crystal substrate via the insulating layer, An etching step of selectively etching one or more unit layers located on the release surface side based on the difference in Ge content, It is characterized by including. Note that "SO I layer" herein consists not limited to the literal concept of "silicon layer on the insulating _{_{_{layer", S i x G ei _ x}}} (0≤ x≤ 1) The case where the unit layer is formed on the insulating layer is also included in the concept of the SOI layer.

In the above-mentioned method of the present invention, the so-called smart cut method, in which the SOI layer is separated by an ion implantation layer formed by ion implantation in order to reduce the thickness of the second silicon single crystal substrate to the SOI layer, Is adopted. At this time, S i _x G _eix (However, 0≤ χ≤ 1) unit layer consisting of the, as a multilayer Epitakisharu layers stacked as mixed crystal ratio X of adjacent ones are different from each other, the second It is formed on a silicon single crystal substrate. In this multilayer epitaxial layer, ions are implanted with hydrogen or the like from the outermost surface side with the unit layer or substrate located deeper than the part to be left as the SOI layer (that is, on the substrate side) as the region to be peeled. Thereby, an ion implantation layer is formed in the region to be separated. In this state, when the multilayer epitaxial layer of the second silicon single crystal substrate is bonded to the first silicon single crystal substrate via the insulating layer and peeled off by the ion implantation layer, the first silicon single crystal substrate becomes The portion of the multilayer epitaxial layer located on the insulating layer side with respect to the ion-implanted layer, that is, the portion of the separated epitaxial layer to be the SOI layer is bonded via the insulating layer.

A damaged layer is formed on the peeled surface of the peeled epitaxy layer portion by implantation of hydrogen ions or the like. According to the present invention, one or more layers located on the peeling surface side of the portion of the epitaxial layer to be peeled are selectively etched based on the difference in Ge content. Removed without. Then, since the unit layer left after the selective etching is used as the SOI layer, the thickness of the SOI layer is not required as much as that of the contact hole, so that the SOI layer having a very good film thickness distribution not only within the wafer but also between the wafers can be obtained. Obtainable.

Selective etching should be performed so that only the uppermost layer on the release surface side is removed. Alternatively, the selective etching may be sequentially repeated for two or more unit layers. The latter is effective in further improving the film thickness uniformity.

According to the method of the present invention, since the thickness uniformity of the obtained SOI layer depends on the thickness uniformity of the epitaxial layer, the standard deviation of the film thickness within the same wafer is, for example, 0.4 nm. The following can be secured. In addition, it is possible to secure the standard deviation between ゥ and ゥ of the same specifications to 2 nm or less. As a result, even when the thickness of the SOI layer is reduced to 20 nm or less, it is possible to reduce the variation in the film thickness within the wafer and between the wafers to a range that can sufficiently withstand practical use.

The present invention is applicable, for example, when forming a SOI layer composed of a single Si layer. In this case, the stripped epitaxial layer portion is composed of at least two layers of the first Si layer and the first Si Ge layer from the insulating layer side, and the etching step etches the first Si layer. As the stop layer, a step of selectively etching the first SiGe layer is included. By leaving the first Si layer as the SOI layer, an SOI layer composed of a single Si layer can be easily obtained. For example, in a case where only the first SiGe layer is selectively etched in the etching step, a peeled surface based on the ion-implanted layer may be formed in the first SiGe layer. On the other hand, when the selective etching is sequentially repeated for two or more layers, if necessary, an additional Si layer or SiGe layer is laminated after the first SiGe layer, and the first selection is performed. The above peeling is performed in the region where the etching is to be performed.

—On the other hand, the SOI layer may be formed by a heterojunction between the Si layer and the SiGe layer. In this case, there are two cases: a case where the Si layer is located on the insulating layer side (first embodiment) and a converse case, that is, a case where the Si Ge layer is located (second embodiment).

For example, the layer to be peeled is composed of the first S i layer, the first S i _X Ge (where 0≤ x <1) layer and the second S layer stacked in this order from the insulating layer side. It can be composed of at least three layers of i-layer. In this case, the etching process It is the first S i _X G e layer as an etch stop layer, comprising the step of selecting Etsu quenching the second S i layer. When the step of selectively etching the second Si layer is completed, the SOI layer of the first embodiment including a heterojunction of the Si layer and the SiGe layer is obtained. the i layer when selecting etching the first S i _X G e layer as an etch stop layer, it is possible to obtain an SOI layer consisting of the first S i layer. In the latter case, the film thickness uniformity can be further improved by repeating the selective etching at least twice. The peeled surface based on the ion-implanted layer may be located in the second Si layer formed in the multilayer epitaxial layer or in the surface layer to be the second Si layer of the second Si single crystal substrate. Can be formed. That is, the second Si layer may be included in the multilayer epitaxial layer, or the ion implantation layer is formed in the second silicon single crystal substrate, and the second silicon layer is formed in the ion implantation layer. The release Si layer obtained by removing a part of the crystal substrate may be any.

The SOI layer according to the second embodiment, which is composed of a heterojunction of a Si layer and a SiGe layer, can be suitably used for manufacturing a high-speed n-channel MOS transistor using a strained Si layer having a tensile strain. . In order to obtain such an SOI layer, the first layer, the first Si layer, and the second S The iGe layer is formed of at least three layers. In this case, the etching step includes a step of selectively etching the second Si Ge layer using the first Si layer as an etch stop layer. Then, by leaving the first Si layer and the first SiGe layer as SOI layers, an SOI layer having a SiSiGe heterojunction structure can be easily obtained. For example, in the case where only the selective etching of the second SiGe layer is performed in the etching step, a peeled surface based on the ion-implanted layer may be formed in the second SiGe layer. On the other hand, when selective etching is sequentially repeated for two or more layers, an additional Si layer or SiGe layer is stacked after the second SiGe layer, and the area where the first selective etching is performed is performed. Performing the above peeling in ₍ Brief description of the drawings

FIG. 1 is an explanatory view of a manufacturing process of an SOI wafer according to the present invention.

FIG. 2A is a first diagram showing the relationship between the thickness of the multilayer epitaxial layer and the formation depth of the high hydrogen concentration layer in FIG.

Figure 2B is also the second figure.

FIG. 3 is a view showing a first modification of the manufacturing process of the SOI wafer according to the present invention.

FIG. 4 is a process explanatory view showing a second modified example. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best mode for carrying out the present invention will be described.

FIG. 1 schematically illustrates a method for manufacturing an SOI wafer according to the present invention. First, a base wafer 1 as a first silicon single crystal substrate shown in the step (a) and a bondue 2 as a second silicon single crystal substrate shown in the step (b) are prepared. In the embodiment of FIG. 1, a silicon oxide film 3 as an insulating film is formed on the first main surface 1a of the base wafer 1, as shown in step (a). This silicon oxide film 3 can be formed by, for example, wet oxidation, but it is also possible to adopt a method such as CVD (Chemical Vapor Deposition). The thickness tx of the silicon oxide film is a known value, for example, about 0.05 to 2 / im. Note that, as the insulating film, a sapphire thin film or a diamond thin film can be used instead of the silicon oxide film 3.

On the other hand, as shown in step (c), the bond epitaxial layer 2 has a multilayer epitaxial layer in which the first Si layer 22 and the first Si layer 21 are alternately stacked in this order. Is done. The growth of the Si layer 21 is performed by using a well-known CVD The growth of the 310 layer 22 can be performed by a CVD method using silane and germane. Although FIG. 1 shows an example in which the silicon oxide film 3 is formed only on the base wafer 1, if the oxide film is as thin as 10 to several 10 nm, the Si layer 2 on the bond wafer 2 may be used. A silicon oxide film can also be formed on the surface of (1). In other words, oxidization at a high temperature of 1,000 ° C or more, which is usually performed, is not preferable because the composition of the SiGe layer changes, but if the thickness is limited to a small film thickness, the oxidation temperature can be sufficiently lowered. There is no need to worry. If the oxide film thickness is insufficient, an oxide film may be formed on the base wafer and the oxide films may be bonded together. As described above, if an oxide film is formed even slightly on the surface of the Si layer 21, the bonding interface and the SOI layer can be separated from each other, and SOI such as contamination and interface states that easily occur at the bonding interface can be formed. Adverse effects on the stratum can be eliminated.

Next, a high-concentration hydrogen layer (ion-implanted layer) 4 is formed in the bond wafer 2 by, for example, implanting hydrogen ions from the outermost surface of the multilayer epitaxial layer by ion implantation. The SOI layer to be finally obtained is constituted by the first Si layer 21.

Further, in order to perform a smooth peel smoothly, injection of hydrogen ions (dose) of 1 X 1 0 ¹⁶ pieces Zcm ² ~: IX 1 0 ¹⁷ atoms cm ^2, and it is desirable to. Injection volume of hydrogen I O emissions becomes impossible normal peeling is less than 1 X 1 0 ¹⁶ atoms ^{/ cm 2, 1 X 1 0} 17 or Z cm ² by weight, the process for ion implantation amount is excessively increased in length As time goes on, it will be unavoidable that production efficiency will decrease.

Next, after cleaning the main surfaces of the base wafer 1 and the bond wafer 2 with a cleaning liquid, as shown in the step (e), they are superposed on the side where the silicon oxide film 3 is formed. By applying a degree of heat treatment, the layer can be peeled off at the hydrogen-rich layer 4 (step (f)). Thereafter, a bonding heat treatment for increasing the bonding strength is performed as necessary. This bonding heat treatment is desirably performed in the range of about 800 to 1 000 ° C. New If the temperature is lower than 800 ° C, the bonding strength is insufficient, and if the temperature is higher than 1000 ° C, the Ge concentration profile at the interface between the Si layer 21 and the Si Ge layer 22 which form a multi-layer epitaxial layer. However, the steepness is lost due to the diffusion, leading to a problem that the surface of the SOI layer after the selective etching is roughened or the thickness distribution of the SOI layer is deteriorated. Note that only the bonding heat treatment may be performed, and the peeling heat treatment may be omitted.

As shown in the step (f), the multi-layered epitaxial layer of Bondue 182 is peeled at the above-mentioned concentration peak position of the high-concentration hydrogen layer 4, and the portion of the epitaxial layer to be peeled, ie, the silicon oxide film From the three sides, the first Si layer 21, the first Si Ge layer 22, and the Si layer composed of a part of the peeled bondue wafer 2 (corresponding to the second Si layer: hereafter, peeling The stacked body in the order of 23 is bonded and integrated via the silicon oxide film 3 on the base wafer 1.

At this time, a damage layer due to ion implantation is formed on the outermost surface of the peeled Si layer 23, but in the present embodiment, a conventional touch-polishing for removing the damage layer is not performed. This is because the damaged layer can be chemically removed during the selective etching described later. By the selective etching, an extremely good JI distribution of the SOI layer is formed, but it can be said that it is preferable to avoid performing a touch-bolishing which worsens this. However, this does not hinder the polishing if the polishing allowance is sufficiently smaller than the etching allowance during the selective etching. Next, as shown in step (g), the exfoliated Si layer 23 is selectively etched. In this selective etching, etching stops near the interface between the exfoliated Si layer 23 and the first Si Ge layer 22 using an etching solution having different etching rates for Si and Si Ge. I will do it. At this time, S i G e etch ing solution for selectively etching the S i with respect to (hereinafter, referred to as a first type etching solution) as the, KOH and K ₂ and C r ₂ 〇 ₇ and flop propanol A mixed solution is suitable (references; Applied Physics Letters, 56 (1990), 373-375). Subsequently, as shown in (h), the SiGe layer 22 As a result, the remaining first Si layer 21 becomes the SOI layer 7. By forming the SOI layer 7 by using such selective etching, compared with the conventional method of reducing the thickness of the SOI layer mainly by using touch varnish, not only within the wafer but also between the wafers Also, an SOI layer having an extremely good film thickness distribution can be obtained. In addition, a layer damaged by hydrogen ion implantation for stripping the SOI layer can be removed without any problem by this etching. Specifically, as shown in FIG. 2A, the uniformity of the obtained film thickness t of the SOI layer 7 is secured to, for example, 0.4 nm or less at the standard deviation σ1 of the film thickness in the same wafer. As shown in Fig. 2B, the standard deviation σ2 of the film thickness t (= t1, t2, t3) between wafers of the same specification can be secured to 2 nm or less. In particular, even when the SOI layer 7 is ultra-thin to 20 nm or less (for example, 10 nm), it is possible to reduce the variation in film thickness within and between wafers to a range that can sufficiently withstand practical use. Become.

As a simpler method, the SOI layer 7 composed of the first Si layer 21 can be obtained by one selective etching. Figure 3 shows an example. That is, as shown in (a), a first SiGe layer 22 and a first Si layer 21 are formed in this order as a multi-layer epitaxy layer on Bondueha 2 and the multi-layer epitaxy is formed. By implanting hydrogen ions from the outermost surface of the metal layer, a high concentration layer of water and dX is formed in the first SiGe layer 22, and the bonding heat treatment and peeling are performed as shown in (b). Then, as shown in (c), the first Si layer 21 and the peeled first Si Ge layer 22 a are formed on the silicon oxide film 3 as an epitaxial layer to be peeled. The laminate consisting of is bonded and integrated.

As shown in (d), the exfoliated first Si layer 22 a is removed from the epitaxial layer portion so that the etching stops near the interface with the first Si layer 21. Selective etching. HF, H ₂ O _2, and CH ₃ COO are used as an etching solution (hereinafter referred to as a second type etching solution) for selectively etching Si Ge with respect to Si. A mixed solution with H is suitable (Reference: Journal of Electrochemical Society, 138 (1991) 202-204). In addition, as an etching method at this time, it is also possible to perform selective etching using dry etching in addition to wet etching. Thereby, the SOI layer 7 of the first Si layer 21 is obtained.

Further, by applying the above method, an SOI layer formed by a heterojunction between the Si layer and the SiGe layer can be obtained. In this case, as shown in FIG. 4, the epitaxial layer to be peeled is divided into the first Si layer 22, the first Si layer 21, and the first layer 21 stacked in this order from the insulating layer 3 side. The second S i Ge layer 24 is formed as at least three layers. The etching step includes at least a step of selectively etching the second Si Ge layer 24 using the first Si layer 21 as an etch stop layer. By leaving the first Si layer 21 and the first Si Ge layer 22 as SOI layers, the first Si Ge layer 22 on the insulating layer 3 side is formed. An SOI layer 7 having an i / SiGe heterojunction structure can be easily obtained. The first Si layer 21 becomes a strain Si and can be suitably used for a high-speed η-channel MOS transistor or the like. In this embodiment, as shown in step (a) of FIG. 4, a second Si layer is further laminated on the second Si Ge layer 24 in the portion of the epitaxial layer to be peeled. It is formed in shape. Here, the second Si layer 2 is formed by a method similar to that of FIG. 1, that is, by forming an ion implantation layer 4 on the surface layer of the bond wafer 2 and peeling off the ion implantation layer 4 after bonding. 3 is formed as a peeled Si layer from the bond 2. Then, the second Si layer 23 is selectively etched as shown in step (b), and the second Si layer 23 is further selectively etched as shown in step (c). As a result, an SOI layer 7 having a Si / SiGe heterojunction structure is obtained. On the other hand, when only the selective etching of the second SiGe layer is performed in the etching step, a peeled surface based on the ion-implanted layer may be formed in the second SiGe layer 24. Further, selective etching using the first Si layer 21 in FIG. 4C as an etch stop layer and the first Si layer 21 as an etch stop layer. , The Si layer may be epitaxially grown on the Si Ge layer 22 again. In this case, if the first Si layer 21 in FIG. 4 (c) is reconsidered as a newly grown Si layer, the finally obtained laminated structure is similar. The Si layer newly formed by this epitaxial growth can be used as a more suitable strained Si layer.

Claims

The scope of the claims

1. On the first main surface of the second silicon single crystal substrate, a unit layer consisting of S _x Ge (where 0 ≤ ≤ ≤ 1) is formed, and the mixed crystal ratios X of adjacent unit layers are different from each other. An epitaxy growth step of forming a multilayer epitaxy layer which is laminated as described above, and, among the unit layers forming the multilayer epitaxy layer, a unit layer or the unit layer located at least one more on the substrate side when viewed from the unit layer forming the outermost layer part. An ion-implanted layer is formed in the separation target region by implanting at least one of hydrogen ions and a rare gas ion from the outermost surface side of the multilayer epitaxial layer with the inside of the second silicon single crystal substrate as a separation target region. An ion implantation layer forming step,

At least one of an outermost surface of the multilayer epitaxial layer formed on the second silicon single crystal substrate, and a first main surface of a first silicon single crystal substrate prepared separately from the second silicon single crystal substrate. Forming an insulating film on the crab, coupling the multilayer epitaxial layer and the second silicon single crystal substrate through the insulating film, and further comprising, in the ion-implanted layer, the ion-implanted layer of the multilayer epitaxy layer. A portion located on the insulating film side (hereinafter referred to as an epitaxial layer portion to be peeled) is peeled off from the remaining portion on the second silicon single crystal substrate side in a state of being bonded to the first silicon single crystal substrate. Bonding and peeling process

While leaving one or more unit layers, including those located in contact with the insulating layer, of the separated epitaxial layer portion bonded to the first silicon single crystal substrate via the insulating layer as an SOI layer, An etching step of selectively etching at least one layer located on the release surface side based on the difference in the Ge content,

A method for producing an SOI wafer.

2. The thickness uniformity of the SOI layer is set to 0.4 nm or less in the standard deviation of the film thickness in the same wafer, and is set to 2 nm or less in the standard deviation between the wafers of the same specification ^ S. This 2. The method for manufacturing a SOI device according to claim 1, wherein:

3. The multilayer Epitakisharu layer 5 one layer and 3 06 ₁ _ ₃₄ (however, 0≤ x <1) layer and the claim 1, wherein, wherein those that are alternately stacked, or Item 2. The method for producing SO I @ Yuha according to Item 2.

4. The peeled Epitakisharu layer portion, the first S i layer Ru are stacked from the insulating layer side in this order, the first S i _X G e (However, 0≤x <1) layer and the second Consists of at least three layers of the Si layer of

The etching step, said first S i _X G e layer as Etchisu top layer, of the second billed ranging third term, wherein a is intended to include the step of selecting Etsuchingu the S i layer SOI ゥ eha manufacturing method.

5. The second Si layer in which the release surface based on the ion-implanted layer is formed in the multilayer epitaxial layer, or the surface layer portion to be the second Si layer of the second Si single crystal substrate 5. The method for producing a SOI II niha according to claim 4, wherein the SOI niha is formed therein.

6. The object to be peeled Epitakisharu layer portion, the insulating layer side of the first S i layer and the first _{_{S i X G e! _ Χ}} ( However, 0≤ χ <1) from at least two layers of layer becomes, the etching step, the first S i layer as an etch stop layer, to claim 3, characterized in that it comprises the first S i _X G e Bok layer a step of selective etching The manufacturing method of the described SO I @ Yuha.

7. a manufacturing method of the SO I Ueha ion implantation layer separation plane based on is formed on the first S i _x G ei χ layer described range 6 preceding claims, characterized in Rukoto.

8. The method for manufacturing an SOI wafer according to claim 4, wherein the first Si layer is left as the SOI layer.

9. The peeled epitaxial layer portion includes a first S i _x G e! _ _Χ (0≤χ <1) layer and a first S i layer laminated in this order from the insulating layer side. And the second S i _X G e _x consists of at least three layers,

The SOI according to claim 3, wherein the etching step includes a step of selectively etching the second Si _x Ge using the first Si layer as an etch stop layer.ゥ Manufacturing method of eha.

10. After selecting etching the second S i _X G e bets, after once dividing removed by the first S i layer by selective etching of the first S i _x Ge i layer and the etch stop layer 10. The method for manufacturing an SOI wafer according to claim 9, wherein a 3i layer is epitaxially grown on the first S13 ₍ 06 layer).