WO2003046992A1 - Procede de production d'une tranche de soi - Google Patents

Procede de production d'une tranche de soi Download PDF

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Publication number
WO2003046992A1
WO2003046992A1 PCT/JP2002/011166 JP0211166W WO03046992A1 WO 2003046992 A1 WO2003046992 A1 WO 2003046992A1 JP 0211166 W JP0211166 W JP 0211166W WO 03046992 A1 WO03046992 A1 WO 03046992A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
soi
single crystal
crystal substrate
silicon single
Prior art date
Application number
PCT/JP2002/011166
Other languages
English (en)
Japanese (ja)
Inventor
Kiyoshi Mitani
Original Assignee
Shin-Etsu Handotai Co.,Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co.,Ltd. filed Critical Shin-Etsu Handotai Co.,Ltd.
Publication of WO2003046992A1 publication Critical patent/WO2003046992A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • An object of the present invention is to reduce both the film thickness uniformity within a wafer and the film thickness uniformity between wafers to a sufficiently small level even when the required film thickness level of the SOI layer is very small. It is possible to suppress quality variation and improve manufacturing yield even when processing into ultra-fine or highly integrated CMOS LSIs. It is an object of the present invention to provide a method of manufacturing an SOI wafer. Disclosure of the invention
  • a method for producing an SOI wafer of the present invention comprises:

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

Selon l'invention, une seconde de couche Si (23), une première couche de SiGe (22) et une première couche de Si (21) sont formées de façon à constituer un stratifié épitaxial, dans cet ordre, sur une tranche (2) à souder. Une couche à haute concentration d'hydrogène est formée dans la seconde couche de Si (23) par implantation d'ions d'hydrogène, et un traitement thermique de liaison et une séparation sont effectués. Un corps stratifié, formant une couche épitaxiale à séparer, comprenant la première couche de Si (21), la première couche de SiGe (22) et la seconde couche de Si (23) séparées est formé de façon à constituer une seule pièce liée sur une couche d'oxyde de silicium (3). La seconde couche de Si (23) ainsi séparée est attaquée de façon sélective, la première couche de SiGe (22a) servant de couche d'arrêt d'attaque. Ainsi, une tranche de SOI peut être produite de sorte qu'à la fois l'uniformité d'épaisseur du film d'une tranche et celle de tranches peuvent être réduites à une valeur suffisamment basse, même si l'épaisseur de film requise pour la couche SOI est d'une valeur très basse.
PCT/JP2002/011166 2001-11-29 2002-10-28 Procede de production d'une tranche de soi WO2003046992A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-364907 2001-11-29
JP2001364907A JP2003168789A (ja) 2001-11-29 2001-11-29 Ｓｏｉウェーハの製造方法

Publications (1)

Publication Number Publication Date
WO2003046992A1 true WO2003046992A1 (fr) 2003-06-05

Family

ID=19175028

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/011166 WO2003046992A1 (fr) 2001-11-29 2002-10-28 Procede de production d'une tranche de soi

Country Status (2)

Country Link
JP (1) JP2003168789A (fr)
WO (1) WO2003046992A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006043471A1 (fr) * 2004-10-20 2006-04-27 Shin-Etsu Handotai Co., Ltd. Procede de fabrication de tranches semiconductrices
WO2006051730A1 (fr) * 2004-11-10 2006-05-18 Shin-Etsu Handotai Co., Ltd. Procédé de fabrication de plaquette semi-conductrice

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6852652B1 (en) * 2003-09-29 2005-02-08 Sharp Laboratories Of America, Inc. Method of making relaxed silicon-germanium on glass via layer transfer
FR2860340B1 (fr) * 2003-09-30 2006-01-27 Soitec Silicon On Insulator Collage indirect avec disparition de la couche de collage
US7265030B2 (en) * 2004-07-20 2007-09-04 Sharp Laboratories Of America, Inc. Method of fabricating silicon on glass via layer transfer
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
WO2006077216A2 (fr) * 2005-01-19 2006-07-27 S.O.I.Tec Silicon On Insulator Technologies Formation et traitement d'une structure en sige
JP5128761B2 (ja) * 2005-05-19 2013-01-23 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
EP2498280B1 (fr) * 2011-03-11 2020-04-29 Soitec DRAM avec des condensateurs en tranchée et transistors logiques à polarisation de substrat intégrés sur un substrat SOI comprenant une couche semiconductrice intrinsèque et procédé de fabrication correspondant

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991005366A1 (fr) * 1989-09-29 1991-04-18 The Government Of The United States Of America, As Represented By The Secretary Of The Department Of The Navy Procede de fabrication d'une couche mince de silicium sur isolateur
EP0843344A1 (fr) * 1996-11-15 1998-05-20 Canon Kabushiki Kaisha Procédé de transfert d'une couche semiconductrice par l'utilisation de la technologie silicium sur isolant (SOI)
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP2001217430A (ja) * 1999-11-26 2001-08-10 Toshiba Corp 半導体基板の製造方法およびこれにより製造された半導体基板
JP2001284558A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 積層半導体基板及びその製造方法並びに半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991005366A1 (fr) * 1989-09-29 1991-04-18 The Government Of The United States Of America, As Represented By The Secretary Of The Department Of The Navy Procede de fabrication d'une couche mince de silicium sur isolateur
EP0843344A1 (fr) * 1996-11-15 1998-05-20 Canon Kabushiki Kaisha Procédé de transfert d'une couche semiconductrice par l'utilisation de la technologie silicium sur isolant (SOI)
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP2001217430A (ja) * 1999-11-26 2001-08-10 Toshiba Corp 半導体基板の製造方法およびこれにより製造された半導体基板
JP2001284558A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 積層半導体基板及びその製造方法並びに半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006043471A1 (fr) * 2004-10-20 2006-04-27 Shin-Etsu Handotai Co., Ltd. Procede de fabrication de tranches semiconductrices
JP2006120782A (ja) * 2004-10-20 2006-05-11 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
JP4617820B2 (ja) * 2004-10-20 2011-01-26 信越半導体株式会社 半導体ウェーハの製造方法
WO2006051730A1 (fr) * 2004-11-10 2006-05-18 Shin-Etsu Handotai Co., Ltd. Procédé de fabrication de plaquette semi-conductrice
JP2006140187A (ja) * 2004-11-10 2006-06-01 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
US7959731B2 (en) 2004-11-10 2011-06-14 Shin-Etsu Handotai Co., Ltd. Method for producing semiconductor wafer

Also Published As

Publication number Publication date
JP2003168789A (ja) 2003-06-13

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