FR2880988B1 - TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE - Google Patents

TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE

Info

Publication number
FR2880988B1
FR2880988B1 FR0500524A FR0500524A FR2880988B1 FR 2880988 B1 FR2880988 B1 FR 2880988B1 FR 0500524 A FR0500524 A FR 0500524A FR 0500524 A FR0500524 A FR 0500524A FR 2880988 B1 FR2880988 B1 FR 2880988B1
Authority
FR
France
Prior art keywords
ygey
treatment
taken
layer
ygey taken
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0500524A
Other languages
English (en)
Other versions
FR2880988A1 (fr
Inventor
Nicolas Daval
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0500524A priority Critical patent/FR2880988B1/fr
Priority to US11/145,482 priority patent/US7232737B2/en
Priority to EP06703581A priority patent/EP1839332A2/fr
Priority to KR1020077016429A priority patent/KR20070090251A/ko
Priority to JP2007551665A priority patent/JP4975642B2/ja
Priority to PCT/EP2006/050261 priority patent/WO2006077216A2/fr
Priority to CN2006800081591A priority patent/CN101142669B/zh
Priority to TW095101822A priority patent/TWI307935B/zh
Publication of FR2880988A1 publication Critical patent/FR2880988A1/fr
Application granted granted Critical
Publication of FR2880988B1 publication Critical patent/FR2880988B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
FR0500524A 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE Expired - Fee Related FR2880988B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0500524A FR2880988B1 (fr) 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
US11/145,482 US7232737B2 (en) 2005-01-19 2005-06-02 Treatment of a removed layer of silicon-germanium
KR1020077016429A KR20070090251A (ko) 2005-01-19 2006-01-17 ＳｉＧｅ 구조체 제조 및 처리방법
JP2007551665A JP4975642B2 (ja) 2005-01-19 2006-01-17 ＳｉＧｅ構造の形成および処理
EP06703581A EP1839332A2 (fr) 2005-01-19 2006-01-17 Formation et traitement d'une structure en sige
PCT/EP2006/050261 WO2006077216A2 (fr) 2005-01-19 2006-01-17 Formation et traitement d'une structure en sige
CN2006800081591A CN101142669B (zh) 2005-01-19 2006-01-17 SiGe结构的形成和处理
TW095101822A TWI307935B (en) 2005-01-19 2006-01-18 Treatment of a removed layer of si1-ygey

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0500524A FR2880988B1 (fr) 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE

Publications (2)

Publication Number Publication Date
FR2880988A1 FR2880988A1 (fr) 2006-07-21
FR2880988B1 true FR2880988B1 (fr) 2007-03-30

Family

ID=34979043

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0500524A Expired - Fee Related FR2880988B1 (fr) 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE

Country Status (5)

Country Link
US (1) US7232737B2 (fr)
JP (1) JP4975642B2 (fr)
CN (1) CN101142669B (fr)
FR (1) FR2880988B1 (fr)
TW (1) TWI307935B (fr)

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US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
US7863157B2 (en) * 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
FR2912258B1 (fr) * 2007-02-01 2009-05-08 Soitec Silicon On Insulator "procede de fabrication d'un substrat du type silicium sur isolant"
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
KR100873299B1 (ko) * 2007-08-20 2008-12-11 주식회사 실트론 Ｓｓｏｉ 기판의 제조방법
JP5528347B2 (ja) * 2007-10-31 2014-06-25 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング 伝動ベルトのリング部品及びそのための製造方法
JP2010135538A (ja) * 2008-12-04 2010-06-17 Sumco Corp 貼り合わせウェーハの製造方法
US8703521B2 (en) 2009-06-09 2014-04-22 International Business Machines Corporation Multijunction photovoltaic cell fabrication
US8802477B2 (en) * 2009-06-09 2014-08-12 International Business Machines Corporation Heterojunction III-V photovoltaic cell fabrication
FR2957190B1 (fr) * 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
CN102347267B (zh) * 2011-10-24 2013-06-19 中国科学院上海微系统与信息技术研究所 一种利用超晶格结构材料制备的高质量sgoi及其制备方法
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
CN103165511B (zh) * 2011-12-14 2015-07-22 中国科学院上海微系统与信息技术研究所 一种制备goi的方法
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation
US9058990B1 (en) 2013-12-19 2015-06-16 International Business Machines Corporation Controlled spalling of group III nitrides containing an embedded spall releasing plane
US9870940B2 (en) 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates
FR3048548B1 (fr) * 2016-03-02 2018-03-02 Soitec Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant

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US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
EP0849788B1 (fr) 1996-12-18 2004-03-10 Canon Kabushiki Kaisha Procédé de fabrication d'un article semiconducteur utilisant un substrat ayant une couche d'un semiconducteur poreux
US5906951A (en) 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5882987A (en) 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP3762221B2 (ja) 1998-04-10 2006-04-05 マサチューセッツ・インスティテュート・オブ・テクノロジー シリコンゲルマニウムエッチング停止層システム
JP3697106B2 (ja) 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
US6297147B1 (en) * 1998-06-05 2001-10-02 Applied Materials, Inc. Plasma treatment for ex-situ contact fill
JP3951487B2 (ja) * 1998-12-25 2007-08-01 信越半導体株式会社 Ｓｏｉ基板及びその製造方法
US6352942B1 (en) 1999-06-25 2002-03-05 Massachusetts Institute Of Technology Oxidation of silicon on germanium
FR2797174B1 (fr) 1999-08-04 2001-12-07 Micro Mega Sa Procede d'obturation canalaire et dispositif de mise a disposition du produit d'obturation
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
US6602613B1 (en) * 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6660606B2 (en) 2000-09-29 2003-12-09 Canon Kabushiki Kaisha Semiconductor-on-insulator annealing method
JP2002164520A (ja) 2000-11-27 2002-06-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
WO2002082514A1 (fr) 2001-04-04 2002-10-17 Massachusetts Institute Of Technology Procede de fabrication d'un dispositif semi-conducteur
JP2002305293A (ja) 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
JP2003031495A (ja) 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
JP2003168789A (ja) * 2001-11-29 2003-06-13 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
FR2834123B1 (fr) * 2001-12-21 2005-02-04 Soitec Silicon On Insulator Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report
AU2003237399A1 (en) * 2002-06-03 2003-12-19 Tien-Hsi Lee Methods for transferring a layer onto a substrate
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
FR2842349B1 (fr) * 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US7008857B2 (en) * 2002-08-26 2006-03-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
FR2846786B1 (fr) 2002-11-05 2005-06-17 Procede de recuit thermique rapide de tranches a couronne
CN100483666C (zh) * 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 施主晶片以及重复利用晶片的方法和剥离有用层的方法
US6995427B2 (en) * 2003-01-29 2006-02-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same
JP4853990B2 (ja) * 2003-01-29 2012-01-11 ソイテック 絶縁体上に歪み結晶層を製造する方法、前記方法による半導体構造及び製造された半導体構造
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
FR2852143B1 (fr) 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
KR20060030911A (ko) * 2003-07-29 2006-04-11 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 공동-임플란트 및 열적 아닐링에 의한 개선된 품질의 박층제조방법
FR2858462B1 (fr) 2003-07-29 2005-12-09 Soitec Silicon On Insulator Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer

Also Published As

Publication number Publication date
JP2008527752A (ja) 2008-07-24
JP4975642B2 (ja) 2012-07-11
TWI307935B (en) 2009-03-21
US20060160328A1 (en) 2006-07-20
CN101142669A (zh) 2008-03-12
FR2880988A1 (fr) 2006-07-21
TW200639969A (en) 2006-11-16
US7232737B2 (en) 2007-06-19
CN101142669B (zh) 2010-08-18

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20150930