FR2852143B1 - Procede de traitement preventif de la couronne d'une tranche multicouche - Google Patents

Procede de traitement preventif de la couronne d'une tranche multicouche

Info

Publication number
FR2852143B1
FR2852143B1 FR0302623A FR0302623A FR2852143B1 FR 2852143 B1 FR2852143 B1 FR 2852143B1 FR 0302623 A FR0302623 A FR 0302623A FR 0302623 A FR0302623 A FR 0302623A FR 2852143 B1 FR2852143 B1 FR 2852143B1
Authority
FR
France
Prior art keywords
crown
preventive treatment
multilayer slice
slice
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0302623A
Other languages
English (en)
Other versions
FR2852143A1 (fr
Inventor
Eric Neyret
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0302623A priority Critical patent/FR2852143B1/fr
Priority to US10/784,040 priority patent/US6939783B2/en
Priority to KR1020057016240A priority patent/KR100806981B1/ko
Priority to JP2006506406A priority patent/JP4855245B2/ja
Priority to PCT/IB2004/000940 priority patent/WO2004079801A1/fr
Priority to EP04715980A priority patent/EP1599896B1/fr
Priority to CNB2004800059654A priority patent/CN100490070C/zh
Priority to TW093105459A priority patent/TWI297176B/zh
Publication of FR2852143A1 publication Critical patent/FR2852143A1/fr
Priority to US11/157,956 priority patent/US7190029B2/en
Application granted granted Critical
Publication of FR2852143B1 publication Critical patent/FR2852143B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
FR0302623A 2003-03-04 2003-03-04 Procede de traitement preventif de la couronne d'une tranche multicouche Expired - Lifetime FR2852143B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR0302623A FR2852143B1 (fr) 2003-03-04 2003-03-04 Procede de traitement preventif de la couronne d'une tranche multicouche
US10/784,040 US6939783B2 (en) 2003-03-04 2004-02-20 Preventive treatment method for a multilayer semiconductor wafer
JP2006506406A JP4855245B2 (ja) 2003-03-04 2004-03-01 多層ウェハのリングの予防処理方法
PCT/IB2004/000940 WO2004079801A1 (fr) 2003-03-04 2004-03-01 Procede de traitement preventif pour la couronne d'une tranche multicouche
KR1020057016240A KR100806981B1 (ko) 2003-03-04 2004-03-01 다층웨이퍼 링의 예방처리방법
EP04715980A EP1599896B1 (fr) 2003-03-04 2004-03-01 Procédé de traitement préventif pour la couronne d'une tranche multicouche
CNB2004800059654A CN100490070C (zh) 2003-03-04 2004-03-01 对多层晶片的环圈的预防性处理工艺
TW093105459A TWI297176B (en) 2003-03-04 2004-03-03 Preventive treatment process for the ring of a multilayer wafer
US11/157,956 US7190029B2 (en) 2003-03-04 2005-06-22 Preventive treatment method for a multilayer semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0302623A FR2852143B1 (fr) 2003-03-04 2003-03-04 Procede de traitement preventif de la couronne d'une tranche multicouche

Publications (2)

Publication Number Publication Date
FR2852143A1 FR2852143A1 (fr) 2004-09-10
FR2852143B1 true FR2852143B1 (fr) 2005-10-14

Family

ID=32865218

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0302623A Expired - Lifetime FR2852143B1 (fr) 2003-03-04 2003-03-04 Procede de traitement preventif de la couronne d'une tranche multicouche

Country Status (8)

Country Link
US (2) US6939783B2 (fr)
EP (1) EP1599896B1 (fr)
JP (1) JP4855245B2 (fr)
KR (1) KR100806981B1 (fr)
CN (1) CN100490070C (fr)
FR (1) FR2852143B1 (fr)
TW (1) TWI297176B (fr)
WO (1) WO2004079801A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160042989A1 (en) * 2013-03-29 2016-02-11 Soitec Process for manufacturing a composite structure

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5519908B2 (ja) * 2004-11-08 2014-06-11 ブルーワー サイエンス アイ エヌ シー． 微細電子部品製造時に基板の外側エッジをコーティングする装置
JP2008526010A (ja) 2004-12-28 2008-07-17 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 低いホール密度を有する薄層を得るための方法
FR2880988B1 (fr) 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
FR2895563B1 (fr) 2005-12-22 2008-04-04 Soitec Silicon On Insulator Procede de simplification d'une sequence de finition et structure obtenue par le procede
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2943458B1 (fr) 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
FR2944645B1 (fr) 2009-04-21 2011-09-16 Soitec Silicon On Insulator Procede d'amincissement d'un substrat silicium sur isolant
KR101057192B1 (ko) * 2009-04-30 2011-08-16 주식회사 하이닉스반도체 노광 과정으로 웨이퍼 상에 패턴을 형성하는 방법
FR2957716B1 (fr) * 2010-03-18 2012-10-05 Soitec Silicon On Insulator Procede de finition d'un substrat de type semi-conducteur sur isolant

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086011A (en) * 1987-01-27 1992-02-04 Advanced Micro Devices, Inc. Process for producing thin single crystal silicon islands on insulator
US4795718A (en) * 1987-05-12 1989-01-03 Harris Corporation Self-aligned contact for MOS processing
FR2629636B1 (fr) * 1988-04-05 1990-11-16 Thomson Csf Procede de realisation d'une alternance de couches de materiau semiconducteur monocristallin et de couches de materiau isolant
JP2645478B2 (ja) * 1988-10-07 1997-08-25 富士通株式会社 半導体装置の製造方法
JPH04129267A (ja) * 1990-09-20 1992-04-30 Fujitsu Ltd 半導体基板およびその製造方法
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JPH07161948A (ja) * 1993-12-10 1995-06-23 Canon Inc 半導体基体及びその製造方法
US5723385A (en) * 1996-12-16 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd Wafer edge seal ring structure
JP3875375B2 (ja) * 1997-10-06 2007-01-31 株式会社ルネサステクノロジ 半導体装置の製造方法および半導体基板
JP3846657B2 (ja) * 1997-11-28 2006-11-15 株式会社Ｓｕｍｃｏ 貼り合わせ基板およびその製造方法
JPH11204452A (ja) * 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体基板の処理方法および半導体基板
JP3887973B2 (ja) * 1998-10-16 2007-02-28 信越半導体株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP2000299451A (ja) * 1999-04-15 2000-10-24 Matsushita Electric Works Ltd Ｓｏｉウェハおよびその製造方法
FR2797714B1 (fr) 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
KR100730806B1 (ko) * 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼
DE60029578T2 (de) * 1999-10-14 2007-07-26 Shin-Etsu Handotai Co., Ltd. Verbundscheiben-herstellungsmethode
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
JP2003224247A (ja) * 2002-01-29 2003-08-08 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハ及びｓｏｉウエーハの製造方法
JP2003309253A (ja) * 2002-02-18 2003-10-31 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハ及びｓｏｉウエーハの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160042989A1 (en) * 2013-03-29 2016-02-11 Soitec Process for manufacturing a composite structure

Also Published As

Publication number Publication date
EP1599896B1 (fr) 2012-11-14
KR100806981B1 (ko) 2008-02-25
KR20050109521A (ko) 2005-11-21
US20050230754A1 (en) 2005-10-20
US7190029B2 (en) 2007-03-13
CN1757097A (zh) 2006-04-05
TWI297176B (en) 2008-05-21
TW200501236A (en) 2005-01-01
EP1599896A1 (fr) 2005-11-30
JP4855245B2 (ja) 2012-01-18
WO2004079801A1 (fr) 2004-09-16
US6939783B2 (en) 2005-09-06
FR2852143A1 (fr) 2004-09-10
US20040197963A1 (en) 2004-10-07
WO2004079801A8 (fr) 2005-04-07
CN100490070C (zh) 2009-05-20
JP2006519504A (ja) 2006-08-24

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Legal Events

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Owner name: SOITEC, FR

Effective date: 20120423

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Year of fee payment: 14

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