FR2827078B1 - Procede de diminution de rugosite de surface - Google Patents

Procede de diminution de rugosite de surface

Info

Publication number
FR2827078B1
FR2827078B1 FR0108859A FR0108859A FR2827078B1 FR 2827078 B1 FR2827078 B1 FR 2827078B1 FR 0108859 A FR0108859 A FR 0108859A FR 0108859 A FR0108859 A FR 0108859A FR 2827078 B1 FR2827078 B1 FR 2827078B1
Authority
FR
France
Prior art keywords
atmosphere
wafer
free surface
surface roughness
reducing surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0108859A
Other languages
English (en)
Other versions
FR2827078A1 (fr
Inventor
Eric Neyret
Ludovic Ecarnot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0108859A priority Critical patent/FR2827078B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/FR2002/002341 priority patent/WO2003005434A2/fr
Priority to AU2002333957A priority patent/AU2002333957A1/en
Priority to EP20020782466 priority patent/EP1412972A2/fr
Priority to KR1020047000100A priority patent/KR100784581B1/ko
Priority to CNB028135512A priority patent/CN1321443C/zh
Priority to JP2003511301A priority patent/JP2004538627A/ja
Publication of FR2827078A1 publication Critical patent/FR2827078A1/fr
Priority to US10/750,443 priority patent/US6962858B2/en
Application granted granted Critical
Publication of FR2827078B1 publication Critical patent/FR2827078B1/fr
Priority to US11/189,899 priority patent/US7883628B2/en
Priority to US11/189,849 priority patent/US7749910B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
FR0108859A 2001-07-04 2001-07-04 Procede de diminution de rugosite de surface Expired - Lifetime FR2827078B1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FR0108859A FR2827078B1 (fr) 2001-07-04 2001-07-04 Procede de diminution de rugosite de surface
AU2002333957A AU2002333957A1 (en) 2001-07-04 2002-07-04 Method for reducing surface rugosity of a semiconductor slice
EP20020782466 EP1412972A2 (fr) 2001-07-04 2002-07-04 Procede de diminution de rugosite de surface
KR1020047000100A KR100784581B1 (ko) 2001-07-04 2002-07-04 표면 거칠기 감소 방법
CNB028135512A CN1321443C (zh) 2001-07-04 2002-07-04 降低表面粗糙度的方法
JP2003511301A JP2004538627A (ja) 2001-07-04 2002-07-04 表面しわを減少させる方法
PCT/FR2002/002341 WO2003005434A2 (fr) 2001-07-04 2002-07-04 Procede de diminution de la rugosite de surface d'une tranche semicondutrice
US10/750,443 US6962858B2 (en) 2001-07-04 2003-12-30 Method for reducing free surface roughness of a semiconductor wafer
US11/189,899 US7883628B2 (en) 2001-07-04 2005-07-27 Method of reducing the surface roughness of a semiconductor wafer
US11/189,849 US7749910B2 (en) 2001-07-04 2005-07-27 Method of reducing the surface roughness of a semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0108859A FR2827078B1 (fr) 2001-07-04 2001-07-04 Procede de diminution de rugosite de surface

Publications (2)

Publication Number Publication Date
FR2827078A1 FR2827078A1 (fr) 2003-01-10
FR2827078B1 true FR2827078B1 (fr) 2005-02-04

Family

ID=8865109

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0108859A Expired - Lifetime FR2827078B1 (fr) 2001-07-04 2001-07-04 Procede de diminution de rugosite de surface

Country Status (8)

Country Link
US (1) US6962858B2 (fr)
EP (1) EP1412972A2 (fr)
JP (1) JP2004538627A (fr)
KR (1) KR100784581B1 (fr)
CN (1) CN1321443C (fr)
AU (1) AU2002333957A1 (fr)
FR (1) FR2827078B1 (fr)
WO (1) WO2003005434A2 (fr)

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US7749910B2 (en) 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
US7883628B2 (en) 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2852143B1 (fr) 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
WO2005013318A2 (fr) * 2003-07-29 2005-02-10 S.O.I.Tec Silicon On Insulator Technologies Procede d’obtention d’une couche mince de qualite accrue par co-implantation et recuit thermique
WO2005024925A1 (fr) * 2003-09-05 2005-03-17 Sumco Corporation Procede de production d'une plaquette soi
JP4552857B2 (ja) * 2003-09-08 2010-09-29 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハおよびその製造方法
JP4619949B2 (ja) * 2003-12-03 2011-01-26 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ ウェハの表面粗さを改善する方法
FR2863771B1 (fr) * 2003-12-10 2007-03-02 Soitec Silicon On Insulator Procede de traitement d'une tranche multicouche presentant un differentiel de caracteristiques thermiques
JP4285244B2 (ja) 2004-01-08 2009-06-24 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの作製方法
FR2867607B1 (fr) * 2004-03-10 2006-07-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat pour la microelectronique, l'opto-electronique et l'optique avec limitaton des lignes de glissement et substrat correspondant
US7772088B2 (en) * 2005-02-28 2010-08-10 Silicon Genesis Corporation Method for manufacturing devices on a multi-layered substrate utilizing a stiffening backing substrate
US7642205B2 (en) 2005-04-08 2010-01-05 Mattson Technology, Inc. Rapid thermal processing using energy transfer layers
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
US20070029043A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US7427554B2 (en) * 2005-08-12 2008-09-23 Silicon Genesis Corporation Manufacturing strained silicon substrates using a backing material
WO2007080013A1 (fr) * 2006-01-09 2007-07-19 International Business Machines Corporation Procede et appareil de traitement de substrats semiconducteurs en tranches collees
CN100490860C (zh) * 2006-01-25 2009-05-27 余内逊 一种微米松花珍珠四女子益肝养颜口服液制备方法
US7863157B2 (en) 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
WO2007118121A2 (fr) 2006-04-05 2007-10-18 Silicon Genesis Corporation Procédé et structure conçus pour fabriquer des cellules photovoltaïques au moyen d'un processus de transfert de couche
FR2903809B1 (fr) 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
US8153513B2 (en) 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
WO2008082920A1 (fr) * 2006-12-28 2008-07-10 Memc Electronic Materials, Inc. Procédé de production de plaquettes lisses
JP5143477B2 (ja) * 2007-05-31 2013-02-13 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
JP5466410B2 (ja) * 2008-02-14 2014-04-09 信越化学工業株式会社 Ｓｏｉ基板の表面処理方法
KR20110115570A (ko) * 2008-11-26 2011-10-21 엠이엠씨 일렉트로닉 머티리얼즈, 인크. 절연체-상-실리콘 구조의 가공 방법
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
US9560953B2 (en) 2010-09-20 2017-02-07 Endochoice, Inc. Operational interface in a multi-viewing element endoscope
CN103835000A (zh) * 2012-11-20 2014-06-04 上海华虹宏力半导体制造有限公司 一种高温改善多晶硅表面粗糙度的方法
CN103065956B (zh) * 2012-12-27 2015-02-25 南京大学 一种实现硅表面结构平滑的方法与设备
FR3046877B1 (fr) * 2016-01-14 2018-01-19 Soitec Procede de lissage de la surface d'une structure
CN109346562A (zh) * 2018-08-30 2019-02-15 华灿光电（浙江）有限公司 一种发光二极管外延片的制备方法及发光二极管外延片
CN109706421B (zh) * 2019-03-07 2020-08-18 苏州微创关节医疗科技有限公司 制备锆及锆合金表面氧化陶瓷层的方法及应用

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Also Published As

Publication number Publication date
FR2827078A1 (fr) 2003-01-10
AU2002333957A1 (en) 2003-01-21
CN1524289A (zh) 2004-08-25
EP1412972A2 (fr) 2004-04-28
JP2004538627A (ja) 2004-12-24
US20040171257A1 (en) 2004-09-02
US6962858B2 (en) 2005-11-08
KR100784581B1 (ko) 2007-12-10
CN1321443C (zh) 2007-06-13
WO2003005434A3 (fr) 2003-11-06
WO2003005434A2 (fr) 2003-01-16
KR20040013106A (ko) 2004-02-11

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Legal Events

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Owner name: SOITEC, FR

Effective date: 20120423

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